68HC705JB3

68HC05JB3 FREESCALE | Alldatasheet

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ª Motorola, Inc., 1998 HC05JB3GRS/H REV 1 68HC05JB3 68HC705JB3 SPECIFICATION (General Release) November 5, 1998 Semiconductor Products Sector Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 i TABLE OF CONTENTS Section Page SECTION 1 GENERAL DESCRIPTION 1.4.1 V DD and V SS SECTION 2 MEMORY SECTION 3 CENTRAL PROCESSING UNIT SECTION 4 INTERRUPTS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 ii REV 1 TABLE OF CONTENTS Section Page SECTION 5 RESETS SECTION 6 LOW POWER MODES SECTION 7 INPUT/OUTPUT PORTS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 iii TABLE OF CONTENTS Section Page SECTION 8 MULTI-FUNCTION TIMER SECTION 9 16-BIT TIMER SECTION 10 UNIVERSAL SERIAL BUS MODULE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 iv REV 1 TABLE OF CONTENTS Section Page SECTION 11 OPTICAL INTERFACE SECTION 12 INSTRUCTION SET SECTION 13 ELECTRICAL SPECIFICATIONS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 v TABLE OF CONTENTS Section Page SECTION 14 MECHANICAL SPECIFICATIONS APPENDIX A MC68HC705JB3 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 vi REV 1 TABLE OF CONTENTS Section Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 vii LIST OF FIGURES Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 viii REV 1 LIST OF FIGURES Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 ix LIST OF TABLES Table Title Page 8-1 RTI and COP Rates at f OP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 x REV 1 LIST OF TABLES Table Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 GENERAL DESCRIPTION MOTOROLA REV 1 1-1 SECTION 1 GENERAL DESCRIPTION The MC68HC05JB3 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC05JB3 is specifically designed to be used in applications where a low speed (1.5Mbps) Universal Serial Bus (USB) interface is required.

1.1 FEATURES

• Industry standard M68HC05 CPU core
• Memory-mapped input/output (I/O) registers
• 2560 Bytes of user ROM
• 144 Bytes of user RAM (includes 64 byte stack)
• Fully compliant Low Speed USB with 3 Endpoints: – 1 Control Endpoint (2 8-byte buffer) – 2 Interrupt Endpoints (1 8-byte buffer shared)
• 3.3V dc output for USB pull-up resistors
• 19 Bidirectional I/O pins with the following features: – 17 I/Os have software programmable pull-down capability – 2 open-drain I/Os have software programmable pull-up, 25mA current sink capability – 4 I/Os with external interrupt capability – 8 I/Os (in 4 pairs) with programmable optical interface
• Multi-Function Timer (MFT)
• 16-bit Timer with 1 input capture and 1 output compare
• Low Voltage Reset (LVR)
• Computer Operating Properly (COP) Watchdog Reset
• Illegal Address Reset Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA GENERAL DESCRIPTION MC68HC05JB3 1-2 REV 1

• Power-Saving STOP and WAIT Modes
• Available in 20-pin PDIP , 20-pin SOIC, 28-pin PDIP , and 28-pin SOIC packages

1.2 MASK OPTIONS

The following mask options are available:

• External interrupt pins (IRQ, PA0 to PA3): [edge-triggered or edge-and-level-triggered]
• Port A, port B, and port C pull-down/pull-up resistors: [connected or disconnected]
• PA0-PA3 external interrupt capability: [enabled or disabled]
• OSC, crystal/ceramic resonator startup delay: [4064 or 224 internal bus cycles]
• Low Voltage Reset (LVR): [enabled or disabled]
• COP function of MFT: [enabled or disabled]

1.3 MCU STRUCTURE

shows the structure of MC68HC05JB3 MCU. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 GENERAL DESCRIPTION MOTOROLA REV 1 1-3 Figure 1-1. MC68HC05JB3 Block Diagram

144 Bytes RAM 2560 Bytes EPROM

DATA DIRECTION REG. A PORT B DATA DIRECTION REG. B CPU CONTROL ALU 68HC05 CPU ACCUM INDEX REG. CPU REGISTERS PROGRAM COUNTER COND CODE REG. 000 0 000 11 STK PNTR0 111HI NZC PA0 ‹ PA1 ‹ PA2 ‹ PA3 ‹ PA4 › PA5 › PA6 › PA7 › VDD VSS 3.3V RESET IRQ TCAP ´ OSC1 OSC2 › : 8mA current sink capability and optical interface ˆ : 25mA current sink, open-drained ‹ : External edge interrupt capability, with internal pull-up, slow transition O/P ´ : PB0 is shared with TCAP with Schmitt trigger input and optical interface PB0 ´ PB1 ˆ PB2 ˆ PB4 ˜ PB5 ˜ PB6 ˜ PB7 ˜ PORT C DATA DIRECTION REG. C PC0 ˜ † PC1 ˜ PC2 ˜ PC3 ˜ ˜ : Pins available in 28-pin package only ˜ †: PC0 shared with OCMP OCMP ˜ † Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA GENERAL DESCRIPTION MC68HC05JB3 1-4 REV 1 Figure 1-2. MC68HC05JB3 Pin Assignments

1.4 FUNCTIONAL PIN DESCRIPTION

The following paragraphs give a description of the general function of each pin assigned in Figure 1-2 1.4.1 V DD and V SS Power is supplied to the MCU through V DD and V SS . V DD is the positive supply, and V SS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency char- acteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.

1.4.2 OSC1, OSC2

The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The OSC1 and OSC2 pins can accept the following sets of components: 1. A crystal as shown in Figure 1-3 (a) 2. A ceramic resonator as shown in Figure 1-3 (a) 3. An external clock signal as shown in Figure 1-3 (b) PA6 PB7 PA5 PB4 PA7 PA3 PB5 PC2 PA2 PA1 RESET PA0 OSC1 OSC2 VSS PB2 IRQ PC0/OCMP PC1 3.3V VDD PB1 PB0/TCAP PB6 PC3 PA4

10 PA5IRQ

3.3V VDD PB0/TCAP PB1 20-pin package 28-pin package Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA GENERAL DESCRIPTION MC68HC05JB3 1-6 REV 1 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3 (b).This configuration is possible ONL Y when the crystal/ceramic resonator mask option is selected.

1.4.3 RESET

This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to V DD , when the power is removed. An internal pull-up is also connected between this pin and V DD . The RESET pin con- tains an internal Schmitt trigger to improve its noise immunity as an input. This pin is an output pin if LVR triggers an internal reset.

1.4.4 IRQ

This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to V DD for "wired-OR" operation, if desired. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. NOTE Each of the PA0 to PA3 I/O pins may be connected as an OR function with the IRQ interrupt function by a mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ pin. The edge or level sensitivity selected by a separate mask option for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal. 1.4.5 3.3V This is an output reference voltage nominally set at 3.3V dc.

1.4.6 D+ and D–

These two lines carry the USB differential data. For low speed device such as MC68HC05JB3, a 1.5 k W resistor is required to be connected across D– and 3.3V for proper signal termination.

1.4.7 PA0-PA7

These eight I/O lines comprise Port A. PA0 to PA7 are push-pull pins with pull- down devices. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 GENERAL DESCRIPTION MOTOROLA REV 1 1-7 PA0 to PA3 has external interrupt function (mask option) with schmitt trigger input circuit, and PA4 to PA7 has 8mA current sink capability. Port A can also be configured as the optical interface.

1.4.8 PB0-PB2, PB3-PB7

These seven I/O lines comprise Port B. The state of any pin is software program- mable and is configured as an input during power-on or reset. PB1 and PB2 are open-drain I/O lines with pull-up devices. PB0 (shared with TCAP) is a push-pull I/O line with pull-down device. PB1 and PB2 are also slow transition outputs, each has 25mA current sink capa- bility at V OL =0.5V. PB4-PB7 I/O lines are push-pull pins with pull-down devices, and are only avail- able in the 28-pin package.

1.4.9 PC0-PC3

These four I/O lines comprise Port C. The state of any pin is software programma- ble and all Port C lines are configured as inputs during power-on or reset. PC0 to PC3 are push-pull pins with pull-down devices. PC0 is also shared with the OCMP pin from the output compare function of the 16-bit timer. Port C is only available in the 28-pin package. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA GENERAL DESCRIPTION MC68HC05JB3 1-8 REV 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MEMORY MOTOROLA REV 1 2-1 SECTION 2 MEMORY The MC68HC05JB3 has 8k-bytes of addressable memory, with 64 bytes of I/O, 144 bytes of user RAM, and 2560 bytes of user ROM, as shown in Figure 2-1 Figure 2-1. MC68HC05JB3 Memory Map $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF $003F $0000 $1FF6 $1FF3 $1FF4 $1FF5 $1FF2 $1FF1 Reserved USB Vector (Low Byte) Timer1 Vector (Low Byte) USB Vector (High Byte) Timer1 Vector (High Byte) MFT Vector (Low Byte) MFT Vector (High Byte) Reserved $1FF0 Reserved Reserved IRQ Vector (High Byte) IRQ Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) I/O Registers

64 Bytes

$0000 $003F $0040 $006F Unused

48 Bytes

144 Bytes

64 Byte Stack

$0070 $00C0 $00FF $0100 $13FF Unused

4864 Bytes

$1400 $1DFF $1E00 $1FEF User ROM

2560 Bytes

496 Bytes

16 Bytes

$1FF0 $1FFF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MEMORY MC68HC05JB3 2-2 REV 1

2.1 I/O AND CONTROL REGISTERS

The I/O and Control Registers reside in locations $0000 to $003F . The bit assign- ments for each register are shown in Figure 2-2 Figure 2-3 Figure 2-4 , and Figure 2-5 . Reading from unused bits will return unknown states, and writing to unused bits will be ignored.

2.2 RAM

The user RAM consists of 144 bytes (including the stack) at locations $0080 to $012F . The stack begins at address $00FF and proceeds down to $00C0. Using the stack area for data storage or temporary work locations requires care to pre- vent it from being overwritten due to stacking from an interrupt or subroutine call.

2.3 ROM

There are a total of 3k-bytes of ROM on chip. This includes 2560 bytes of user ROM with locations $1400 to $1DFF for user program storage and 16 bytes for user vectors at locations $1FF0 to $1FFF . Also, 496 bytes of Self-check ROM on chip at locations $1E00 to $1FEF . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MEMORY MOTOROLA REV 1 2-3

2.4 I/O REGISTERS SUMMARY

ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0000 Port A Data R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0PORTA W $0001 Port B Data R PB7 PB6 PB5 PB4 PB2 PB1 PB0PORTB W $0002 Port C Data R PC3 PC2 PC1 PC0PORTC W $0003 Unused R W $0004 Port A Data Direction R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0DDRA W $0005 Port B Data Direction R DDRB7 DDRB6 DDRB5 DDRB4 SLOWE DDRB2 DDRB1 DDRB0DDRB W $0006 Port C Data Direction R OCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0DDRC W $0007 Unused R W $0008 MFT Ctrl/Status R TOF RTIF TOFE RTIE 00 RT1 RT0TCSR W TOFR RTIFR $0009 MFT Counter R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 TCNT W $000A IRQ Control/Status R IRQE 0 0 0 IRQF 0 0 IRQPUICSR W IRQR $000B Unused R W $000C Unused R W $000D Unused R W $000E Optical Interface En. R TCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0OIER W $000F Port C Pull-down/up R PDURC W PDRC3 PDRC2 PDRC1 PDRC0 unused bits reserved bits Figure 2-2. MC68HC05JB3 I/O Registers $0000-$000F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MEMORY MC68HC05JB3 2-4 REV 1 ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0010 Port A Pull-down/up R PDURA W PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0 $0011 Port B Pull-down/up R PDURB W PDRB7 PDRB6 PDRB5 PDRB4 PURB2 PURB1 PDRB0 $0012 Timer1 Control R ICIE OCIE TOIE 000 IEDG 0 TCR W $0013 Timer1 Status R ICF OCF TOF 00000 TSR W $0014 Input Capture MSB R ICH7 ICH6 ICH5 ICH4 ICH3 ICH2 ICH1 ICH0 ICH W $0015 Input Capture LSB R ICL7 ICL6 ICL5 ICL4 ICL3 ICL2 ICL1 ICL0 ICL W $0016 Output Compare MSB R OCH7 OCH6 OCH5 OCH4 OCH3 OCH2 OCH1 OCH0OCH W $0017 Output Compare LSB R OCL7 OCL6 OCL5 OCL4 OCL3 OCL2 OCL1 OCL0OCL W $0018 Timer1 Counter MSB R TCNTH7 TCNTH6 TCNTH5 TCNTH4 TCNTH3 TCNTH2 TCNTH1 TCNTH0 TCNTH W $0019 Timer1 Counter LSB R TCNTL7 TCNTL6 TCNTL5 TCNTL4 TCNTL3 TCNTL2 TCNTL1 TCNTL0 TCNTL W $001A Alter. Counter MSB R ACNTH7 ACNTH6 ACNTH5 ACNTH4 ACNTH3 ACNTH2 ACNTH1 ACNTH0 ACNTH W $001B Alter. Counter LSB R ACNTL7 ACNTL6 ACNTL5 ACNTL4 ACNTL3 ACNTL2 ACNTL1 ACNTL0 ACNTL W $001C Unused R W $001D Unused R W $001E Unused R W $001F Unused R W unused bits reserved bits Figure 2-3. MC68HC05JB3 I/O Registers $0010-$001F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MEMORY MOTOROLA REV 1 2-5 ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0020 USB Endpoint 0 Data 0 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R0 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0021 USB Endpoint 0 Data 1 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R1 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0022 USB Endpoint 0 Data 2 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R2 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0023 USB Endpoint 0 Data 3 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R3 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0024 USB Endpoint 0 Data 4 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R4 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0025 USB Endpoint 0 Data 5 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R5 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0026 USB Endpoint 0 Data 6 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R6 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0027 USB Endpoint 0 Data 7 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UD0R7 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 $0028 USB Endpoint 1 Data 0 R UD1R0 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $0029 USB Endpoint 1 Data 1 R UD1R1 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002A USB Endpoint 1 Data 2 R UD1R2 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002B USB Endpoint 1 Data 3 R UD1R3 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002C USB Endpoint 1 Data 4 R UD1R4 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002D USB Endpoint 1 Data 5 R UD1R5 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002E USB Endpoint 1 Data 6 R UD1R6 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002F USB Endpoint 1 Data 7 R UD1R7 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 unused bits reserved bits Figure 2-4. MC68HC05JB3 I/O Registers $0020-$002F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 CENTRAL PROCESSING UNIT MOTOROLA REV 1 3-1 SECTION 3 CENTRAL PROCESSING UNIT The MC68HC05JB3 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF . All other instructions and registers behave as described in this chapter.

3.1 REGISTERS

The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1 and are described in the following paragraphs. Figure 3-1. MC68HC05 Programming Model CONDITION CODE REGISTER I ACCUMULATOR A INDEX REGISTER X 452 3 STACK POINTER SP 14 815 9 1213 10 11 PC CC111 1100000000 PROGRAM COUNTER H NZC HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA CENTRAL PROCESSING UNIT MC68HC05JB3 3-2 REV 1

3.2 ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device.

3.3 INDEX REGISTER (X)

The index register shown in Figure 3-1 is an 8-bit register that can perform two functions:

• Indexed addressing
• Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register content to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register content to a 16-bit immediate value. The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device.

3.4 STACK POINTER (SP)

The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF . The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations.

3.5 PROGRAM COUNTER (PC)

The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 CENTRAL PROCESSING UNIT MOTOROLA REV 1 3-3 Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

3.6 CONDITION CODE REGISTER (CCR)

The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register.

3.6.1 Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.

3.6.2 Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions.

3.6.3 Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag.

3.6.4 Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA CENTRAL PROCESSING UNIT MC68HC05JB3 3-4 REV 1

3.6.5 Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INTERRUPTS MOTOROLA REV 1 4-1 SECTION 4 INTERRUPTS The MCU can be interrupted in six different ways:

• Non-maskable Software Interrupt Instruction (SWI)
• External Asynchronous Interrupt (IRQ)
• External Interrupt via IRQ on PA0-PA3 (mask option)
• USB Interrupt
• Timer1 Interrupt (16-bit Timer)
• Multi-Function Timer Interrupt

4.1 INTERRUPT VECTORS

Table 4-1. Reset/Interrupt Vector Addresses Function Source Control Bit Global Hardware Mask Local Software Mask Priority (1 = Highest) Vector Address Reset Power-On Logic RESET Pin Low Voltage Reset Illegal Address Reset COP Watchdog Software Interrupt (SWI) User Code — — — Same Priority As Instruction$1FFC–$1FFD External Interrupt (IRQ) IRQ Pin — I Bit IRQE Bit 2 $1FFA–$1FFB USB Interrupts TXD0F TXD1F RESUMP — I Bit TXD0IE TXD1IE 3 $1FF8–$1FF9 Timer1 Interrupts ICF Bit OCF Bit TOF Bit — I Bit ICIE Bit OCIE Bit TOIE Bit 4 $1FF6–$1FF7 MFT Interrupts CTOF Bit RTIF Bit — I Bit CTOFE Bit RTIE Bit 5 $1FF4–$1FF5 Reserved $1FF2–$1FF3 Reserved $1FF0–$1FF1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INTERRUPTS MC68HC05JB3 4-2 REV 1 NOTE If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit.

4.2 INTERRUPT PROCESSING

The CPU does the following actions to begin servicing an interrupt:

• Stores the CPU registers on the stack in the order shown in Figure 4-1.
• Sets the I bit in the condition code register to prevent further interrupts.
• Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1. The return from interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt are shown in the flow chart in Figure 4-2. $0020 (BOTTOM OF RAM) $0021 $00BE $00BF $00C0 (BOTTOM OF STACK) $00C1 $00C2 UNSTACKING ORDER ß n CONDITION CODE REGISTER 5 1 n+1 ACCUMULATOR 4 2 n+2 INDEX REGISTER 3 3 n+3 PROGRAM COUNTER (HIGH BYTE) 2 4 n+4 PROGRAM COUNTER (LOW BYTE) 1 5 Ý STACKING $00FD ORDER $00FE $00FF TOP OF STACK (RAM) Figure 4-1. Interrupt Stacking Order Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INTERRUPTS MOTOROLA REV 1 4-3 Figure 4-2. Interrupt Flowchart NO EXTERNAL INTERRUPT? I BIT SET? FROM RESET YES YES CLEAR IRQ LATCH. NO EXECUTE INSTRUCTION. UNSTACK CCR, A, X, PCH, PCL. FETCH NEXT INSTRUCTION. STACK PCL, PCH, X, A, CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. USB INTERRUPT? YES NO TIMER1 INTERRUPT? YES NO MFT INTERRUPT? YES NO SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES NO Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INTERRUPTS MC68HC05JB3 4-4 REV 1

4.3 RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-2. A low level input on the RESET pin or an internally generated RST signal causes the program to vector to its start- ing address which is specified by the contents of memory locations $1FFE and $1FFF. The I-bit in the condition code register is also set.

4.4 SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is exe- cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter- rupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address is specified by the con- tents of memory locations $1FFC and $1FFD.

4.5 HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware inter- rupts which are explained in the following sections.

4.5.1 External Interrupt IRQ

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ logic is shown in Figure 4-3. The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the four lower Port-A pins (PA0 to PA3) to act as other IRQ interrupt sources. Refer to Figure 4-3 for the following descriptions. IRQ interrupt source comes from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on any falling edge of PA0-3 pins if PA0-3 interrupts have been enabled. If ‘edge-only’ sensitivity is chosen by a mask option, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Falling edge on the IRQ pin. 2. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option). If level sensitivity is chosen, the active high state of the signal to the clock input of the IRQ latch can also activate an IRQF flag which creates an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensi- tive to the following cases: 1. Low level on the IRQ pin. 2. Falling edge on the IRQ pin. 3. Low level on any PA0-PA3 pin with IRQ enabled (via mask option). 4. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INTERRUPTS MOTOROLA REV 1 4-5 The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQR acknowledge bit in the ICSR. As long as the output state of the IRQF flag bit is active the CPU will continuously re-enter the IRQ interrupt sequence until the active state is removed or the IRQE enable bit is cleared. Figure 4-3. External Interrupt (IRQ) Logic

4.5.2 IRQ Control/Status Register (ICSR) - $0A

The IRQ interrupt function is controlled by the ICSR located at $000A. All unused bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ICSR R IRQE 0 0 0 IRQF 0 0 IRQPU$000A W IRQR reset: 10000000 Figure 4-4. IRQ Control and Status Register (ICSR) IRQ IRQ LATCH VDD RST IRQ VECTOR FETCH IRQ STATUS/CONTROL REGISTER EXTERNAL INTERRUPT REQUEST IRQE IRQF IRQR INTERNAL DATA BUS TO BIH & BIL INSTRUCTION PROCESSING R IRQ Level (Mask Option) PA0 PA1 PA2 PA3 Port A External Interrupt (Mask Option) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INTERRUPTS MC68HC05JB3 4-6 REV 1 IRQPU — IRQ pin PUll-up resistor enable This bit enables/disables the internal pull-up resistor on the IRQ pin. 1 = Internal pull-up resistor in IRQ pin enabled. 0 = Internal pull-up resistor in IRQ pin disabled. IRQR — IRQ Interrupt Acknowledge This write-only bit clears an IRQ interrupt by clearing the IRQ latch, and hence the IRQF bit. The IRQR bit will always read as a logic zero. 1 = Clears IRQ interrupt request (clears IRQF). 0 = No effect. IRQF — IRQ Interrupt Request Flag Writing to the IRQF flag bit will have no effect on it. If the additional setting of IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains set the CPU will re-enter the IRQ interrupt sequence continuously until either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is cleared by reset. 1 = Indicates that an IRQ request is pending. 0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is pending. The IRQF flag bit can be cleared by writing a logic one to the IRQR acknowledge bit to clear the IRQ latch and also conditioning the external IRQ sources to be inactive (if the level sensitive interrupts are enabled via mask option). Doing so before exiting the service routine will mask out additional occurrences of the IRQF . IRQE — IRQ Interrupt Enable The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt sequence. 1 = Enables IRQ interrupt, that is, the IRQF flag bit can generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I-bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set in order to allow the external IRQ to exit these modes. 0 = The IRQF flag bit cannot generate an interrupt sequence.

4.5.3 Port A External Interrupts (PA0-PA3, by mask option)

The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins if enabled by a single mask option. If enabled, the lower four bits of Port A can activate the IRQ interrupt function, and the interrupt operation will be the same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt sources are also controlled by the IRQE enable bit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INTERRUPTS MOTOROLA REV 1 4-7 NOTE The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 to PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs. NOTE If enabled, the PA0 to PA3 pins will cause an IRQ interrupt only when the corresponding pin is configured as input.

4.5.4 Timer1 Interrupt (TIMER1)

The TIMER1 interrupt is generated by the 16-bit timer when either an overflow or an input capture or output compare has occurred as described in the section on 16-bit timer. The interrupt flags and enable bits for the Timer1 interrupts are located in the Timer1 Control & Status Register (TSR) located at $0012, $0013. The I-bit in the CCR must be clear in order for the TIMER1 interrupt to be enabled. Either of these three interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $1FF6 and $1FF7.

4.5.5 USB Interrupt (USB)

The USB interrupt is generated by the USB module as described in the section on Universal Serial Bus. The interrupt enable bits for the USB interrupt are located at bit3-bit2 of UIR0 register and bit3-bit2 of UIR1 register. Also Once the device goes into Suspend Mode, any bus activities will cause the USB to generate an interrupt to CPU to come out from the Suspend mode. The I-bit in the CCR must be clear in order for the USB interrupt to be enabled. Either of these two interrupts will vector to the same interrupt service routine located at the address specified by the con- tents of memory locations $1FF8 and $1FF9.

4.5.6 MFT Interrupt (MFT)

The MFT interrupt is generated by the MFT module as described in the section on Multi-function Timer. These interrupts will vector to the same interrupt service rou- tine located at the address specified by the contents of memory locations $1FF4 and $1FF5. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INTERRUPTS MC68HC05JB3 4-8 REV 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA RESETS MC68HC05JB3 5-2 REV 1

5.1 POWER-ON RESET

A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A 224tCYC or 4064tCYC (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of the multiple tCYC time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic one.

5.2 EXTERNAL RESET

A logic zero applied to the RESET pin for 1.5tCYC generates an external reset. This pin is connected to a Schmitt trigger input gate to provide and upper and lower threshold voltage separated by a minimum amount of hysteresis. The exter- nal reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripher- als. The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This RESET pulldown device will only be asserted for 3 to 4 cycles of the internal clock, fOP, or as long as the internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will not be turned on. NOTE Do not connect the RESET pin directly to VDD , as this may overload some power supply designs when the internal pulldown on the RESET pin activates.

5.3 INTERNAL RESETS

The five internally generated resets are the initial power-on reset function, the COP Watchdog timer reset, the low voltage reset, and the illegal address detector. Only the COP Watchdog timer reset, low voltage reset and illegal address detec- tor will also assert the pulldown device on the RESET pin for the duration of the reset function or 3 to 4 internal clock cycles, whichever is longer.

5.3.1 Power-On Reset (POR)

The internal POR is generated on power-up to allow the clock oscillator to stabi- lize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 224 or 4064 (224 or 4064 is selected by mask option) internal processor bus clock cycles after the oscillator becomes active. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 RESETS MOTOROLA REV 1 5-3 The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 224 or 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD .

5.3.2 USB Reset

The USB reset is generated by a detection on the USB bus reset signal. For MC68HC05JB3, seeing a single-end zero on its upstream port for 4 to 8 bit times will set RSTF bit in UIR0 register. The detections will also generate the RST signal to reset the CPU and other peripherals in the MCU.

5.3.3 Computer Operating Properly (COP) Reset

The COP watchdog is enabled by a mask option. A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic zero to the COPC bit of the COP register at location $1FF0. COPC — COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on system. 0 = Reset COP watchdog timer. The COP Watchdog reset will assert the pull-down device to pull the RESET pin low for one cycle of the internal bus clock. Refer to section on Multi-Function Timer for detail on COP watchdog timeout peri- ods.

5.3.4 Low Voltage Reset (LVR)

The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low one cycle of the internal bus clock. The Low Volt- age Reset circuit is enabled by a mask option. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COPR R 00000000 $1FF0 W COPC reset: UUUUUUU0 U = UNAFFECTED BY RESET Figure 5-2. COP Watchdog Register (COPR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA RESETS MC68HC05JB3 5-4 REV 1

5.3.5 Illegal Address Reset

An opcode fetch from an address that is not in the ROM or the RAM generates an illegal address reset. The illegal address reset will assert the pull-down device to pull the RESET pin low for 3 to 4 cycles of the internal bus clock. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 LOW POWER MODES MOTOROLA REV 1 6-1 SECTION 6 LOW POWER MODES There are three modes of operation that reduce power consumption:

• Stop mode
• Wait mode
• Data retention mode Figure 6-1 shows the sequence of events in Stop and Wait modes. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA LOW POWER MODES MC68HC05JB3 6-2 REV 1 Figure 6-1. STOP and WAIT Flowchart STOP EXTERNAL RESET? EXTERNAL INTERRUPT? NO NO START STABILIZATION DELAY YES YES END OF STABILIZATION DELAY? YES NO WAIT RESTART INTERNAL PROCESSOR CLOCK 1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR. NO EXTERNAL RESET? YES NO EXTERNAL INTERRUPT? YES NO USB INTERRUPT? YES RESET OR NO YES YES NO STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET START -UP DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR, SET IRQE IN ICSR USB INTERRUPT NO YES IRQ OR RESET? RESTART EXTERNAL OSCILLATOR, IRQ TIMER1 INTERRUPT? INTERNAL MFT INTERRUPT? INTERNAL EXTERNAL OSCILLATOR ACTIVE, INTERNAL TIMER CLOCK ACTIVE STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR, SET IRQE IN ICSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 LOW POWER MODES MOTOROLA REV 1 6-3

6.1 STOP MODE

STOP mode is entered by executing the STOP instruction. This is the lowest power consumption mode of the MCU. In the STOP Mode the internal oscillator is turned off, halting all internal processing. Execution of the STOP instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled. All other registers, including the other bits in the TCSR, and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP Mode by an IRQ external interrupt or a USB coming out from Suspend Mode Interrupt (Bus activity detection) or an exter- nally generated RESET, USB Reset or an LVR reset. When exiting the STOP Mode the internal oscillator will resume after a 224 or 4064 internal processor clock cycle oscillator stabilization delay.

6.2 WAIT MODE

WAIT mode is entered by executing the WAIT instruction. This places the MCU in a low-power mode, which consumes more power than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/ Status Register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. The WAIT Mode may be exited when an external IRQ, USB, Timer1 or MFT inter- rupt, an LVR reset, USB reset or an external RESET occurs.

6.3 DATA-RETENTION MODE

The Data-Retention mode is only available if the Low Voltage Reset function (mask option) is not enabled. In the data retention mode, the MCU retains RAM contents and CPU register con- tents at VDD voltages as low as 2Vdc. The data retention feature allows the MCU to remain in a low power consumption state during which it retains data, but the CPU cannot execute instructions. The RESET pin must be held low during data- retention mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA LOW POWER MODES MC68HC05JB3 6-4 REV 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLA REV 1 7-1 SECTION 7 INPUT/OUTPUT PORTS In normal operating mode there are 19 usable bidirectional I/O lines arranged as one 8-bit I/O port (Port-A), one 7-bit I/O port (Port-B), and one 4-bit I/O port (Port C). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). The eight port pins, PB4-PB7 and PC0-PC3, are only available on the 28-pin version of the device. Table 7-1 shows a summary of Port-A, Port-B, and Port-C functions.

7.1 PORT-A

Port-A is an 8-bit bi-directional port. The Port-A data register is at $0000 and the data direction register (DDRA) is at $0004. Reset does not affect the data regis- ters, but clears the data direction registers, thereby returning the port pins to inputs. Writing a ‘1’ to a DDR bit sets the corresponding port bit to output mode. All Port-A pins have programmable pull-down resistors. PA4 to PA7 each has 8mA current sink capability. The table below summarizes the pin configurations for Port-A. Table 7-1. Summary of Port Pin Functions Port Pins Internal Resistor Configuration Current Drive/Sink Additional Features PA0-PA3 Pull-down1 1.6mA sink External Interrupt2 Optical Interface PA4-PA7 8mA sink PB0 1.6mA sink shared with TCAP PB1, PB2 Pull-up 1 25mA sink, open-drain Slow Transition Output PB4-PB7 Pull-down1 1.6mA sink Pins available only in 28-pin devicePC0 shared with OCMP PC1-PC3 Notes: 1. A pull-up/pull-down resistor is enabled by setting the corresponding register bit to “0” and the port pull-up/down mask option is selected. 2. Selected by mask option. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INPUT/OUTPUT PORTS MC68HC05JB3 7-2 REV 1

7.1.1 Port-A Data Register

7.1.2 Port-A Data Direction Register

DDRAx — PAx Data Direction 1 = Port pin set as output. 0 = Port pin set as input.

7.1.3 Port-A Pull-down/up Register

With the pull-up/down mask option selected, each pin in Port-A has an internal pull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit in the Port-A pull-down/up control register (PDURA) at location $0010. PDRAx — PAx Pin Pull-down enable 1 = Internal pull-down disabled. 0 = Internal pull-down enabled.

7.1.4 PA0-PA3 Interrupts

A mask option selects the capability for PA0-PA3 to be used as external IRQ inter- rupt inputs. These four I/O pins also have schmitt trigger input circuits. See INTERRUPTS section for detail. PDRAx DDRAx Pin Configuration 0 0 Input with pull-down 0 1 Output Push/Pull 1 0 Input 1 1 Output Push/Pull BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PORTA R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0$0000 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0$0004 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDURA R $0010 W PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 reset: 00000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLA REV 1 7-3

7.1.5 PA0-PA7 Optical Interface

Port-A is programmable to use as ports for the optical interface. See OPTICAL INTER FACE section for details.

7.2 PO R T-B

Port-B is a 7-bit bi-directional port. The Port-B data register is at $0001 and the data direction register (DDRB) is at $0005. Reset does not affect the data regis- ters, but clears the data direction registers, thereby returning the port pins to inputs. W riting a ‘one’ to a DDR bit sets the corresponding port bit to output mode. PB4-PB7 are only available on the 28-pin version of the device. All Port-B pins have programmable pull-down or pull-up resistors. PB1 and PB2 each has 25mA current sink capability. PB0 is also used as the 16-timer TCAP input pin. When configured as output, the input to the input capture will be permanently tied “low ” and no input capture can be generated. The table below summa rizes the pin configurations for Port-B.

7.2.1 Port-B Data Register

7.2.2 Port-B Data Direction Register

DDRBx — PBx Data Direction 1 = Port pin set as output. 0 = Port pin set as input. PDRBx/PURBx DDRBx Pin Configuration

00 PB0, PB4-PB7: Input with pull-down

PB1, PB2: Input with pull-up

01 PB0, PB4-PB7: Output Push-Pull

PB1, PB2: Output Open-drain with pull-up 1 0 Input

11 PB0, PB4-PB7: Output Push-Pull

PB1, PB2: Output Open-drain BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PORTB R PB7 PB6 PB5 PB4 0 PB2 PB1 PB0$0001 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DDRB R DDRB7 DDRB6 DDRB5 DDRB4 SLOWE DDRB2 DDRB1 DDRB0$0005 W reset: 00000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INPUT/OUTPUT PORTS MC68HC05JB3 7-4 REV 1 SLOWE — Slow Transition Enable See Section 7.2.4 for details. 1 = Enable slow falling-edge output transition feature on PB1 and PB2. 0 = Disable slow falling-edge output transition feature on PB1 and PB2.

7.2.3 Port-B Pull-down/up Register

With the pull-up/down mask option selected, PB0 and PB4-PB7 each has an inter- nal pull-down resistor, while PB1 and PB2 each has an internal pull-up resistor, which can be enabled by writing a ‘0’ to the corresponding bit in the Port-B pull-down/up control register (PDURB) at location $0011. PDRBx — PBx Pin Pull-down enable 1 = Internal pull-down disabled. 0 = Internal pull-down enabled. PURBx — PBx Pin Pull-up enable 1 = Internal pull-up disabled. 0 = Internal pull-up enabled.

7.2.4 PB1, PB2 Slow Transition Output

The slow transition output feature is enabled by setting the SLOWE bit in DDRB at $0005. PB2 — a high-to-low output transition is a sharp falling edge transition delayed by tCYC ÷ 2. PB1 — a high-to-low output transition is a slow falling edge (drops from 5.0V to 2.2V in 167ns typically at fOP =3MHz, with 50pF load) followed by a fast transition to VSS . The fast transition duration is depending on the strength of the output driver defined for each port. See Figure 7-1. Both PB1 and PB2 have 25mA current sink capability. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDURB R $0011 W PDRB7 PDRB6 PDRB5 PDRB4 PURB2 PURB1 PDRB0 reset: 00000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLA REV 1 7-5 Figure 7-1. PB1 Slow Falling-edge Output

7.3 PORT-C

Port-C is a 4-bit bi-directional port. The Port-C data register is at $0002 and the data direction register (DDRC) is at $0006. Reset does not affect the data regis- ters, but clears the data direction registers, thereby returning the port pins to inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode. All Port-C pins have programmable pull-down resistors, and are only available on the 28-pin version of the device. PC0 is also used as the 16-timer OCMP output pin. The table below summarizes the pin configurations for Port-A.

7.3.1 Port-C Data Register

7.3.2 Port-C Data Direction Register

PDRCx DDRCx Pin Configuration 0 0 Input with pull-down 0 1 Output Push-Pull 1 0 Input 1 1 Output Push-Pull BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PORTC R PC3 PC2 PC1 PC0$0002 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DDRC R OCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0$0006 W reset: 00000000 50pF 5.0V 165ns 330ns 2.2VOutput Driver Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INPUT/OUTPUT PORTS MC68HC05JB3 7-6 REV 1 DDRCx — PCx Data Direction 1 = Port pin set as output. 0 = Port pin set as input. VROFF — USB 3.3V Voltage Reference See USB section for details. 1 = Disable 3.3V regulator. 0 = Enables 3.3V regulator. OCMPO — OCMP Output Enable See 16-BIT TIMER section for details. 1 = PC0 is OCMP pin, OCF from 16-bit timer output compare. 0 = PC0 is standard I/O pin, from Port-C data register.

7.3.3 Port-C Pull-down/up Register

With the pull-up/down mask option selected, each pin in Port-C has an internal pull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit in the Port-C pull-down/up control register (PDURC) at location $000F . PDRCx — PCx Pin Pull-down Enable 1 = Internal pull-down disabled. 0 = Internal pull-down enabled. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDURC R $000F W PDRC3 PDRC2 PDRC1 PDRC0 reset: 00000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MULTI-FUNCTION TIMER MOTOROLA REV 1 8-1 SECTION 8 MULTI-FUNCTION TIMER The Multi-Function Timer (or Core Timer) module is a 15-stage ripple counter with Timer Over Flow (CTOF), Real Time Interrupt (RTI), and COP Watchdog function. Figure 8-1. Multi-Function Timer Block Diagram COP Watchdog RTI Select Circuit Overflow CircuitDetect fOP ÷22 ÷210 Internal Timer Clock (NTF1) CTOF RTIF CTOFE RTIE RT1 RT0 RTIFRCTOFR Timer Control & Status Register ($08) Timer Counter Register ($09) Interrupt Circuit Resetable Timer (÷8) 7-bit counter MCU Internal Bus to CPU interrupt ÷214÷215÷217 ÷216 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MULTI-FUNCTION TIMER MC68HC05JB3 8-2 REV 1

8.1 OVERVIEW

As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by four. NTF1 has the same phase and frequency as the processor bus clock, PH2, but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter Register (TCNT) at address $09. A timer overflow function is implemented on the last stage of this 8-bit counter, giving a possible interrupt rate of fOP ÷1024. The last stage of the 8-bit counter also drives a further 7-bit counter. The final four stages is used by the RTI circuit, giving possible RTI rates of fOP ÷214, 215, 216 or 217, selected by RT1 and RT0 (see Table 8-1). The RTI rate selector bits, and the RTI and CTOF enable bits and flags are located in the Timer Control and Status Register at location $08. The power-on cycle clears the entire counter chain and begins clocking the counter. After 224 or 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and nor- mal device operation will begin. If RESET is asserted at any time during operation the counter chain will be cleared.

8.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG

The COP Watchdog is enabled by a mask option. The COP Watchdog Timer function is implemented by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the nor- mal reset vector is fetched. Preventing a COP time-out is done by writing a “0” to bit-0 of address $1FF0. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared.

8.3 MFT REGISTERS

8.3.1 Timer Counter Register (TCNT) $09

The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP ÷4 and can be used for various functions including a software input capture. Extended time periods can be attained using the CTOF function to incre- ment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2. This register is cleared by reset. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MULTI-FUNCTION TIMER MOTOROLA REV 1 8-3 Figure 8-2. Timer Counter Register

8.3.2 Timer Control/Status Register (TCSR) $08

The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR follow- ing reset. Figure 8-3. Timer Control/Status Register (TCSR) RT0, RT1 — Real-Time Interrupt period select bits These two bits select the Real-Time Interrupt period and the COP Watchdog reset period. RTIFR — Real Time Interrupt Acknowledge The RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is unaf- fected by reset. Reading the RTIFR will always return a logical zero. 1 = Clears the RTIF flag bit. 0 = Does not clear the RTIF flag bit. CTOFR — Timer Overflow Acknowledge The CTOFR is an acknowledge bit that resets the CTOF flag bit. This bit is unaffected by reset. Reading the CTOFR will always return a logical zero. 1 = Clears the CTOF flag bit. 0 = Does not clear the CTOF flag bit. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCNT R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 $0009 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCSR R CTOF RTIF CTOFE RTIE 00 RT1 RT0$0008 W CTOFR RTIFR reset: 00000011 Table 8-1. RTI and COP Rates at fOP =3.0MHz Bus Frequency, fBUS =fOP =3.0 MHz RT1 RT0 Divide Ratio RTI Rate COP Reset Period (RTI · 8) 00 2 14 5.46ms 43.68ms 01 2 15 10.92ms 87.36ms 10 2 16 21.85ms 174.8ms 11 2 17 43.69ms 349.52ms Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MULTI-FUNCTION TIMER MC68HC05JB3 8-4 REV 1 RTIE — Real Time Interrupt Enable The RTIE is an enable bit that allows generation of a TIMER Interrupt by the RTIF bit. 1 = When set, the TIMER Interrupt is generated when the RTIF flag bit is set. 0 = When cleared, no TIMER interrupt caused by RTIF bit set will be generated. This bit is cleared by reset. CTOFE — Timer Overflow Enable The CTOFE is an enable bit that allows generation of a TIMER Interrupt upon overflow of the Timer Counter Register. 1 = When set, the TIMER Interrupt is generated when the CTOF flag bit is set. 0 = When cleared, no TIMER interrupt caused by CTOF bit set will be generated. This bit is cleared by reset. RTIF — Real Time Interrupt Flag The RTIF is a read-only flag bit. 1 = Set when the output of the chosen (1 of 4 selections) Real Time Interrupt stage goes active. A TIMER Interrupt request will be generated if RTIE is also set. 0 = Reset by writing a logical one to the RTIF acknowledge bit, RTIFR. Writing to the RTIF flag bit has no effect on its value. This bit is cleared by reset. CTOF — Timer Overflow Flag The CTOF is a read-only flag bit. 1 = Set when the 8-bit ripple counter rolls over from $FF to $00. A TIMER Interrupt request will be generated if CTOFE is also set. 0 = Reset by writing a logical one to the CTOF acknowledge bit, CTOFR. Writing to the CTOF flag bit has no effect on its value. This bit is cleared by reset.

8.4 OPERATION DURING STOP MODE

When STOP is exited by an external interrupt or an LVR reset or an external RESET , the internal oscillator will resume, followed by a 224 or 4064 internal pro- cessor oscillator stabilization delay.

8.5 COP CONSIDERATION DURING STOP MODE

In STOP mode, the clock to the Watchdog Timer is stopped and is therefore impossible to generate COP reset when in STOP mode. The COP function will resume 224 or 4064 cycles after exiting from STOP . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 16-BIT TIMER MOTOROLA REV 1 9-1 SECTION 9 16-BIT TIMER This 16-bit Programmable Timer (Timer1) has an Input Capture function and an Output Compare function. Figure 9-1 shows a block diagram of the 16-bit programmable timer. Figure 9-1. Programmable Timer Block Diagram IEDG ICIE OCIE TOIE TMRH ($0018) TMRL ($0019) 16-BIT COUNTER ‚ 4 INTERNAL (fOSC ‚ 2) TIMER CONTROL REGISTER TIMER REQUEST OVERFLOW (TOF) RESET CLOCK INTERRUPT ACRH ($001A) ACRL ($001B) 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) EDGE SELECT & DETECT ICF OCF TOF TIMER STATUS REGISTER IEDG ICF OCF $0012 $0013 INTERNAL DATA BUS LOGIC ICRH ($0014) ICRL ($0015) PC0/ OCMPMUX PORT-C LOGIC OCMPO PB0/ TCAP SIGNAL CONDITIONING TCMPE (bit7 at $0E) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-2 REV 1 The basis of the 16-bit Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a spe- cific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. Because the counter is 16 bits long and preceded by a fixed divide-by-four pres- caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4MHz crystal oscillator is 2 microsecond/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012 and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013.

9.1 TIMER REGISTERS (TMRH, TMRL)

The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 9-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 9-2. Programmable Timer Counter Block Diagram TOIE TMRH ($0018) TMR LSB 16-BIT COUNTER ‚ 4 INTERNAL (fOSC ‚ 2) TIMER CONTROL REG. TIMER REQUEST OVERFLOW (TOF) RESET CLOCK INTERRUPT TMRL ($0019) TOF TIMER STATUS REG. $0012 $0013 INTERNAL ($FFFC) DATA READ TMRH READ TMRL READ LATCH BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 16-BIT TIMER MOTOROLA REV 1 9-3 The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. The TMRL latch is a transparent read of the LSB until the a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter. NOTE To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMRH R TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0 $0018 W reset: 11111111 TMRL R TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0 $0019 W reset: 11111100 Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-4 REV 1

9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL)

The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 9-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF flag bit and Timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 9-4. Alternate Counter Block Diagram The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC. The ACRL latch is a transparent read of the LSB until the a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACRH R ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0 $001A W reset: 11111111 ACRL R ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0 $001B W reset: 11111100 Figure 9-5. Alternate Counter Registers (ACRH, ACRL) ACRH ($001A) TMR LSB 16-BIT COUNTER ‚ 4 INTERNAL (fOSC ‚ 2) RESET CLOCK ACRL ($001B) INTERNAL ($FFFC) DATA READ ACRH READ ACRL READ LATCH BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 16-BIT TIMER MOTOROLA REV 1 9-5 NOTE To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL.

9.3 INPUT CAPTURE REGISTERS

Figure 9-6. Timer Input Capture Block Diagram The input capture function is a technique whereby an external signal (connected to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi- ble to relate the timing of an external signal to the internal counter value, and hence to elapsed time. NOTE Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0 DDR or Data Register can cause an unwanted TCAP interrupt. This can be avoided by clearing the ICIE bit before changing the configuration of PB0, and clearing any pending interrupts before enabling ICIE. The signal on the TCAP pin is first directed to a schmitt trigger or a voltage comparator as shown in Figure 9-7. Setting the TCMPE bit to “1” will enable the comparator and the VDD /2 reference voltage. ICIE ICRH ($0014) 16-BIT COUNTER ‚ 4 INTERNAL (fOSC ‚ 2) TIMER CONTROL REG. TIMER REQUEST INPUT CAPTURE (ICF) RESET CLOCK INTERRUPT ICRL ($0015)ICF TIMER STATUS REG. $0012 $0013 INTERNAL ($FFFC) DATA READ ICRH READ ICRLLATCH BUS IEDG EDGE SELECT & DETECT LOGIC IEDG INTERNAL DATA BUS SIGNAL CONDITIONING PB0/ TCAP TCMPE (bit7 at $0E) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-6 REV 1 TCMPE — Timer Input Capture Comparator Enable 1 = Timer input capture comparator is selected. 0 = Timer input capture comparator schmitt trigger is selected. NOTE When the comparator and VDD /2 reference are enabled, PB0 pin will automatically becomes an input pin, irrespective of DDR setting. However, it is recommended to set PB0 as an input first (via DDR), before enabling the comparator. A read of PB0 will reflect the TCAP pin status, not the PB0 register bit. The comparator uses the VDD /2 reference as the compare voltage, resulting in a typical output as shown in Figure 9-8. Switching off the VDD /2 voltage reference by clearing TCMPE=0 will further save power when the MCU is in a low power mode. Figure 9-7. TCAP Input Signal Conditioning BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OIER R TCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0$000E W reset: 00000000 MUX PB0/ TCAP Voltage Reference VREF EN PB0 I/O PORT LOGIC TCMPE bit VDD ÷ 2 Schmitt Trigger Comparator To edge select and detect logic Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-8 REV 1 Reading the ICRH inhibits further captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does not inhibit transfer of the free-running counter. There is no conflict between read- ing the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. NOTE To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL.

9.4 OUTPUT COMPARE REGISTERS

The Output Compare function is a means of generating an interrupt when the 16- bit timer counter reaches a selected value as shown in Figure 9-10. Software writes the selected value into the output compare registers. On every fourth inter- nal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the output compare interrupt flag, OCF is set. A timer interrupt request to the CPU is generated if the output compare interrupt enable is set, i.e. OCIE=1. Port pin, PC0 is configured as the OCMP output pin when the OCMPO bit (bit7 at $06) is set to “1”. The OCMP output reflects the logic of the output compare inter- rupt flag, OCF , as shown in Figure 9-10. OCMPO — OCMP Output Enable 1 = PC0 is OCMP pin, OCF from 16-bit timer output compare. 0 = PC0 is standard I/O pin, from Port-C data register. Software can use the output compare register to measure time periods, to gener- ate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle. Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare flag bit (OCF). BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DDRC R OCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0$0006 W reset: 00000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-10 REV 1

9.5 TIMER CONTROL REGISTER (TCR)

The timer control register is shown in Figure 9-12 performs the following func- tions:

• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Control the active edge polarity of the TCAP signal on pin PB0/TCAP Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected. ICIE - INPUT CAPTURE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the PB0/ TCAP pin. Reset clears the ICIE bit. 1 = Input capture interrupts enabled. 0 = Input capture interrupts disabled. OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by a successful compare between the timer counter and the output compare registers. Reset clears the OCIE bit. 1 = Output compare interrupts enabled. 0 = Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled. 0 = Timer overflow interrupts disabled. ... ... BF ... ... SEI ... ... STA LDA STX ... ... CLI OCRH TSR OCRL DISABLE INTERRUPTS INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ENABLE INTERRUPTS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCR R ICIE OCIE TOIE 000 IEDG 0 $0012 W reset: 000000 Unaffected 0 Figure 9-12. Timer Control Register (TCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 16-BIT TIMER MOTOROLA REV 1 9-11 IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transi- tion on the TCAP pin triggers a transfer of the contents of the timer register to the input capture register. Reset has no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture. 0 = Negative edge (high to low transition) triggers input capture.

9.6 TIMER STATUS REGISTER (TSR)

The timer status register (TSR) shown in Figure 9-13 contains flags for the follow- ing events:

• An active signal on the PB0/TCAP pin, transferring the contents of the timer registers to the input capture registers.
• A match between the 16-bit counter and the output compare registers
• An overflow of the timer registers from $FFFF to $0000. Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits in the TSR. ICF - INPUT CAPTURE FLAG The ICF bit is automatically set when an edge of the selected polarity occurs on the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL, $0015) of the input capture registers. Reset has no effect on ICF . OCF - OUTPUT COMPARE FLAG The OCF bit is automatically set when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set, and then accessing the low byte (OCRL, $0017) of the output compare registers. Reset has no effect on OCF . OCF status will be latched to the output of OCMP (PC0 pin) if the OCMPO bit is set to “1” (bit7 at $06). TOF - TIMER OVERFLOW FLAG The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers. Reset has no effect on TOF . BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T S R R I C F O C F T O F 00000 $0013 W reset: U U U 00000 U = UNAFFECTED BY RESET Figure 9-13. Timer Status Registers (TSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA 16-BIT TIMER MC68HC05JB3 9-12 REV 1

9.7 TIMER OPERATION DURING WAIT MODE

During WAIT mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the MCU out of the WAIT mode.

9.8 TIMER OPERATION DURING STOP MODE

When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until the STOP mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If STOP mode is exited via an external reset (logic low applied to the RESET pin) the counter is forced to $FFFC. If a valid input capture edge occurs at the PB0/TCAP pin during the STOP mode the input capture detect circuitry will be armed. This action does not set any flags or “wake up” the MCU, but when the MCU does “wake up” there will be an active input capture flag (and data) from the first valid edge. If the STOP mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during the STOP mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-1 SECTION 10 UNIVERSAL SERIAL BUS MODULE This USB Module is designed for USB application in LS products. With minimized software effort, it can fully comply with USB LS device specification. See USB specification version 1.0 for the detail description of USB.

10.1 FEATURES

• Integrated 3.3 Volt Regulator with 3.3V Output Pin
• Integrated USB transceiver supporting Low Speed functions
• USB Data Control Logic – Packet decoding/generation – CRC generation and checking – NRZI encoding/decoding – Bit-stuffing
• USB reset support
• Control Endpoint 0 and Interrupt Endpoints 1 and 2
• Two 8-byte transmit buffers
• One 8-byte receive buffer
• Suspend and resume operations
• Remote Wake-up support
• USB generated interrupts
• Transaction interrupt driven
• Resume interrupt
• End of Packet interrupt
• STALL, NAK, and ACK handshake generation Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-2 REV 1

10.2 OVERVIEW

This section provides an overview of the Universal Serial Bus (USB) module in the MC68HC05JB3. This USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev 1.0. Three types of USB data transfers are supported: control, interrupt, and bulk (transmit only). Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2 can function as interrupt or bulk, but only in the transmit direction. A block diagram of the USB module is shown Figure 10-1. The USB module manages communications between the host and the USB function. The module is partitioned into four functional blocks. These blocks consist of a 3.3 volt regulator, a dual function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed in Section 10.4. Figure 10-1. USB Block Diagram USB CONTROL LOGIC TRANSCEIVER RCV VPIN VMIN VPOUT VMOUT REGULATOR 3.3V OUT CPU BUS USB REGISTERS USB Upstream Port Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-3

10.2.1 USB Protocol

Figure 10-2 shows the various transaction types supported by the MC68HC05JB3 USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later. Figure 10-2. Supported Transaction Types per Endpoint Each USB transaction is comprised of a series of packets. The MC68HC05JB3 USB module supports the packet types shown in Figure 10-3. Token packets are generated by the USB host and decoded by the USB device. Data and Handshake packets are both decoded and generated by the USB device depending on the type of transaction. SETUP IN OUT DATA0/1 DATA0 DATA1ACK DATA1 OUT ACKOUT DATA0 ACK ACK DATA0/1 ENDPOINT 0 TRANSACTIONS: Control Write Control Read No-Data Control ENDPOINTS 1 & 2 TRANSACTIONS: Interrupt Bulk Transmit IN ACK KEY: Unrelated Bus Traffic Host Generated Device Generated ACK SETUP OUT IN DATA0/1 DATA0 DATA1ACK DATA1 IN ACKIN DATA0 ACK ACK ACK SETUP INDATA0 DATA1ACK ACK DATA0/1IN ACK Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-4 REV 1 Figure 10-3. Supported USB Packet Types The following sections will give some detail on each segment used to form a complete USB transaction.

10.2.1.1 Sync Pattern

The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a synchronization pattern and is prefixed to each packet. This pattern is equivalent to a data pattern of seven 0’s followed by a 1 (0x80). Figure 10-4. Sync Pattern The start of a packet (SOP) is signaled by the originating port by driving the D+ and D– lines from the idle state (also referred to as the “J” state) to the opposite logic level (also referred to as the “K” state). This switch in levels represents the first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels for the start of packet and the sync pattern. Token Packet: IN OUT SYNC PID PID ADDR ENDP CRC5 EOP SETUP Data Packet: DATA0 SYNC PID PID DATA CRC5 EOP DATA1 0 - 8 bytes Handshake Packet: ACK NAK SYNC PID PID EOP STALL SYNC PATTERN PID0 PID1IdleNRZI Data Encoding Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-5 Figure 10-5. SOP, Sync Signaling and Voltage Levels

10.2.1.2 Packet Identifier Field

The Packet Identifier field is an eight bit number comprised of the four bit packet identification (PID) and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 10-1 shows the PID values for the supported packet types. Table 10-1. Supported Packet Identifiers

10.2.1.3 Address Field (ADDR)

The Address field is a seven bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MC68HC05JB3 USB device. PID Value PID Type %1001 IN Token %0001 OUT Token %1101 SETUP Token %0011 DATA0 Packet %1011 DATA1 Packet %0010 ACK Handshake %1010 NAK Handshake %1110 STALL Handshake END OF SYNC FIRST BIT OF PACKET SOPBUS IDLE VOH (min) VSE (max) VSE (min) VOL (min) VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-6 REV 1

10.2.1.4 Endpoint Field (ENDP)

The Endpoint field is a four bit number that is used to select a particular endpoint within a USB device. For the MC68HC05JB3, this will be a binary number between zero and two inclusive. Any other value will cause the transaction to be ignored.

10.2.1.5 Cyclic Redundancy Check (CRC)

Cyclic Redundancy Checks are used to verify the address and data stream of a USB transaction. This field is five bits wide for token packets and sixteen bits wide for data packets. CRCs are generated in the transmitter and sent on the USB data lines after both the endpoint field and the data field. Figure 10-6 shows how the five bit CRC value is calculated from the data stream and verified for the address and endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRC value is calculated and either transmitted or verified for the data packet of a given transaction. Figure 10-6. CRC Block Diagram for Address and Endpoint Fields 00 101 01100 next bit Data Stream Update every bit time Reset to ones at SOP Equal?Good CRC Bad CRC YN Expected Residual: Generator Polynomial: MUX 10 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-7 Figure 10-7. CRC Block Diagram for Data Packets

10.2.1.6 End Of Packet (EOP)

The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will be signaled by driving D+ and D– to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D– output drivers are placed in their high-impedance state. The bus termination resistors hold the bus in the idle state. Figure 10-8 shows the data signaling and voltage levels for an end of packet transaction. MUX next bit Input / Output Update every bit time Reset to ones at SOP Equal?Good CRC Bad CRC Y N Expected Residual: Generator Polynomial: Data Stream Output Data Stream CRC16 Transmitted MSB first after final data byte. TRANSMIT RECEIVE 0000010000 00010 1 0000010000 0 0110 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-8 REV 1 Figure 10-8. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. Figure 10-9. EOP Width Timing

10.2.2 Reset Signaling

A reset is signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The reset signaling is specified to be present for a minimum of 10 ms. An active device (powered and not in the suspend state) seeing a single-ended zero on its USB data inputs for more than 2.5ms may treat that signal as a reset, but must have interpreted the signaling as a reset within 5.5 ms. For a Low speed device, an SE0 condition between 4 and 8 low speed bit times represents a valid USB reset. A USB sourced reset will hold the MC68HC05JB3 in reset for the duration of the reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be set after the internal reset is removed (See Section 10.5.2 for more detail). After a reset is removed, the device will be in the attached, but not yet addressed or configured state (refer to Section 9.1 of the USB specification). The device must be able to accept a device address via a SET_ADDRESS command (refer to section 9.4 of the USB specification) no later than 10 ms after the reset is removed. BUS DRIVEN TO LAST BIT OF BUS IDLE EOP STROBE PACKET IDLE STATE BUS FLOATS VOH (min) VSE (max) VSE (min) VOL (min) VSS EOP WIDTH tPeriod DIFFERENTIAL DATA LINES DATA CROSSOVER LEVEL Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-9 Reset can wake a device from the suspended mode. A device may take up to 10ms to wake up from the suspended state.

10.2.3 Suspend

The MC68HC05JB3 supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3.0 ms. Entry into Suspend mode is controlled by the SUSPND bit in the USB Interrupt Register. Any low speed bus activity should keep the device out of the suspend state. Low speed devices are kept awake by periodic low speed EOP signals from the host. This is referred to as Low speed keep alive (refer to Section 11.2.5.1 of the USB specification). Firmware should monitor the EOPF flag and enter suspend mode by setting the SUSPND bit if an EOP is not detected for 3 ms. Per the USB specification, the MC68HC05JB3 is required to draw less than 500mA from the VDD supply when in the suspend state. This includes the current supplied by the voltage regulator to the 15 KW to ground termination resistors placed at the host end of the USB bus. This low current requirement means that firmware is responsible for entering STOP mode once the USB module has been placed in the suspend state.

10.2.4 Resume After Suspend

The MC68HC05JB3 can be activated from the suspend state by normal bus activity, a USB reset signal, or by a forced resume driven from the MC68HC05JB3.

10.2.4.1 Host Initiated Resume

The host signals resume by initiating resume signalling (“K” state) for at least 20 ms followed by a standard low speed EOP signal. This 20 ms ensures that all devices in the USB network are awakened. After resuming the bus, the host must begin sending bus traffic within 3 ms to prevent the device from re-entering suspend mode.

10.2.4.2 USB Reset Signalling

Reset can wake a device from the suspended mode. A device may take up to 10 ms to wake up from the suspended state.

10.2.4.3 Remote Wake-up

The MC68HC05JB3 also supports the remote wake-up feature. The firmware has the ability to exit suspend mode by signaling a resume state to the upstream Host or Hub. A non-idle state (“K” state) on the USB data lines is accomplished by asserting the FRESUM bit in the UCR1 register. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-10 REV 1 When using the remote wake-up capability, the firmware must wait for at least 5 ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. The FRESUM bit should be asserted to cause the resume state on the USB data lines for at least 10ms, but not more than 15ms. Note that the resume signalling is controlled by the FRESUM bit and meeting the timing specifications is dependent on the firmware. When FRESUM is cleared by firmware, the data lines will return to their high impedance state. Refer to Section 10.5.5 for more information about how the Force Resume (FRESUM) bit can be used to initiate the remote wake-up feature.

10.2.5 Low Speed Device

Externally, low speed devices are configured by the position of a pull-up resistor on the USB D– pin of the MC68HC05JB3. Low speed devices are terminated as shown in Figure 10-10 with the pull-up on the D– line. Figure 10-10. External Low Speed Device Configuration For low speed transmissions, the transmitter’s EOP width must be between 1.25ms and 1.50ms. These ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. A low speed receiver must accept a 670ns wide SE0 followed by a J transition as a valid EOP . An SE0 narrower than 330ns or an SE0 not followed by a J transition must be rejected as an EOP . An EOP between 330ns and 670ns may be rejected or accepted as above. Any SE0 that is 2.5ms or wider is automatically a reset.

10.3 CLOCK REQUIREMENTS

The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the oscillator circuits is the clock source for the USB module and requires that a 6 MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted frequency tolerance for low speed functions is approximately –1.5% (15000 ppm). This tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. The jitter in the low speed data rate must be less than 10 ns. This tolerance allows the use of resonators in low cost, low speed devices.

10.4 HARDWARE DESCRIPTION

The USB module as previously shown in Figure 10-1 contains four functional blocks: a 3.3 volt regulator, a LS USB transceiver, the USB control logic, and the USB registers. The following will detail the function of the regulator, transceiver and control logic. See Section 10.5 for the register discussion. 1.5KW 3.3V Regulator Out USB Low Speed Cable MC68HC05JB3 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-11

10.4.1 Voltage Regulator

The USB data lines are required by the USB Specification to have a maximum output voltage between 2.8V and 3.6V. The data lines are also required to have an external 1.5KW pullup resistor connected between a data line and a voltage source between 3.0V and 3.6V. Since the power provided by the USB cable is specified to be between 4.4V and 5.0V, an on-chip regulator is used to drop the voltage to the appropriate level for sourcing the USB transceiver and external pullup resistor. An output pin driven by the regulator voltage is provided to source the 1.5KW external resistor. Figure 10-11 shows the worst case electrical connection for the voltage regulator. This regulator can be switched off by user program to save power when the device is in suspend mode. Please note that if the regulator is off, the D– line should be tied to another voltage source with an external pull-up resistor. VROFF — USB 3.3V Voltage Reference The 3.3V Voltage Regulator for the USB transmitter and external D– pull-up can be switched off to reduce power consumption when device is in suspend mode. 1 = Disable 3.3V regulator. 0 = Enables 3.3V regulator. Figure 10-11. Regulator Electrical Connections BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DDRC R OCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0$0006 W reset: 00000000 LS Transceiver 3.3V R2 R2 R1 = 1.5KW –5% R2 = 15KW –5% Regulator USB Data Lines Host or Hub USB Cable 4.4V VROFF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-12 REV 1

10.4.2 USB Transceiver

The USB transceiver provides the physical interface to the USB D+ and D– data lines. The transceiver is composed of two parts: an output drive circuit and a differential receiver.

10.4.2.1 Output Driver Characteristics

The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable. The static output swing of the driver in its low state is below the VOL of 0.3 V with a 1.5 kW load to 3.6 V and in its high state is above the VOH of 2.8 V with a 15 kW load to ground. The output swings between the differential high and low state are well balanced to minimize signal skew. Slew rate control on the driver is used to minimize the radiated noise and cross talk. The driver’s outputs support three-state operation to achieve bi-directional half duplex operation. The driver can tolerate a voltage on the signal pins of –0.5 V to 3.8 V with respect to local ground reference without damage. 10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics The rise and fall time of the signals on this cable are greater than 75 ns to keep RFI emissions under FCC class B limits, and less than 300 ns to limit timing delays and signaling skews and distortions. The driver reaches the specified static signal levels with smooth rise and fall times, and minimal reflections and ringing when driving the cable. This driver is used only on network segments between low speed devices and the ports to which they are connected. Figure 10-12. Low Speed Driver Signal Waveforms

10.4.3 Receiver Characteristics

USB data transmission is done with differential signals. A differential input receiver is used to accept the USB data signal. A differential 1 on the bus is represented by D+ being at least 200 mV more positive than D– as seen at the receiver, and a differential 0 is represented by D– being at least 200 mV more positive than D+ as seen at the receiver. The signal cross over point must be between 1.3V and 2.0V. ONE BIT TIME (1.5 Mb/s) SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL REFLECTIONS AND RINGING VSE (min) VSE (max) VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-13 The receiver features an input sensitivity of 200 mV when both differential data inputs are in the range of 0.8 V to 2.5 V with respect to the local ground reference. This is called the common mode input voltage range. Proper data reception is also achieved when the differential data lines are outside the common mode range, as shown in Figure 10-13. The receiver can tolerate static input voltages between –0.5V to 3.8 V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines. Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range

10.4.3.1 Receiver Data Jitter

The data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. The more of the bit cell that any data edge can occupy and still be decoded, the more reliable the data transfer will be. Data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit cell from the nominal (centered) data edge position. Jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). The receive data jitter budget for low speed is given in the electrical section of the this specification. The specification includes the consecutive (next) and paired transition values for each source of jitter.

10.4.3.2 Data Source Jitter

The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time between any set of data transitions is N x TPERIOD – jitter time, where ‘N’ is the number of bits between the transitions and TPERIOD is defined as the actual period of the data rate. The data jitter is COMMON MODE INPUT VOLTAGE (VOLTS) 1.0 0.8 0.6 0.4 0.2 MINIMUM DIFFERENTIAL SENSITIVITY (VOLTS) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-14 REV 1 measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in Figure 10-14. Figure 10-14. Data Jitter For low speed transmissions, the jitter time for any consecutive differential data transitions must be within – 25 ns and within – 10 ns for any set of paired differential data transitions. These jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, and to noise and other random effects.

10.4.3.3 Data Signal Rise and Fall Time

The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time for the rising and falling edges of low speed signals is 75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into a capacitive load of 350 pF . The rising and falling edges should be smooth transitional (monotonic) when driving the cable to avoid excessive EMI. Figure 10-15. Data Signal Rise and Fall Time

10.4.4 USB Control Logic

The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The logic contains byte count buffers for transmit operations that load the active transmit endpoints byte count and use this to determine the number of bytes to transfer. This same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. CONSECUTIVE TRANSITIONS tPeriod DIFFERENTIAL DATA LINES CROSSOVER POINTS PAIRED TRANSITIONS tR DIFFERENTIAL DATA LINES tF RISE TIME FALL TIME 10% 90% 90% 10% LOW SPEED: 75 ns at CL = 50 pF , 300 ns at CL = 350 pF C L C L Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-15 When transmitting, the control logic handles parallel to serial conversion, CRC generation, NRZI encoding, and bit stuffing. When Receiving, the control logic handles Sync detection, packet identification, end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and serial to parallel conversion. Errors detected by the control logic include bad CRC, time-out while waiting for EOP , and bit stuffing violations.

10.4.4.1 Data Encoding/Decoding

The USB employs NRZI data encoding when transmitting packets. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. Figure 10-16 shows a data stream and the NRZI equivalent and Figure 10-17 is a flow diagram for NRZI. The high level represents the J state on the data lines in this and subsequent figures showing NRZI encoding. A string of zeros causes the NRZI data to toggle each bit time. A string of ones causes long periods with no transitions in the data. Figure 10-16. NRZI Data Encoding Figure 10-17. Flow Diagram for NRZI IDLEDATA IDLENRZI 0110 0 000 00 0 11 1 1 1 POWER UP NO PACKET TRANSMISSION IDLE BEGIN PACKET FETCH THE DATA BIT NO YES NO DATA TRANSITION TRANSITION IS PACKAGE TRANSFER DONE? NO YES DATA TRANSMISSION IS DATA BIT = 0? Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-16 REV 1

10.4.4.2 Bit Stuffing

In order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the USB (see Figure 10-18 and Figure 10-19). A 0 is inserted after every six consecutive 1’s in the data stream before the data is NRZI encoded to force a transition in the NRZI data stream. This gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. The receiver must decode the NRZI data, recognize the stuffed bits, and discard them. Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission. The data “one” that ends the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always enforced, without exception. If required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (EOP) signal. Figure 10-18. Bit Stuffing IDLE NRZI ENCODED DATA BIT STUFFED DATA RAW DATA STUFFED BIT SYNC PATTERN PACKET DATA PACKET DATASYNC PATTERN PACKET DATASYNC PATTERN SIX ONES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-17 Figure 10-19. Flow Diagram for Bit Stuffing POWER UP NO PACKET TRANSMISSION IDLE NO YES IS PACKAGE TRANSFER DONE? NO YES RESET THE BIT COUNTER TO 0 INSERT A ZERO BIT COUNTER = 6? INCREMENT THE COUNTER = 0 = 1BIT VALUE? GET NEXT BIT RESET BIT COUNTER TO 0 BEGIN PACKET TRANSMISSION Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-18 REV 1

10.5 I/O REGISTER DESCRIPTION

The USB Endpoint registers are comprised of a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the USB and the CPU. These registers are shown in Table 10-2. Table 10-2. Register Summary Register Name Bit 7 6 5 4 3 2 1 Bit 0 Addr USB Control Register 2 (UCR2)

0 TX1ST 0

ENABLE2 ENABLE1 STALL2 STALL1 $0037 TX1STR USB Address Register (UADDR) USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 $0038 USB Interrupt Register 0 (UIR0) TXD0F RXD0F RSTF SUSPND TXD0IE RXD0IE $0039 TXD0FR RXD0FR USB Interrupt Register 1 (UIR1) TXD1F EOPF RESUMF 0 TXD1IE EOPIE $003A RESUMFR TXD1FR EOPFR USB Control Register 0 (UCR0) T0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B USB Control Register 1 (UCR1) T1SEQ ENDADD TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C USB Status Register (USR) RSEQ SETUP 0 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 $003D USB Endpoint 0 Data Register 0 (UE0D0) UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0020 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 flfl USB Endpoint 0 Data Register 7 (UE0D7) UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0027 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 USB Endpoint 1/2 Data Register 0 (UE1D0) $0028 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 flfl USB Endpoint 1/2 Data Register 7 (UE1D7) $002F UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 = Unimplemented Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-19

10.5.1 USB Address Register (UADDR)

USBEN — USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is clear, the USB module will not respond to any tokens. Reset clears this bit. 1 = USB function enabled. 0 = USB function disabled. UADD6-UADD0 — USB Function Address These bits specify the USB address of the device. Reset clears these bits.

10.5.2 USB Interrupt Register 0 (UIR0)

TXD0F — Endpoint 0 Data Transmit Flag This read only bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmis- sion, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing a logic 0 to TXD0F has no effect. 1 = Transmit on Endpoint 0 has occurred. 0 = Transmit on Endpoint 0 has not occurred. RXD0F — Endpoint 0 Data Receive Flag This read only bit is set after the USB module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD0FR bit after all of the received data has been read. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UADDR R USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0$0038 W reset: 00000000 Figure 10-20. USB Address Register (UADDR) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UIR0 R TXD0F RXD0F RSTF SUSPND TXD0IE RXD0IE 00 $0039 W TXD0FR RXD0FR reset: 00000000 = Unimplemented Figure 10-21. USB Interrupt Register 0 (UIR0) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-20 REV 1 Software must also set RX0E bit to one to enable the next data packet recep- tion. If RXD0F bit is not cleared, a NAK handshake will be returned in the next OUT transaction. Reset clears this bit. Writing a logic 0 to RXD0F has no effect. 1 = Receive on Endpoint 0 has occurred. 0 = Receive on Endpoint 0 has not occurred. RSTF — USB Reset Flag This read only bit is set when a valid reset signal state is detected on the D+ and D– lines. This reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. This bit is cleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit is cleared by a POR reset. SUSPND — USB Suspend Flag To save power, this read/write bit should be set by the software if a 3ms con- stant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend mode. Unnecessary ana- log circuitry will be powered down. Software must clear this bit after the Resume flag (RESUMF) is set while this Resume interrupt flag is serviced. TXD0IE — Endpoint 0 Transmit Interrupt Enable This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt when the TXD0F bit becomes set. 1 = USB interrupts enabled for Transmit Endpoint 0. 0 = USB interrupts disabled for Transmit Endpoint 0. RXD0IE — Endpoint 0 Receive Interrupt Enable This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt when the RXD0F bit becomes set. 1 = USB interrupts enabled for Receive Endpoint 0. 0 = USB interrupts disabled for Receive Endpoint 0. TXD0FR — Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a logic 0 to TXD0FR has no effect. Reset clears this bit. RXD0FR — Endpoint 0 Receive Flag Reset Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a logic 0 to RXD0FR has no effect. Reset clears this bit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-21

10.5.3 USB Interrupt Register 1 (UIR1)

TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag This read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the data stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E must also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing a logic 0 to TXD1F has no effect. 1 = Transmit on Endpoint 1 or Endpoint 2 has occurred. 0 = Transmit on Endpoint 1 or Endpoint 2 has not occurred. EOPF — End of Packet Detect Flag This read only bit is set when a valid End-of-Packet sequence is detected on the D+ and D– lines. Software must clear this flag by writing a logic 1 to the EOPFR bit. Reset clears this bit. Writing a logic 0 to EOPF has no effect. 1 = End-of-Packet sequence has been detected. 0 = End-of-Packet sequence has not been detected. RESUMF — Resume Flag This read only bit is set when USB bus activity is detected while the SUSPND bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect. 1 = USB bus activity has been detected. 0 = No USB bus activity has been detected. RESUMFR — Resume Flag Reset Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writ- ing a logic 0 to RESUMFR has no effect. Reset clears this bit. TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable This read/write bit enables the USB to generate an interrupt when the shared Transmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Reset clears this bit. 1 = USB interrupts enabled for Transmit Endpoints 1 and 2. 0 = USB interrupts disabled for Transmit Endpoints 1 and 2. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UIR1 R TXD1F EOPF RESUMF 0 TXD1IE EOPIE 00 $003A W RESUMFR TXD1FR EOPFR reset: 00000000 = Unimplemented Figure 10-22. USB Interrupt Register 1(UIR1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-22 REV 1 EOPIE — End of Packet Detect Interrupt Enable This read/write bit enables the USB to generate an interrupt when the EOPF bit becomes set. Reset clears this bit. 1 = USB interrupts enabled for Transmit Endpoints 1 and 2. 0 = USB interrupts disabled for Transmit Endpoint 1 and 2. TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a logic 0 to TXD1FR has no effect. Reset clears this bit. EOPFR — End of Packet Flag Reset Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a logic 0 to the EOPFR has no effect. Reset clears this bit.

10.5.4 USB Control Register 0 (UCR0)

T0SEQ — Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 Token active for next Endpoint 0 transmit. 0 = DATA0 Token active for next Endpoint 0 transmit. STALL0 — Endpoint 0 Force Stall Bit This read/write bit causes Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. The USB hard- ware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake. 0 = Default. TX0E — Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to Endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more Endpoint 0 data needs to be transmitted. If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent. 0 = Data is not ready. Respond with NAK. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UCR0 R T0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0$003B W reset: 00000000 Figure 10-23. USB Control Register 0 (UCR0) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-23 RX0E — Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB Host controller sends an OUT token to Endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received. 0 = Not ready for data. Respond with NAK. TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for Endpoint 0. These bits are cleared by reset.

10.5.5 USB Control Register 1 (UCR1)

T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit. 0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit. ENDADD — Endpoint Address Select This read/write bit specifies whether the data inside the registers UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. 1 = The data buffers are used for Endpoint 2. 0 = The data buffers are used for Endpoint 1. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UCR1 R T1SEQ ENDADD TX1E FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0$003C W reset: 00000000 Figure 10-24. USB Control Register 1 (UCR1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-24 REV 1 TX1E — Endpoint 1/Endpoint 2 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set. Software should set the TX1E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent. 0 = Data is not ready. Respond with NAK. FRESUM — Force Resume This read/write bit forces a resume state (“K” or non-idle state) onto the USB data lines to initiate a remote wake-up. Software should control the timing of the forced resume to be between 10ms and 15 ms. Setting this bit will not cause the RESUMF bit to set. 1 = Force data lines to “K” state. 0 = Default. TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.

10.5.6 USB Control Register 2 (UCR2)

TX1STR — Clear Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a logic 0 to the TX1STR has no effect. Reset clears this bit. TX1ST — Transmit First Flag This read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is set when the USB control logic is setting the Endpoint 0 Data Receive Flag (RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at the end of an Endpoint 0 reception. This bit lets the firmware know that the Endpoint 0 transmission happened before the Endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT. 0 = IN transaction occurred after SETUP/OUT. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UCR2 R 0 TX1ST 0 ENABLE2 ENABLE1 STALL2 STALL1$0037 W TX1STR reset: - -0-0000 = Unimplemented Figure 10-25. USB Control Register 2 (UCR2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-25 ENABLE2 — Endpoint 2 Enable This read/write bit enables Endpoint 2 and allows the USB to respond to IN packets addressed to Endpoint 2. Reset clears this bit. 1 = Endpoint 2 is enabled and can respond to an IN token. 0 = Endpoint 2 is disabled. ENABLE1 — Endpoint 1 Enable This read/write bit enables Endpoint 1 and allows the USB to respond to IN packets addressed to Endpoint 1. Reset clears this bit. 1 = Endpoint 1 is enabled and can respond to an IN token. 0 = Endpoint 1 is disabled. STALL2 — Endpoint 2 Force Stall Bit This read/write bit causes Endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. Reset clears this bit. 1 = Send STALL handshake. 0 = Default. STALL1 — Endpoint 1 Force Stall Bit This read/write bit causes Endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. Reset clears this bit. 1 = Send STALL handshake. 0 = Default.

10.5.7 USB Status Register (USR)

RSEQ — Endpoint 0 Receive Sequence Bit This read only bit indicates the type of data packet last received for Endpoint 0 (DATA0 or DATA1). 1 = DATA1 Token received in last Endpoint 0 receive. 0 = DATA0 Token received in last Endpoint 0 receive. SETUP — SETUP Token Detect Bit This read only bit indicates that a valid SETUP token has been received. 1 = Last token received for Endpoint 0 was a SETUP token. 0 = Last token received for Endpoint 0 was not a SETUP token. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 USR R RSEQ SETUP 0 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0$003D W reset: UUUUUUUU = Unimplemented Figure 10-26. USB Status Register (USR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-26 REV 1 RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet Size These read only bits store the number of data bytes received for the last OUT or SETUP transaction for Endpoint 0. These bits are not affected by reset.

10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)

UE0RD7 - UE0RD0 — Endpoint 0 Receive Data Buffer These read only bits are serially loaded with OUT token or SETUP token data received over the USB’s D+ and D– pins. UE0TD7 - UE0TD0 — Endpoint 0 Transmit Data Buffer These write only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at Endpoint 0.

10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)

UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer These write only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff- ers are shared by Endpoints 1 and 2 and depend on proper configuration of the ENDADD bit.

10.6 USB INTERRUPTS

The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UE0D0 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0020 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 to :::::::: :::::::: UE0D7 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0027 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 reset: XXXXXXXX Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UE1D0 R $0028 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 to :::::::: :::::::: UE1D7 R $002F W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 reset: XXXXXXXX Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-27

• End of Transaction interrupts signify a completed transaction (receive or transmit)
• Resume interrupts signify that the USB bus is reactivated after having been suspended
• End of Packet interrupts signify that a low speed end of packet signal was detected All USB interrupts share the same interrupt vector. Firmware is responsible for determining which interrupt is active.

10.6.1 USB End of Transaction Interrupt

There are three possible end of transaction interrupts: Endpoint 0 Receive, Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of transaction interrupts occur as detailed in the following sections.

10.6.1.1 Receive Control Endpoint 0

For a Control OUT transaction directed at Endpoint 0, the USB module will generate an interrupt by setting the RXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-29. SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving a SETUP interrupt are shown in Figure 10-30.

10.6.1.2 Transmit Control Endpoint 0

For a Control IN transaction directed at Endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-31.

10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2

Transmit Endpoints 1 and 2 share their interrupt flag. For an IN transaction directed at Endpoint 1 or 2, the USB module will generate an interrupt by setting the TXD1F flag in the UIR1 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-32.

10.6.2 Resume Interrupt

The USB module will generate a USB interrupt if low speed bus activity is detected after entering the suspend state. A transition of the USB data lines to the non-idle state (“K” state) while in the suspend mode will set the RESUMF flag in the UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can only occur while the MC68HC05JB3 is in the suspend mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-28 REV 1

10.6.3 End of Packet Interrupt

The USB module can generate a USB interrupt upon detection of an end of packet signal (a single ended 0) for low speed devices. Upon detection of an SE0 sequence, the USB module sets the EOPF bit and will generate an interrupt if the EOPIE bit in the UIR1 register is set. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-29 Figure 10-29. OUT Token Data Flow for Receive Endpoint 0 Valid OUT token received for Endpoint 0 Endpoint 0 Receive Enabled? (USBEN = 1) Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) Error free DATA packet? No Response from USB function Send NAK Handshake Ignore transaction No response from USB function Set RXD0F to 1 Receive Control Endpoint Interrupt Enabled? (RXD0IE = 1) No Interrupt Valid transaction Interrupt generated Endpoint 0 Receive Not Stalled? (STALL0 = 0) Send STALL Handshake Accept Data Valid DATA token received for Endpoint 0? No Response from USB function Time-outN N N N N N Y Y Y Y Y Y Y Set/clear RSEQ bit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-30 REV 1 Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0 Valid SETUP token received for Endpoint 0 Endpoint 0 Receive Enabled? (USBEN = 1) Error free DATA packet? No Response from USB function Ignore transaction No response from USB function Set RXD0F to 1 Receive Control Endpoint Interrupt Enabled? (RXD0IE = 1) No Interrupt Valid transaction Interrupt generated Accept Data Set SETUP to 1 N N N Y Y Y Y Y Y STALL0 = 0? N Clear STALL0 bit Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) N Y set/clear RSEQ bit No Response from USB function Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLA REV 1 10-31 Figure 10-31. IN Token Data Flow for Transmit Endpoint 0 Transmit Endpoint Enabled? (USBEN = 1) Transmit Endpoint ready to Transfer? (TX0E = 1) && (TXD0F = 0) No Response from USB function Send NAK Handshake ACK received and no Set TXD0F to 1 Transmit Endpoint Interrupt Enabled? (TXD0IE = 1) No Interrupt Valid transaction Interrupt generated Transmit Endpoint not Stalled by firmware? (STALL0 = 0) Send STALL Handshake Send DATA Data PID set by T0SEQ Valid IN token received for Endpoint 0 N Y N N Y Y Y No Response from USB function N Y Time-out condition occur? N Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB3 10-32 REV 1 Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/2 Transmit Endpoint Enabled? (USBEN = 1) Transmit Endpoint ready to Transfer? (TX1E = 1) && (TXD1F = 0) & No Response from USB function Send NAK Handshake Set TXD1F to 1 Transmit Endpoint Interrupt Enabled? (TXD1IE = 1) No Interrupt Valid transaction Interrupt generated Transmit Endpoint not Stalled by firmware? (STALL1 & ENDP1) + (STALL2 & ENDP2) Send STALL Handshake Send DATA Data PID set by T1SEQ Valid IN token received for Endpoints 1 or 2 N N N Y Y Y ACK received and no Time-out condition occurs? No Response from USB function N Y ((ENDP2 & ENDADD) + (ENDP1 & ENDADD )) ENDP1 is Endpoint 1 directed traffic ENDP2 is Endpoint 2 directed traffic Note: Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 OPTICAL INTERFACE MOTOROLA REV 1 11-1 SECTION 11 OPTICAL INTERFACE The MC68HC05JB3 MCU has four pairs of Optical Interfaces, configured through Port-A. This port has built-in optical coupler interface devices, which can be directly connected to IR displacement encoders, such as in optical mouse and optical joystick applications.

11.1 OVERVIEW

In practical designs, each axis requires two optical couplers to detect the displace- ment. Hence, the eight optical interfaces on port-A are enabled in pairs, with each pair enabled by a bit in the Optical Interface Enable Register ($0E). Figure 11-1 shows a one pair of the optical interface. Table 11-1 shows the port-A configura- tion for the four pairs. Table 11-1. Port-A Optical Interface Pairs For optimal performance, the reference voltage used in the optical interface module is selectable from eight predefined values, as shown in Figure 11-2. and Table 11-2. This allows the optical interface to be easily configured by software to match the IR displacement encoders. The reference voltage is selected using the bits VREF0-VREF2 in the OIER. Optical Coupler Port pin used Enable bit in OIER Pair 1 PA0 and PA1 OIE0 Pair 2 PA2 and PA3 OIE1 Pair 3 PA4 and PA5 OIE2 Pair 4 PA6 and PA7 OIE3 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 OPTICAL INTERFACE MOTOROLA REV 1 11-3

11.2 OPTICAL INTERFACE ENABLE REGISTER

The OIER register controls the operation of the optical interface devices on Port-A. This register is located at address $0E. Figure 11-3. Optical Interface Enable Register (TCSR) OIE0 — Optical Interface pair 0 Enable 1 = PA0 and PA1 optical interface are enabled. 0 = PA0 and PA1 optical interface are disabled. OIE1 — Optical Interface pair 1 Enable 1 = PA2 and PA3 optical interface are enabled. 0 = PA2 and PA3 optical interface are disabled. OIE2 — Optical Interface pair 2 Enable 1 = PA4 and PA5 optical interface are enabled. 0 = PA4 and PA5 optical interface are disabled. OIE3 — Optical Interface pair 3 Enable 1 = PA6 and PA7 optical interface are enabled. 0 = PA6 and PA7 optical interface are disabled. VREF[0:2] — Reference Voltage Selection These 3 bits are used to select the optical interface reference voltage. Table 11-2. Optical Interface Reference Voltage Selection BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OIER R TCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0$000E W reset: 00000000 VREF2 VREF1 VREF0 Reference Voltage (mV), V DD =5 V 000 3 0 0 001 4 3 0 010 5 6 0 011 6 9 0 100 8 2 0 101 9 5 0 1 1 0 1080 1 1 1 1210 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA OPTICAL INTERFACE MC68HC05JB3 11-4 REV 1 TCMPE — Timer Input Capture Comparator Enable This bit is used to enable the comparator in the 16-bit timer input capture circuit. Please refer to 16-BIT TIMER section. 1 = Timer input capture comparator is selected. 0 = Timer input capture comparator schmitt trigger is selected. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-1 SECTION 12 INSTRUCTION SET This section describes the addressing modes and instruction types.

12.1 ADDRESSING MODES

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, No Offset
• Indexed, 8-Bit Offset
• Indexed, 16-Bit Offset
• Relative

12.1.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long.

12.1.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-2 REV 1

12.1.3 Direct

Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination.

12.1.4 Extended

Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.

12.1.5 Indexed, No Offset

Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF . Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

12.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-3

12.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.

12.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

12.1.9 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-4 REV 1

12.1.10 Register/Memory Instructions

Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1 lists the register/memory instructions. Table 12-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-5

12.1.11 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions.

12.1.12 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the Table 12-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left ASL Arithmetic Shift Right ASR Clear Bit in Memory BCLR Set Bit in Memory BSET Clear CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-6 REV 1 third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 12-3 lists the jump and branch instructions. Table 12-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-7

12.1.13 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 12-4 lists these instructions.

12.1.14 Control Instructions

These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 12-5, use inherent addressing. Table 12-4. Bit Manipulation Instructions Instruction Mnemonic Clear Bit BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Set Bit BSET Table 12-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and Enable IRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-8 REV 1

12.1.15 Instruction Set Summary

Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ‹ (A) + (M) + (C) × — ××× IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ‹ (A) + (M) × — ××× IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X Logical AND A ‹ (A) Ù (M) — — ×× — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ××× DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ‹ 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ‹ (PC) + 2 + rel ? Z = 1 ————— R E L 2 7 r r 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-9 BHCC rel Branch if Half-Carry Bit Clear PC ‹ (PC) + 2 + rel ? H = 0 ————— R E L 2 8 r r 3 BHCS rel Branch if Half-Carry Bit Set PC ‹ (PC) + 2 + rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ‹ (PC) + 2 + rel ? C Ú Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch if IRQ Pin High PC ‹ (PC) + 2 + rel ? IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ‹ (PC) + 2 + rel ? IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff p BLO rel Branch if Lower (Same as BCS) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch if Lower or Same PC ‹ (PC) + 2 + rel ? C Ú Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ‹ (PC) + 2 + rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ‹ (PC) + 2 + rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ‹ (PC) + 2 + rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ‹ (PC) + 2 + rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ‹ (PC) + 2 + rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ‹ (PC) + 2 + rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if bit n clear PC ‹ (PC) + 2 + rel ? M n = 0 ———— × DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRSET n opr relBranch if Bit n Set PC ‹ (PC) + 2 + rel ? M n = 1 ———— × DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ‹ (PC) + 2 + rel ? 1 = 0 ————— R E L 2 1 r r 3 Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-10 REV 1 BSET n opr Set Bit n Mn ‹ 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ‹ (PC) + 2; push (PCL) SP ‹ (SP) – 1; push (PCH) SP ‹ (SP) – 1 PC ‹ (PC) + rel CLC Clear Carry Bit C ‹ 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ‹ 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ‹ $00 A ‹ $00 X ‹ $00 M ‹ $00 M ‹ $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) —— ×× 1 DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ‹ (M) – 1 A ‹ (A) – 1 X ‹ (X) – 1 M ‹ (M) – 1 M ‹ (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC M A X M M Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-11 INC opr INCA INCX INC opr,X INC ,X Increment Byte M ‹ (M) + 1 A ‹ (A) + 1 X ‹ (X) + 1 M ‹ (M) + 1 M ‹ (M) + 1 DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ‹ Jump Address ————— DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ‹ (PC) + n (n = 1, 2, or 3) Push (PCL); SP ‹ (SP) – 1 Push (PCH); SP ‹ (SP) – 1 PC ‹ Conditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ‹ (M) — — ×× — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ‹ (M) — — ×× — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 ×× DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ‹ (X) · (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX ii ff NOP No Operation ————— I N H 9 D 2 Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA INSTRUCTION SET MC68HC05JB3 12-12 REV 1 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ‹ $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ‹ (SP) + 1; Pull (CCR) SP ‹ (SP) + 1; Pull (A) SP ‹ (SP) + 1; Pull (X) SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL)————— I N H 8 1 6 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ‹ 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ‹ 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ‹ (X) — — ×× — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 INSTRUCTION SET MOTOROLA REV 1 12-13 SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ‹ (PC) + 1; Push (PCL) SP ‹ (SP) – 1; Push (PCH) SP ‹ (SP) – 1; Push (X) SP ‹ (SP) – 1; Push (A) SP ‹ (SP) – 1; Push (CCR) SP ‹ (SP) – 1; I ‹ 1 PCH ‹ Interrupt Vector High Byte PCL ‹ Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 — — ×× — DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts — 0 — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask Ù Logical AND ii Immediate operand byte Ú Logical OR IMM Immediate addressing mode ¯ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ‹ Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag × Set or cleared n Any bit — Not affected Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLAINSTRUCTION SETMC68HC05JB3 12-14REV 1 Table 12-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX 0123456789AB C D EF BRSET0

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB M SB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLA REV 1 13-1 SECTION 13 ELECTRICAL SPECIFICATIONS This section provides the electrical and timing specifications for the MC68HC05JB3.

13.1 MAXIMUM RATINGS

Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. The device is not intended to operate at these conditions. The MCU contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range from VSS £ (VIN or VOUT ) £ VDD . Connect unused inputs to the appropriate voltage level, either VSS or VDD .

13.2 THERMAL CHARACTERISTICS

(Voltages referenced to VSS ) Rating Symbol Value Unit Supply Voltage V DD –0.3 to +7.0 V Bootloader Mode (IRQ/VPP Pin Only) V IN VSS – 0.3 to 17 V Current Drain Per Pin Excluding VDD and VSS I2 5 m A Operating Junction Temperature T J +150 °C Operating Temperature Range MC68HC05JB3 (Standard) MC68HC05JB3 (Extended) TA TA TL to TH 0 to +70 –40 to +85 Storage Temperature Range T stg –65 to +150 °C Characteristic Symbol Value Unit Thermal Resistance 20-pin PDIP 20-pin SOIC 28-pin PDIP 28-pin SOIC qJA qJA qJA qJA °C/W °C/W °C/W °C/W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB3 13-2 REV 1

13.3 DC ELECTRICAL CHARACTERISTICS

Table 13-1. DC Electrical Characteristics (VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Output Voltage ILoad = 10.0 mA VOL VOH VDD – 0.1 0.1 — V Output High Voltage (ILoad =–0.8 mA) PA0-7, PB0-2, PB4-7, PC0-3 VOH VDD – 0.8 — — V Output Low Voltage (ILoad = 1.6mA) PA0-3, PB0, PB4-7, PC0-3 (ILoad = 8mA) PA4-7 (ILoad = 25mA) PB1, PB2 (see note 8) VOL 0.4 0.4 0.5 V Input High Voltage PA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1 VIH 0.7· VDD —V DD V Input Low Voltage PA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1 VIL VSS — 0.2 · VDD V Supply Current (see Notes) Run (USB active) Run (USB suspended) Wait (USB active) Wait (USB suspended) Stop (USB suspended) 3.3V regulator on IDD 7.5 2.5 100 mA mA mA mA mA I/O Ports Hi-Z Leakage Current PA0-7, PB0-2, PB4-7, PC0-3 (without individual pull-down/up activated)IZ —— –10 mA Input Pull-down Current PA0-7, PB0, PB4-7, PC0-3 (with individual pull-down activated) IIL 50 100 200 mA Input Current RESET , IRQ, OSC1 I in ——5 mA Capacitance Ports (as Input or Output) RESE T, IRQ, OSC1, OSC2 C out C in pF pF Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 R OSC 1 2 3 M W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLA REV 1 13-3 NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25°C only. 3. Wait IDD : Only MFT and Timer1 active. 4. Run (Operating) IDD , Wait IDD : Measured using external square wave clock source to OSC1 (fOSC = 6.0 MHz), all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD –0.2 VDC. 6. Stop IDD measured with OSC1 = VSS . 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. T A = 0°C to +40°C. 9. These are preliminary specifications.

13.4 USB DC ELECTRICAL CHARACTERISTICS

PB1, PB2 R PULLUP 30 50 75 K W LVR Inhibit (see note 9) V LVRI 3.3 V LVR Recover (see note 9) V LVRR 3.5 V TCAP Input Threshold Voltage V TCAP VDD /2 V Table 13-2. USB DC Electrical Characteristics (VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Conditions Min Typ Max Unit Hi-Z State Data Line Leakage ILO 0V<Vin<3.3V –10 +10 mA Differential Input Sensitivity VDI |(D+)–(D–)| 0.2 V Differential Common Mode Range VCM Includes VDI range 0.8 2.5 V Single Ended Receiver Threshold VSE 0.8 2.0 V Static Output Low V OL R L of 1.5k to 3.6V 0.3 V Static Output High V OH R L of 15k to GND 2.8 3.6 V Table 13-1. DC Electrical Characteristics (VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB3 13-4 REV 1

13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS

NOTES: 1. All voltages measured from local ground, unless otherwise specified. 2. All timings use a capacitive load of 50pF , unless otherwise specified. 3. Low speed timings have a 1.5k pull-up to 2.8V on the D– data line. 4. Measured from 10% to 90% of the data signal. 5. The rising and falling edges should be smooth transitions (monotonic). 6. Timing differences between the differential data signals. 7. Measured at crossover point of differential data signals. 8. Capacitive loading includes 50pF of tester capacitance. Table 13-3. USB Low Speed Source Electrical Characteristics Parameter Symbol Conditions (Notes 1,2,3) Min Typ Max Unit Transition time: Rise Time Fall Time TR TF Notes 4, 5, 8 C L=50pF C L=350pF C L=50pF C L=350pF 300 300 ns ns ns ns Rise/Fall Time Matching T RFM TR /TF 80 120 % Output Signal Crossover Voltage VCRS 1.3 2.0 V Low Speed Data Rate T DRATE 1.5Mbs –1.5% 1.4775 676.8 1.500 666.0 1.5225 656.8 Mbs ns Source Differential Driver Jitter To Next Transition For Paired Transitions TUDJ1 TUDJ2 C L=350pF Notes 6 and 7 –25 –10 ns ns Receiver Data Jitter Tolerance To Next Transition For Paired Transitions TDJR1 TDJR2 C L=350pF Notes 7 –75 –45 ns ns Source EOP Width TEOPT Note 7 1.25 1.50 ms Differential to EOP Transition Skew TDEOP Note 7 –40 100 ns Receiver EOP Width Must Reject as EOP Must Accept TEOPR1 TEOPR2 Note 7 330 675 ns ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLA REV 1 13-5

13.6 CONTROL TIMING

NOTES: 1. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC . 2. Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C) 3. tslow is a parameter dependent on fOSC and loading. Typical value of tslow is TENTATIVEL Y set at 170 ns with minimal value of 130ns and maximal value of 185ns under the SIMULATION conditions that fOSC is 6.0 MHz and slow output transition feature is enabled. Actual transition time will be specified to replace the TBDs when enough characterization has been done on various wafers from different lots. The values listed here represent data off simulation runs under the specified conditions. Under no cir- cumstances should they be treated as the final specification. Table 13-4. Control Timing (VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Min Max Units Frequency of Operation Crystal Oscillator Option External Clock Source fOSC fOSC DC MHz MHz Internal Operating Frequency Crystal Oscillator (fOSC ‚ 2) External Clock (fOSC ‚ 2) fOP fOP DC MHz MHz Cycle Time (1/fOP )t CYC 330 — ns RESET Pulse Width Low t RL 1.5 — t CYC IRQ Interrupt Pulse Width Low (Edge-Triggered) tILIH 0.5 — t CYC IRQ Interrupt Pulse Period t ILIL note 1 — t CYC PA0 to PA3 Interrupt Pulse Width High (Edge-Triggered) tIHIL 0.5 — tCYC PA0 to PA3 Interrupt Pulse Period t IHIH note 1 — t CYC OSC1 Pulse Width t OH , tOL ——n s Output High to Low Transition Period on PA6, PA7, PB0-4 tSLOW ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB3 13-6 REV 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 A-1 APPENDIX A MC68HC705JB3 This appendix describes the MC68HC705JB3, the emulation part for MC68HC05JB3. The entire MC68HC05JB3 data sheet applies to the MC68HC705JB3, with exceptions outlined in this appendix. A.1 INTRODUCTION The MC68HC705JB3 is an EPROM version of the MC68HC05JB3, and is avail- able for user system evaluation and debugging. The MC68HC705JB3 is function- ally identical to the MC68HC05JB3 with the exception of the 2560 bytes user ROM is replaced by 2560 bytes user EPROM. Also, the mask options available on the MC68HC05JB3 are implemented using the Mask Option Register (MOR) in the MC68HC705JB3. The MC68HC705JB3 is not available in the 20-pin SOIC package. A.2 MEMORY The MC68HC705JB3 memory map is shown in Figure A-1. A.3 MASK OPTION REGISTER (MOR) The Mask Option Register (MOR) is a byte of EPROM used to select the features controlled by mask options on the MC68HC05JB3. In order to program this regis- ter the MORON bit in PCR need to be set to “1” before doing the EPROM pro- gramming process. COPEN – COP Enable 1 = COP watchdog function disabled. 0 = COP watchdog function enabled. IRQTRIG – IRQ, PA0-PA3 Interrupt Option 1 = Edge-triggered only. 0 = Edge-and-level-triggered. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MOR R COPEN IRQTRIG PULLREN PAINTEN OSCDLY LVREN$01FF W reset: 00111111 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 A-2 REV 1 PULLREN – Port A, B, and C Pull-up/down Option 1 = Connected. 0 = Disconnected PAINTEN – PA0-PA3 External Interrupt Option 1 = External interrupt capability on PA0-PA3 disabled. 0 = External interrupt capability on PA0-PA3 enabled. OSCDLY – Oscillator Delay Option 1 = 224 internal clock cycles. 0 = 4064 internal clock cycles. LVREN – LVR Option 1 = Low Voltage Reset circuit enabled. 0 = Low Voltage Reset circuit disabled. Figure A-1. MC68HC705JB3 Memory Map $003F $0000 I/O Registers EPROM Program Control Register $003E $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF $1FF6 $1FF3 $1FF4 $1FF5 $1FF2 $1FF1 Reserved USB Vector (Low Byte) Timer1 Vector (Low Byte) USB Vector (High Byte) Timer1 Vector (High Byte) MFT Vector (Low Byte) MFT Vector (High Byte) Reserved $1FF0Reserved Reserved IRQ Vector (High Byte) IRQ Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) I/O Registers $0000 $003F $0040 $006F Unused $0070 $00C0 $00FF $13FF Unused

4608 Bytes

$1400 $1DFF $1E00 $1FEF User EPROM $1FF0 $1FFF Mask Option Register$01FF Unused: 256 Bytes Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 A-3 A.4 BOOTSTRAP MODE Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is at VTST and the PB0 pin is at logic zero. The Bootloader program is masked in the ROM area from $1E00 to $1FEF . This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass. The user code must be a one-to-one correspondence with the internal EPROM addresses. A.5 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Reg- ister located at address $3E. Please contact Motorola for programming board availability. A.5.1 EPROM Program Control Register (PCR) This register is provided for programming the on-chip EPROM in the MC68HC705JB3. MORON – Mask Option Register ON 0 = Disable programming to Mask Option Register ($01FF) 1 = Enable programming to Mask Option Register ($01FF) ELAT – EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit should not be set when no programming voltage is applied to the Vpp pin. PGM – EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array. 1 = Programming power is switched ON to EPROM array. If ELAT„ 1, then PGM=0. Bits [7:3] – Reserved These are reserved bits and should remain zero. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 P C R R 00000 MORON ELAT PGM$003E W R R R R R reset: 00000000 R = Reserved Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 A-4 REV 1 A.5.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time tPGMR 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes. CAUTION It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. Figure A-2 shows the flow required to successfully program the EPROM. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 MOTOROLA REV 1 A-5 Figure A-2. EPROM Programming Sequence A.6 EPROM PROGRAMMING SPECIFICATIONS Table A-1. EPROM Programming Electrical Characteristics (VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Programming Voltage IRQ/VPP VPP 10 12 15 V Programming Current IRQ/VPP IPP —3— m A Programming Time per byte tEPGM 1 4 —m s START ELAT=1 Write EPROM byte PGM=1 Wait 1ms PGM=0 ELAT=0 Write additional byte? N Y END Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA MC68HC05JB3 A-6 REV 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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