68HC05V12

68HC05V12 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 240

Technical content

Datasheet sections

• 9.1 Contents
• 9.2 Introduction
• 9.3 Timer Counter Registers $18−$19 and $1A−$1B
• 9.4 Output Compare Register $16−$17
• 9.5 Input Capture Register $14−$15

Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED 68HC05V12 General Release Specification December 10, 1996 CSIC System Design Group Austin, Texas Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification © Motorola, Inc., 1996 MC68HC05V12 — Rev. 1.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification List of Sections NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 List of Sections Section 14. Byte Data Link Controller-Digital Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED List of Sections General Release Specification MC68HC05V12 — Rev. 1.0 List of Sections Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Table of Contents NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Table of Contents Section 1. General Description

1.6.9 PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB,

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC05V12 — Rev. 1.0 Table of Contents Section 2. Memory Map Section 3. Central Processing Unit (CPU) Section 4. Interrupts Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Table of Contents NON-DISCLOSURE AGREEMENT REQUIRED Secton 5. Resets Section 6. Low-Power Modes Section 7. Parallel Input/Output (I/O) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC05V12 — Rev. 1.0 Table of Contents Section 8. Core Timer Section 9. 16-Bit Timer Section 10. Serial Peripheral Interface (SPI) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Table of Contents NON-DISCLOSURE AGREEMENT REQUIRED Section 11. Pulse Width Modulators (PWMs) Section 12. EEPROM Section 13. A/D Converter Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC05V12 — Rev. 1.0 Table of Contents Section 14. Byte Data Link Controller-Digital (BDLC-D) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Table of Contents NON-DISCLOSURE AGREEMENT REQUIRED Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC05V12 — Rev. 1.0 Table of Contents Section 15. Gauge Drivers Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Table of Contents NON-DISCLOSURE AGREEMENT REQUIRED Section 16. Instruction Set Secton 17. Electrical Specifications Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC05V12 — Rev. 1.0 Table of Contents Section 18. Mechanical Specifications Section 19. Ordering Information Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification List of Figures NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 List of Figures Figure Title Page 1-2 MC68HC05V12 Pin Assignments (68-Pin PLCC Package) .25 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED List of Figures General Release Specification MC68HC05V12 — Rev. 1.0 List of Figures Figure Title Page 10-3 Serial Peripheral Interface Master-Slave Interconnection .102 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification List of Figures NON-DISCLOSURE AGREEMENT REQUIRED Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED List of Figures General Release Specification MC68HC05V12 — Rev. 1.0 List of Figures Figure Title Page 17-5 BDLC Variable Pulse Width Modulation (VPW) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification List of Tables NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 List of Tables Table Title Page 14-3 Transmit In-Frame Response Control Bit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED List of Tables General Release Specification MC68HC05V12 — Rev. 1.0 List of Tables Table Title Page 17-1 BDLC Transmitter VPW Symbol Timings 17-2 BDLC Receiver VPW Symbol Timings Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 1. General Description

1.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description

1.2 Introduction

The Motorola MC68HC05V12 microcontroller is a custom M68HC05- based MCU featuring a byte data link controller (BDLC) module and on- chip power regulation for the on-chip gauge drivers. The device is available packaged in a 68-pin plastic lead chip carrier (PLCC). A functional block diagram of the MC68HC05V12 is shown inFigure 1-1.

1.3 Features

Features of the MC68HC05V12 include the following.

• M68HC05 Core with On-Chip Oscillator for Crystal/Ceramic Resonator
• 12 Kbytes of User ROM and 384 Bytes of User RAM
• 256 Bytes of Byte, Block, or Bulk Erasable EEPROM
• Byte Data Link Controller (BDLC) Module
• 5-Channel, 8-Bit Analog-to-Digital (A/D) Converter
• Serial Peripheral Interface (SPI)
• 8-Bit Timer with Real-Time Interrupt
• 16-Bit Timer with One Input Capture and One Output Compare
• Two 38-Frequency, 6-Bit Pulse Width Modulators (PWMs)
• Mask Option Selectable Computer Operating Properly (COP) Watchdog System
• 23 General-Purpose Input/Output (I/O) Pins: – Eight I/O Pins with Interrupt Wakeup Capability – Eight I/O Pins Multiplexed with Timer, PWMs, and Serial Peripheral Interface (SPI) Pins – Seven General-Purpose I/O Pins
• Five Input-Only Pins Multiplexed with A/D Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED

• On-Chip H-Bridge Driver Circuitry to Drive Six Gauges – Four Minor Gauges – Two Major Gauges
• Mask Option Selectable Low-Voltage Reset (LVR)
• Power-Saving Stop Mode and Wait Mode Instructions (Mask Option Selectable STOP Instruction Disable)

1.4 MCU Structure

The overall block diagram of the MC68HC05V12 is shown in Figure 1-1. NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high andRESET is active low. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified inSection 17. Electrical Specifications.

1.5 Selectable Mask Options

The following mask options are selectable.

• Sensitivity onIRQ interrupt, edge- and level-sensitive or edge- sensitive only
• Selectable COP watchdog system enable/disable
• Selectable low-voltage reset (LVR) to hold CPU in reset
• Selectable STOP instruction disable Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description Figure 1-1. MC68HC05V12 Block Diagram INDEX REGISTER OSCILLATOR RESET OSC 1 OSC 2 SRAM — 384 BYTES USER ROM — 12 KBYTESIRQ PA0 PA1 PA3 PA3 PA4 PA5 PA6 DATA DIRECTION REG PORT A VSSD EEPROM — 256 BYTES 16-BIT TIMER WITH

1 TCAP AND 1 TCMP

PC7 * PC0 * PC1 * PC2 * PC3 * PC4 * PC5 * PC6 * DATA DIRECTION REG PORT C GAUGE DRIVERS VDD LVR 2-CHANNEL 38-FREQUENCY , 6-BIT PWM SPI 5-CHANNEL, 8-BIT A/D CONVERTER PD0/AD0 PD1/AD1 PD2/AD2 PD3/AD3 PD4/AD4 BDLC RXP VSSA INTERRUPT VCCA VPGC CLKIN 8-BIT TIMER WITH RTI VDD VGVREF VGSUP VSSG MAJ/MIN GAUGE PINS (20 PINS) INTERNAL DATA/ADDRESS BUS VREFH VREFL TXP IMAX * Interrupt Pins VDD INTERNAL STACK PTR COND CODE REG 1 1 1 I N Z CH CPU CONTROL 0 0 0 1100000 ALU 68HC05 CPU ACCUMLATOR PROGRAM COUNTER CPU REGISTERS PB0/SS WATCHDOG VSSD INTERNAL DIGITAL SUPPLIES VSSG Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Functional Pin Descriptions MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED

1.6 Functional Pin Descriptions

The pinout for the MC68HC05V12 is shown inFigure 1-2 followed by a functional description of each pin. Figure 1-2. MC68HC05V12 Pin Assignments (68-Pin PLCC Package) 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 1053 4342414039383736353433323129 302827 PB0/SS PB1/SCK PB2/MOSI PB3/MISO PB4/PWMA PB5/PWMB PB6/TCMP PB7/TCAP TXP RXP VDD VSSD IMAX MINB1 MINB2+ MINB2- VSSG PC3 PC2 PC1 PC0 VREFH VREFL PD4/AD4 PD3/AD3 PD2/AD2 PD1/AD1 PD0/AD0 VCCA VSSA MIND1 MIND2+ MIND2- VSSG MINA1 MINA2+ MINA2- MAJA1+ MAJA1- MAJA2+ MAJA2- VPGC VGSUP VGREF MAJB1+ MAJB1- MAJB2+ MAJB2- MINC1 MINC2+ MINC2- IRQ VSSD VDD OSC1 OSC2 RESET PA6 PA5 PA4 PA3 PA2 PA1 PA0 PC7 PC6 PC5 PC4 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description

1.6.1 VDD and VSSD

These pins provide power to all the microcontroller’s digital circuits. The short rise and fall times of the MCU supply current transients place very high short-duration current demands on the internal power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU supply pins as possible. Two sets of VDD and VSS pins are required to maintain on-chip supply noise within acceptable limits. Each supply pin pair will require its own decoupling capacitor. These are high-current pins.

1.6.2 VSSA

VSSA is a separate ground pad which provides a ground return for the analog-to-digital (A/D) subsystem and the digital-to-analog (D/A) gauge subsystem. To prevent digital noise contamination, this pin should be connected directly to a low-impedance ground reference point.

1.6.3 VCCA

VCCA is a separate supply pin providing power to the analog subsystems of the A/D converter and gauge drivers. This pin must be connected to the VDD pin externally. To prevent contamination from the digital supply, this pin should be adequately decoupled to a low-impedance ground reference.

1.6.4 VREFH and VREFL

VREFH is the positive (high) reference voltage for the A/D subsystem. VREFL is the negative (low) reference voltage for the A/D subsystem. VREFH and VREFL should be isolated from the digital supplies to prevent any loss of accuracy from the A/D converter. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Functional Pin Descriptions MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED

1.6.5 OSC1 and OSC2

The OSC1 and OSC2 pins are the connections for the on-chip oscillator. OSC1 is the input to the oscillator inverter. The output (OSC2) will always reflect OSC1 inverted except when the device is in stop mode which forces OSC2 high. The OSC1 and OCS2 pins can accept the following sets of components: 1. A crystal as shown inFigure 1-3(a) 2. A ceramic resonator as shown inFigure 1-3(a) 3. An external clock signal as shown inFigure 1-3(b) The frequency, fOSC , of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP .

1.6.5.1 Crystal Oscillator

The circuit inFigure 1-3(a) shows a typical oscillator circuit for an AT- cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion and radiated emissions.

1.6.5.2 Ceramic Resonator Oscillator

In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit inFigure 1-3(a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion and radiated emissions. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description

1.6.5.3 External Clock

An external clock from another CMOS-compatible device can be connected to the OSC1 input. The OSC2 pin should be left unconnected, as shown inFigure 1-3(b). Figure 1-3. Oscillator Connections

1.6.6 RESET

This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. TheRESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. TheRESET pin has an internal pulldown device that pulls theRESET pin low when there is an internal computer operating properly (COP) watchdog reset, power-on reset (POR), illegal address reset, a disabled STOP instruction reset or an internal low-voltage reset. Refer to Section 5. Resets.

1.6.7 IRQ (Maskable Interrupt Request)

This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a programmable mask option to select either negative edge-sensitive triggering or both negative edge- sensitive and low level-sensitive triggering. The IRQ input requires an external resistor to VDD for wire-OR operation, if desired. If theIRQ pin is not used, it must be tied to the VDD supply. TheIRQ pin contains an (a) Crystal or Ceramic Resonator Connections UNCONNECTED EXTERNAL CLOCK (b) External Clock Source Connection OSC1 OSC2 MCU 20 pF *20 pF * 4 MHz*

10 MΩ *

*Values shown are typical. For further information, consult the crystal oscillator vendor. MCU OSC1 OSC2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Functional Pin Descriptions MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED internal Schmitt trigger as part of its input to improve noise immunity. Each of the PC0 through PC7 I/O pins may be connected as an OR function with the IRQ interrupt function. This capability allows keyboard scan applications where the transitions on the I/O pins will behave the same as theIRQ pin. The edge or level sensitivity selected by a mask option for theIRQ pin does not apply to the port C input/output (I/O) pin interrupt. The I/O pin interrupt is always negative edge-sensitive. See Section 4. Interrupts for more details on the interrupts.

1.6.8 PA0–PA6

These seven I/O lines comprise port A. The state of any pin is software programmable, and all port A lines are configured as inputs during power-on or reset. SeeSection 7. Parallel Input/Output (I/O) for more details on the I/O ports.

1.6.9 PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB, PB6/TCMP, and PB7/TCAP

These eight I/O lines comprise port B. The state of any pin is software programmable, and all port B lines are configured as inputs during power-on or reset. SeeSection 7. Parallel Input/Output (I/O) for more details on the I/O ports. PB0–PB3 are shared with serial peripheral interface (SPI) functions. See Section 10. Serial Peripheral Interface (SPI) for more details concerning the operation of the SPI and configuration of these pins. PB6 and PB7 are also shared with timer functions. The TCAP pin controls the input capture feature for the on-chip 16-bit timer. The TCMP pin provides an output for the output compare feature of the on-chip 16- bit timer. SeeSection 9. 16-Bit Timer for more details on the operation of the timer subsystem. PB4 and PB5 are shared with the pulse width modulator output pins (PWMA and PWMB). See Section 11. Pulse Width Modulators (PWMs) for more details on the operation of the PWMs. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description

1.6.10 PC0–PC7

These eight I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. All eight pins are connected via an internal gate to the IRQ interrupt function. When the IRQ interrupt function is enabled, all the port C pins will act as negative edge-sensitive IRQ sources. See Section 7. Parallel Input/Output (I/O) for more details on the I/O ports.

1.6.11 PD0–PD4/AD0–AD4

When the A/D converter is disabled, PD0–PD4 are general-purpose input pins. The A/D converter is disabled upon exiting from reset. When the A/D converter is enabled, one of these pins is the analog input to the A/D converter. The A/D control register contains control bits to direct which of the analog inputs are to be converted at any one time. A digital read of this pin when the A/D converter is enabled results in a read of logical zero from the selected analog pin. A digital read of the remaining pins gives their correct (digital) values. SeeSection 13. A/D Converter for more details on the operation of the A/D subsystem.

1.6.12 TXP and RXP

These pins provide the I/O interface for the BDLC subsystem. See Section 14. Byte Data Link Controller-Digital (BDLC-D) for more details on the operation of the BDLC.

1.6.13 IMAX

This pin is used to define the maximum coil current in the gauges by connecting a resistor from this pin (RMAX ) to ground as shown in 15.7 Coil Sequencer and Control.

1.6.14 VPGC

This pin is the gauge power control pin for the external pass device. Refer to15.7 Coil Sequencer and Control. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Functional Pin Descriptions MC68HC05V12 — Rev. 1.0 General Release Specification General Description NON-DISCLOSURE AGREEMENT REQUIRED

1.6.15 VGSUP

This pin is the regulated gauge voltage input. Refer to15.7 Coil Sequencer and Control.

1.6.16 VSSG

Two pins are provided for a separate gauge driver ground, VSSG . Used as the current return only for the coil driver circuitry, it is a high-current pin.

1.6.17 VGVREF

This pin is the feedback pin for the gauge power regulator. External resistors as shown inFigure 15-14 . Sample Gauge Connections to the MC68HC05V12 are used to set the gauge input voltage at pin VGSUP .

1.6.18 MAJA(B)1+, MAJA(B)1−, MAJA(B)2+, and MAJA(B)2−

These pins are the full H-bridge coil driver pins. The A or B refer to pins associated with major gauge A or gauge B, and pin 1+/− or pin 2+/− refer to coil 1 or coil 2 of that major gauge and the direction of current flow. Refer to15.3 Gauge System Overview for more details on the operation of these pins.

1.6.19 MINA(B,C,D)1, MINA(B,C,D)2+, and MINA(B,C,D)2−

MINA(B,C,D)2+ and MINA(B,C,D)2− are the full H-bridge driver pins used with or for the minor gauges. These pins allow the coil current to be reversed for movement of gauge pointer from 0 to 180 degrees. MINA(B,C,D)1 is the low-side driver pin used with the minor gauges. The current flow through the coil is restricted to one direction. Refer to

15.3 Gauge System Overview for more details on the operation of

these pins. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description

1.7 Power Supply Pin Connections

Refer toFigure 1-4 for a supply decoupling diagram. Figure 1-4. Supply Decoupling Diagram

1.8 Decoupling Recommendations

To provide effective decoupling and to reduce radiated RF emissions, small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. A frequency that is too low will reduce decoupling effectiveness and could increase radiated RF emissions from the system. A low value capacitor (470 pF to 0.01µF) placed in parallel with the other capacitors will improve the bandwidth and effectiveness of the network. VDD VSSD 0.1 µF VSSA VCCA A/D CONVERTER 0.1 µF SINGLE POINT GROUND DIGITAL GAUGE REGISTER GAUGE DRIVERS DIGITAL CIRCUIT SUPPLY DIGITAL CIRCUIT GROUND VGSUP* ANALOG GROUND ANALOG SUPPLY MODULES VDD VSSD 0.1 µF VPGC* VSSG 0.1 µF * Refer toSection 15. Gauge Drivers for decoupling recommendations. **Optional supply isolation circuit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC05V12 — Rev. 1.0 General Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Memory Map NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 2. Memory Map

2.1 Contents

2.2 Introduction

When the MC68HC05V12 is in the single-chip mode, the input/out (I/O) and peripherals, user RAM, EEPROM, and user ROM are all active as shown inFigure 2-1. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC05V12 — Rev. 1.0 Memory Map Figure 2-1. MC68HC05V12 Single-Chip Mode Memory Map

2.3 I/O and Control Registers

The I/O and control registers reside in locations $0000–$003F. The overall organization of these registers is shown inFigure 2-2. The bit assignments for each register are shown inFigure 2-3 through Figure 2-6. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. BOOTLOADER/ FACTORY TEST CODE ROM

1008 BYTES

16 BYTES

64 BYTES

192 BYTES

Reset Vector (Low Byte) Reset Vector (High Byte) SWI Vector (Low Byte) SWI Vector (High Byte) IRQ Vector (Low Byte) IRQ Vector (High Byte) 16-Bit Timer Vector (Low Byte) 16-Bit Timer Vector (High Byte) $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF BDLC Vector (Low Byte) $003F $0000 $0100 $00FF 0255 0256 I/O $3FFF $3FF0 $3FEF $0040 $003F $0000 USER ROM

12032 BYTES

$3FF6BDLC Vector (High Byte) $3FF38-Bit Timer Vector (Low Byte) $3FF4SPI Vector (High Byte) $3FF5SPI Vector (Low Byte) $3FF28-Bit Timer Vector (High Byte) $3FF1Gauge Vector (Low Byte) $3FF0 *Gauge Vector (High Byte)/ 15360 15359 $3C00 $3BFF $0D00 $0CFF USER EEPROM

256 BYTES

2496 BYTES

$0340 $033F $0240 $01BF 0447 0576 USER RAM

128 BYTES

*Reading $3FF0 returns the gauge vector EPROM byte. Writing a zero to $3FF0, bit 0, resets the COP. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Memory Map NON-DISCLOSURE AGREEMENT REQUIRED Figure 2-2. MC68HC05V12 I/O Registers Memory Map Port A Data Register Port B Data Register Port A Data Direction Register Port B Data Direction Register 16-Bit Timer Status Register EEPROM Program Register A/D Data Register A/D Status and Control Register $0000 Port C Data Register Port C Data Direction Register Alternate Count Register (Low) Alternate Count Register (High) 16-Bit Timer Count Register (Low) 16-Bit Timer Count Register (High) Output Compare Register (Low) Output Compare Register (High) Input Capture Register (Low) Input Capture Register (High) 16-Bit Timer Control Register Unimplemented Unimplemented Unimplemented Unimplemented SPI Status Register SPI Control Register SPI Data Register Port D Data Register Reserved Unimplemented Current Direction Register — DMINA Current Direction Register — DMAJB IRQ Status and Control Register Unused 8-Bit Timer Status and Control Current Direction Register — DMINB Current Direction Register — DMINC Current Direction Register — DMIND 8-Bit Timer Counter Register $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Gauge Enable Register — GER Scan Status & Control Reg — SSCR Magnitude Register — MINA1 Magnitude Register — MAJB2 Magnitude Register — MAJA1 Magnitude Register — MAJB1 Magnitude Register — MAJA2 Magnitude Register — MINA2 Magnitude Register — MINB1 Magnitude Register — MINB2 Magnitude Register — MINC1 Magnitude Register — MINC2 Magnitude Register — MIND1 Magnitude Register — MIND2 Reserved Miscellaneous Register PWMA Data Register PWMA Control Register PWMB Data Register PWMB Control Register BDLC Control Register 1 BDLC Control Register 2 BDLC State Vector Register BDLC Data Register BDLC Analog Roundtrip Delay Register Current Direction Register — DMAJA Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC05V12 — Rev. 1.0 Memory Map

2.4 RAM

The total RAM consists of 384 bytes (including the stack). The stack begins at address $00FF and proceeds down to $00C0 (64 bytes). Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. NOTE: The stack is located in the middle of the RAM address space. Data written to addresses within the stack address range can be overwritten during stack activity.

2.5 Boot ROM

The boot ROM space in the MC68HC05V12 consists of 1008 bytes including EEPROM test code, burn-in code, and 16 bytes of bootloader vectors.

2.6 USER ROM

There are 12,032 bytes of user ROM and 16 bytes of ROM for user vectors and the COP update location.

2.7 EEPROM

This device contains 256 bytes of EEPROM. Programming the EEPROM is performed by the user on a single-byte basis by manipulating the programming register located at address $001C. Refer toSection 12. EEPROM for programming details. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Memory Map NON-DISCLOSURE AGREEMENT REQUIRED Addr. Register Read/ Write Bit 7 6 5 4321 Bit 0 $0000 Port A Data — PORTA PA6 PA5 PA4 PA3 PA2 PA1 PA0 W $0001 Port B Data — PORTB R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W $0002 Port C Data — PORTC R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 W $0003 Port D Data — PORTD R 0 0 0 PD4 PD3 PD2 PD1 PD0 W $0004 Port A Data Direction — DDRA DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W $0005 Port B Data Direction — DDRB R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W $0006 Port C Data Direction — DDRC R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W $0007 Unimplemented R W $0008 Core Timer Status and Control — CTSCR R CTOF RTIF TOFE RTIE RT1 RT0 W TOFC RTIFC $0009 Core Timer Counter — CTCR R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 W $000A SPI Control — SCR R SPIE SPE MSTR CPOL CPHA SPR1 SPR0 W $000B SPI Status — SSR R SPIF WCOL MODF W $000C SPI Data — SDR R SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 W $000D Unimplemented R W $000E Unimplemented R W $000F Unimplemented R W = Unimplemented R = Reserved Figure 2-3. I/O Registers $0000–$000F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC05V12 — Rev. 1.0 Memory Map Addr. Register Read/ Write Bit 7 6 5 4 3 2 1 Bit 0 $0010 Unimplemented R W $0011 Unimplemented R W $0012 16-Bit Timer Control — TMRCR R ICIE OCIE TOIE TON IEDG OLVL W $0013 16-Bit Timer Status — TMRSR R ICF OCF TOF W $0014 Input Capture High — TCAP (High) R IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 W $0015 Input Capture Low — TCAP (Low) R IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0 W $0016 Output Compare High — TCMP (High) R OC15 OC14 OC13 OC12 OC11 OC10 OC9 OC8 W $0017 Output Compare Low — TCMP (Low) R OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 W $0018 Timer Counter High — TCNT (High) R CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 W $0019 Timer Counter Low — TCNT (Low) R CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 W $001A Alternate Counter High — ALTCNT (High) R AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 W $001B Alternate Counter Low —ALTCNT (Low) R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W $001C EEPROM Programming — EEPROG R CPEN ER1 ER0 EELAT EERC EEPGM W $001D A/D Data — ADDR R AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W $001E A/D Status and Control — ADSCR R COCO ADRC ADON CH4 CH3 CH2 CH1 CH0 W $001F IRQ Status and Control — ISCR R IRQE IPCE IRQF IPCF 0 W IRQA = Unimplemented Figure 2-4. I/O Registers $0010–$001F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Memory Map NON-DISCLOSURE AGREEMENT REQUIRED Addr. Register Read/ Write Bit 7 6 5 4 3 2 1 Bit 0 $0020 Gauge Enable — GER R MJAON MJBON MIAON MIBON MICON MIDON CMPS R W $0021 Scan Status/ Control — SSCR R SYNIE SYNF R GCS1 GCS0 SCNS AUTOS W SYNR $0022 MAJA1 Magnitude — MAJA1 R B7 B6 B5 B4 B3 B2 B1 B0 W $0023 MAJA2 Magnitude — MAJA2 R B7 B6 B5 B4 B3 B2 B1 B0 W $0024 MAJB1 Magnitude — MAJB1 R B7 B6 B5 B4 B3 B2 B1 B0 W $0025 MAJB2 Magnitude — MAJB2 R B7 B6 B5 B4 B3 B2 B1 B0 W $0026 MINA1 Magnitude — MINA1 R B7 B6 B5 B4 B3 B2 B1 B0 W $0027 MINA2 Magnitude — MINA2 R B7 B6 B5 B4 B3 B2 B1 B0 W $0028 MINB1 Magnitude — MINB1 R B7 B6 B5 B4 B3 B2 B1 B0 W $0029 MINB2 Magnitude — MINB2 R B7 B6 B5 B4 B3 B2 B1 B0 W $002A MINC1 Magnitude — MINC1 R B7 B6 B5 B4 B3 B2 B1 B0 W $002B MINC2 Magnitude — MINC2 R B7 B6 B5 B4 B3 B2 B1 B0 W $002C MIND1 Magnitude — MIND1 R B7 B6 B5 B4 B3 B2 B1 B0 W $002D MIND2 Magnitude — MIND2 R B7 B6 B5 B4 B3 B2 B1 B0 W $002E MAJA Current Direction — DMAJA R 0 0 0 0 0 0 DMJA1 DMJA2 W $002F MAJB Current Direction — DMAJB R 0 0 0 0 0 0 DMJB1 DMJB2 W R = Reserved Figure 2-5. I/O Registers $0020–$002F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC05V12 — Rev. 1.0 Memory Map Addr. Register Read/ Write Bit 7 6 5 4 3 2 1 Bit 0 $0030 MINA Current Direction — DMINA R 0 0 0 0 0 0 0 DMIA W $0031 MINB Current Direction — DMINB R 0 0 0 0 0 0 0 DMIB W $0032 MINC Current Direction — DMINC R 0 0 0 0 0 0 0 DMIC W $0033 MIND Current Direction — DMIND R 0 0 0 0 0 0 0 DMID W $0034 Reserved R R R R R R R R R W $0035 Miscellaneous — MISCR R

0 OCE 0 0 0 0 0 0

W $0036 PWMA Data — PWMAD R POLA 0 D5 D4 D3 D2 D1 D0 W $0037 PWMA Control — PWMAC R PSA1A PSA0A 0 0 PSB3A PSB2A PSB1A PSB0A W $0038 PWMB Data — PWMBD R POLB 0 D5 D4 D3 D2 D1 D0 W $0039 PWMB Control — PWMBC R PSA1B PSA0B 0 0 PSB3B PSB2B PSB1B PSB0B W $003A BDLC Control 1 — BCR1 R IMSG CLKS R1 R0 0 0 IE WCM W $003B BDLC Control 2 — BCR2 R ALBE DLBE RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 W $003C BDLC State Vector — BSVR R0 0 I 3I 2I 1I 0 0 0 W $003D BDLC Data — BDATR R BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 W $003E BDLC Analog Round Trip Delay — BARD R ATS RXPOL 0 0 BO3 BO2 BO1 BO0 W $003F Reserved R R R R R R R R R W = One-Time Write = Unimplemented R = Reserved Figure 2-6. I/O Registers $0030–$003F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Memory Map NON-DISCLOSURE AGREEMENT REQUIRED

2.8 Miscellaneous Register

The miscellaneous register is located at $0035. OCE — Output Compare Enable This bit controls the function of the PB6 pin. 0 = PB6 functions as a normal I/O pin. 1 = PB6 becomes the TCMP output pin for the 16-bit timer. See Section 9. 16-Bit Timer for a description of the TCMP function. $0035 Bit 7 654321 Bit 0 Read: 0 OCE 000000 Write: Reset: 00000000 = Unimplemented Figure 2-7. Miscellaneous Register (MISC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC05V12 — Rev. 1.0 Memory Map Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Central Processing Unit (CPU) NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 3. Central Processing Unit (CPU)

3.1 Contents

3.2 Introduction

This section describes the CPU registers.

3.3 CPU Registers

Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Central Processing Unit (CPU) General Release Specification MC68HC05V12 — Rev. 1.0 Central Processing Unit (CPU) Figure 3-1. Programming Model

3.3.1 Accumulator

The accumulator (A) is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and non- arithmetic operations. ACCUMULATOR (A)A INDEX REGISTER (X)X SP110000 0000 PCLPCH00 ZCIN1H11 0475 CONDITION CODE REGISTER (CCR) PROGRAM COUNTER (PC) STACK POINTER (SP) 07815 15 5 HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Bit 7 654321 Bit 0 Read: Write: Reset: Unaffected by reset Figure 3-2. Accumulator (A) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Central Processing Unit (CPU) CPU Registers MC68HC05V12 — Rev. 1.0 General Release Specification Central Processing Unit (CPU) NON-DISCLOSURE AGREEMENT REQUIRED

3.3.2 Index Register

In the indexed addressingmodes, the CPU uses the byte in the index register (X) to determine the conditional address of the operand. The 8-bit index register can also serve as a temporary data storage location.

3.3.3 Stack Pointer

The stack pointer (SP) is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer is preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. The 10 most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations. An interrupt uses five locations. Bit 7 654321 Bit 0 Read: Write: Reset: Unaffected by reset Figure 3-3. Index Register (X) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 3-4. Stack Pointer (SP) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Central Processing Unit (CPU) General Release Specification MC68HC05V12 — Rev. 1.0 Central Processing Unit (CPU)

3.3.4 Program Counter

The program counter (PC) is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally and appear as 00. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

3.3.5 Condition Code Register

The condition code register (CCR) is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Read: 00 5 Write: Reset 0 0 Loaded with vectors from $3FF3 and $3FFF Figure 3-5. Program Counter (PC) Bit 7 654321 Bit 0 Read: 1 1 1 HIN Z C Write: Reset: 1 1 1U1UUU = Unimplemented U = Unaffected Figure 3-6. Condition Code Register (CCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Central Processing Unit (CPU) CPU Registers MC68HC05V12 — Rev. 1.0 General Release Specification Central Processing Unit (CPU) NON-DISCLOSURE AGREEMENT REQUIRED Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half- carry flag is required for binary coded decimal (BCD) arithmetic operations. Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Central Processing Unit (CPU) General Release Specification MC68HC05V12 — Rev. 1.0 Central Processing Unit (CPU)

3.4 Arithmetic/Logic Unit

The arithmetic/logic unit (ALU) performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 4. Interrupts

4.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts

4.2 Introduction

The MCU can be interrupted eight different ways: 1. Non-Maskable Software Interrupt Instruction (SWI) 2. External Asynchronous Interrupt (IRQ) 3. External Interrupt via IRQ on PC0–PC7 (IRQ) 4. Internal 16-Bit Timer Interrupt (TIMER) 5. Internal BDLC Interrupt (BDLC) 6. Internal Serial Peripheral Interface Interrupt (SPI) 7. Internal 8-Bit Timer Interrupt (CTIMER) 8. Internal Gauge Interrupt (GAUGE)

4.3 CPU Interrupt Processing

Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, then the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, then stacks the current CPU register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending after the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF0 through $3FFF as defined inTable 4-1. Because the M68HC05 CPU does not support interruptible instructions, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tCYC secs An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing. Table 4-1. Vector Address for Interrupts and Reset Register Flag Name Interrupts CPU Interrupt Vector Address N/A N/A Reset RESET $3FFE-$3FFF N/A N/A Software SWI $3FFC-$3FFD ISCR IRQF/IPCF External (IRQ & Port C) IRQ $3FFA-$3FFB TSR TOF Timer Overflow TIMER $3FF8-$3FF9 TSR OCF Output Compare TIMER $3FF8-$3FF9 TSR ICF Input Capture TIMER $3FF8-$3FF9 BSVR I3:I0 BDLC BDLC $3FF6-$3FF7 SPSR SPIF SPI SPI $3FF4-$3FF5 CTSCR CTOF Core Timer Overflow CTIMER $3FF2-$3FF3 CTSCR RTIF Real Time CTIMER $3FF2-$3FF3 SSCR SYNF Gauge Synchronize GAUGE $3FF0-$3FF1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts Figure 4-1. Interrupt Processing Flowchart N RESTORE REGISTERS FROM STACK: CCR, A, X, PC PORT C OR IRQ INTERRUPT? LOAD PC FROM APPROPRIATE VECTOR SET I BIT IN CC REGISTER STACK PC, X, A, CCR CLEAR IRQ REQUEST LATCH FETCH NEXT INSTRUCTION EXECUTE INSTRUCTION N N Y Y Y N I BIT IN CCR SET? SPI INTERRUPT? SWI INSTRUCTION N Y RTI INSTRUCTION Y FROM RESET N Y16-BIT TIMER INTERRUPT? N YBDLC INTERRUPT? N Y8-BIT TIMER INTERRUPT? N YGAUGE INTERRUPT? Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED

4.4 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown inFigure 4-1. A low level input on theRESET pin or internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $3FFE and $3FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described inSection 5. Resets.

4.5 Software Interrupt (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.

4.6 Hardware Interrupts

All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Two types of hardware interrupts are explained in the following paragraphs.

4.7 External Interrupt (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown inFigure 4-2. NOTE: The BIH and BIL instructions will apply only to the level on theIRQ pin itself and not to the output of the logic OR function with the port C IRQ interrupts. The state of the individual port C pins can be checked by reading the appropriate port C pins as inputs. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts Figure 4-2. IRQ Function Block Diagram The IRQ pin is one source of an external interrupt. All port C pins (PC0 through PC7) act as other external interrupt sources. These sources have their own interrupt latch but are combined with IRQ into a single external interrupt request. The port C interrupt sources are negative (falling) edge-sensitive only. Note that all port C pins are ANDed together to form the negative edge signal which sets the corresponding flag bits. A high-to-low transition on any port C pin configured as an interrupt input will, therefore, set the respective flag bit. If a port C pin is to be used as an interrupt input, the corresponding data direction and data bits must both be cleared. If either the pin is configured as an output or the data bit is set, a falling edge on the pin will not generate an interrupt. TheIRQ pin interrupt source may IRQ LATCH R VDD IRQ PIN IRQE LEVEL (MASK OPTION) IRQF TO IRQ PROCESSING IN CPU IRQA TO BIH & BIL INSTRUCTION SENSING RST R IPCE IPCF IRQ VECTOR FETCH VDD IRQPC LATCH PC0 PC7 DDRC0 DDRC7 DRC0 DRC0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

External Interrupt (IRQ) MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED be selected to be either edge sensitive or edge and level sensitive through a mask option. If the edge-sensitive interrupt option is selected for theIRQ pin, only the IRQ latch output can activate an IRQF flag which creates an interrupt request to the CPU to generate the external interrupt sequence. When edge sensitivity is selected for the IRQ interrupt, it is sensitive to the following cases: 1. Falling edge on theIRQ pin 2. Falling edge on any port C pin with IRQ enabled If the edge and level mask option is selected, the active low state of the IRQ pin can also activate an IRQF flag which creates an IRQ request to the CPU to generate the IRQ interrupt sequence. When edge and level sensitivity are selected for the IRQ interrupt, it is sensitive to the following cases: 1. Low level on theIRQ pin 2. Falling edge on theIRQ pin 3. Falling edge on any port C pin with IRQ enabled The IRQE enable bit controls whether an active IRQF flag (IRQ pin interrupt) can generate an IRQ interrupt sequence. The IPCE enable bit controls whether an active IPCF flag (port C interrupt) can generate an IRQ interrupt sequence. The IRQ interrupt is serviced by the interrupt service routine located at the address specified by the contents of $3FFA and $3FFB. The IRQF latch is cleared automatically by entering the interrupt service routine to maintain compatibility with existing M6805 interrupt servicing protocol. To allow the user to identify the source of the interrupt, the port interrupt flag (IPCF) is not cleared automatically. This flag must be cleared within the interrupt handler prior to exit to prevent repeated re- entry. This is achieved by writing a logic one to the IRQA (IRQ acknowledge) bit, which will clear all pending IRQ interrupts (including a pendingIRQ pin interrupt). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts The interrupt request flag (IPCF) is read only and cannot be cleared by writing to it. The acknowledge flag always reads as a logic 0. Together, these features permit the safe use of read-modify-write instructions (for instance, BSET and BCLR) on the ISCR. NOTE: Although read-modify-write instruction use is allowable on the ISCR, shift operations should be avoided due to the possibility of inadvertently setting the IRQA.

4.7.1 IRQ Status and Control Register

The IRQ interrupt function is controlled by the IRQ status and control register (ISCR) located at $001F. All unused bits in the ISCR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset. IRQE − IRQ Interrupt Enable The IRQE bit controls whether the IRQF flag bit can or cannot initiate an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can generate an interrupt sequence. If the IRQE enable bit is cleared, the IRQF flag bit cannot generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set to allow the external IRQ to exit these modes. In addition, reset also sets the I bit, which masks all interrupt sources. IPCE − Port C IRQ Interrupt Enable The IPCE bit controls whether the IPCF flag bit can or cannot initiate an IRQ interrupt sequence. If the IPCE enable bit is set, the IPCF flag bit will generate an interrupt sequence. If the IPCE enable bit is $001F Bit 7 654321 Bit 0 Read: IRQE IPCE

0 IRQF 0 IPCF 0

Write: IRQA Reset: 10000000 = Unimplemented Figure 4-3. IRQ Status and Control Register (ISCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

External Interrupt (IRQ) MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED cleared, the IPCF flag bit will not generate an interrupt sequence. Reset clears the IPCE enable bit, thereby disabling port C IRQ interrupts. In addition, reset also sets the I bit, which masks all interrupt sources. Execution of the STOP or WAIT instructions does not effect the IPCE bit. NOTE: The IPCE mask bit must be set prior to entering stop or wait modes if port IRQ interrupts are to be enabled. IRQF − IRQ Interrupt Request The IRQF flag bit indicates that an IRQ request is pending. Writing to the IRQF flag bit will have no effect on it. The IRQF flag bit is cleared when the IRQ vector is fetched prior to the service routine being entered. The IRQF flag bit can also be cleared by writing a logic one to the IRQA acknowledge bit to clear the IRQ latch. In this way any additional IRQF flag bit that is set while in the service routine can be ignored by clearing the IRQF flag bit before exiting the service routine. If the additional IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains set, the CPU will re-enter the IRQ interrupt sequence continuously until either the IRQF flag bit or the IRQE enable bit is clear. This flag can be set only when the IRQE enable is set. The IRQ latch is cleared by reset. IPCF − Port C IRQ Interrupt Request The IPCF flag bit indicates that a port C IRQ request is pending. Writing to the IPCF flag bit will have no effect on it. The IPCF flag bit must be cleared by writing a logic 1 to the IRQA acknowledge bit. If the IPCF bit is not cleared via IRQA, the CPU will re-enter the IRQ interrupt sequence continuously until either the IPCF flag bit or the IPCE enable bit is clear. This bit is operational regardless of the state of the IPCE bit. The IPCF bit is cleared by reset. IRQA − IRQ Interrupt Acknowledge The IRQA acknowledge bit clears an IRQ interrupt by clearing the IRQF and IPCF bits. This is achieved by writing a logic 1 to the IRQA acknowledge bit. Writing a logic 0 to the IRQA acknowledge bit will have no effect on the any of the IRQ bits. If either the IRQF or IPCF bit is not cleared within the IRQ service routine, then the CPU will re- enter the IRQ interrupt sequence continuously until the IRQ flag bits Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts are all cleared. The IRQA is useful for cancelling unwanted or spurious interrupts which may have occurred while servicing the initial IRQ interrupt. NOTE: The IRQ flag is cleared automatically during the IRQ vector fetch. The IRQPC latch is not cleared automatically (to permit interrupt source differentiation as long as the Interrupt source is present) and must be cleared from within the IRQ service routine.

4.7.2 External Interrupt Timing

If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of the IRQ source. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB. The IRQ timing diagram is shown inFigure 4-4. Figure 4-4. External Interrupts Timing Diagram IRQ tILIH tILIL tILIHIRQ1 (PORT) IRQn (PORT) IRQ (MCU) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Interrupts NON-DISCLOSURE AGREEMENT REQUIRED Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive- only trigger is available as a mask option for theIRQ pin only. 4.8 16-Bit Timer Interrupt Three different timer interrupt flags cause a 16-bit timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3FF8 and $3FF9.

4.9 BDLC Interrupt

The interrupt service routine is located at the address specified by the contents of memory location $3FF6 and $3FF7.

4.10 SPI Interrupt

Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3FF4 and $3FF5. 4.11 8-Bit Timer Interrupt This timer can create two types of interrupts. A timer overflow interrupt will occur whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt will occur whenever the programmed time elapses and the enable bit RTIE is set. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $3FF2 and $3FF3. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Interrupts General Release Specification MC68HC05V12 — Rev. 1.0 Interrupts

4.12 Gauge Synchronize Interrupt

This interrupt service routine is located at the address specified by the contents of memory location $3FF0 and $3FF1. See15.6.2 Current Magnitude Registers for further details.

4.13 Stop and Wait Modes

All modules which are capable of generating interrupts in stop or wait mode will be allowed to do so if the module is configured properly. The I bit is cleared automatically when stop or wait mode is entered. Interrupts detected on port C are recognized in stop or wait mode if port C interrupts are enabled. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Resets NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 5. Resets

5.1 Contents

5.2 Introduction

The MCU can be reset from six sources: one external input and five internal restart conditions. TheRESET pin is an input with a Schmitt trigger as shown inFigure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer toFigure 5-2 for reset timing detail. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Resets General Release Specification MC68HC05V12 — Rev. 1.0 Resets Figure 5-1.Reset Block Diagram

5.3 External Reset (RESET)

The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever theRESET pin is pulled below the lower threshold and remains in reset until theRESET pin rises above the upper threshold. This active low input will generate the RST signal and reset the CPU and peripherals. NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown that is activated by any reset source. This RESET pulldown device will only be asserted for three to four CPU LATCH RESET COP WATCHDOG (COPR) RST OSC DATA ADDRESS PH2 TO OTHER PERIPHERALS S LOW-VOLTAGE RESET (LVR)VDD IRQ MODE SELECT TO IRQ LOGIC LATCH R POWER-ON RESET (POR)VDD ILLEGAL ADDRESS (ILADDR)ADDRESS PH2 CLOCKED ONE-SHOT (PULSE WIDTH = 3 x tCYC) D D DISABLED STOP INSTRUCTION STOPEN Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Resets NON-DISCLOSURE AGREEMENT REQUIRED cycles of the internal clock, fOP , or as long as an internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will be turned on for only the three to four internal clock cycles.

5.4 Internal Resets

The five internally generated resets are the initial power-on reset function, the COP watchdog timer reset, the illegal address detector, the low-voltage reset, and the disabled STOP instruction. All internal resets will also assert (pull to logic 0) the externalRESET pin for the duration of the reset or three to four internal clock cycles, whichever is longer.

5.4.1 Power-On Reset (POR)

The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles (PH2) after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this 4064-cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will activate theRESET pin pulldown device connected to the pin. VDD must drop below VPOR for the internal POR circuit to detect the next rise of VDD . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Resets General Release Specification MC68HC05V12 — Rev. 1.0 Resets Figure 5-2. RESET and POR Timing Diagram

5.4.2 Computer Operating Properly Reset (COPR)

The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. Regardless of an internal or external RESET, the MCU comes out of a COP reset according to the pin conditions that determine mode selection. The COP reset function is enabled or disabled by the COP mask option. PCH PCL OSC12 RESET INTERNAL PROCESSOR INTERNAL ADDRESS BUS1 3FFE 3FFF VDD 4064 tcyc tcyc tRL INTERNAL DATA BUS 1 3FFE3FFE3FFE 3FFE NEW PC 3FFF NOTES: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge ofRESET initiates the reset sequence. NEW NEW OP CODEPCLPCH NEW PC NEW PC OP CODE NEW PC CLOCK1 0 V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Resets NON-DISCLOSURE AGREEMENT REQUIRED The COP watchdog reset will activate the internal pulldown device connected to theRESET pin.

5.4.2.1 Resetting the COP

Preventing a COP reset is done by writing a 0 to the COPR bit. This action will reset the counter and begin the timeout period again. The COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return user data programmed at that location.

5.4.2.2 COP during Wait Mode

The COP will continue to operate normally during wait mode. The system should be configured to pull the device out of wait mode periodically and reset the COP by writing to the COPR bit to prevent a COP reset.

5.4.2.3 COP during Stop Mode

When the STOP enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be held in reset during the 4064 cycles of startup delay. If any operable interrupt is used to exit stop mode, the COP counter will not be reset during the 4064-cycle startup delay and will have that many cycles already counted when control is returned to the program.

5.4.2.4 COP Watchdog Timer Considerations

The COP watchdog timer is active in user mode if enabled by the COP mask option. If the COP watchdog timer is selected, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the oscillator to halt and prevent the COP watchdog timer from timing out. Therefore, it is recommended that the STOP instruction should be disabled if the COP watchdog timer is enabled. If the COP watchdog timer is selected, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP watchdog Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Resets General Release Specification MC68HC05V12 — Rev. 1.0 Resets should be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized inTable 5-1.

5.4.2.5 COP Register

The COP register is shared with the MSB of an unimplemented user interrupt vector as shown inFigure 5-3. Reading this location will return whatever user data has been programmed at this location. Writing a 0 to the COPR bit in this location will clear the COP watchdog timer. Table 5-1. COP Watchdog Timer Recommendations IF the following conditions exist: THEN the COP Watchdog Timer should be as follows:STOP Instruction WAIT Time Converted to Reset WAIT Time Less Than COP Timeout Enable or Disable COP Converted to Reset WAIT Time MORE than COP Timeout Disable COP Acts as STOP Any Length WAIT Time Disable COP $3FF0 BIt 7 654321 Bit 0 Read: X X X X X X X X Write: COPR Reset: X X X X X X X X = Unimplemented Figure 5-3. COP Watchdog Timer Location Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Resets NON-DISCLOSURE AGREEMENT REQUIRED

5.4.3 Illegal Address Reset

An illegal address reset is generated when the CPU attempts to fetch an instruction from either unimplemented address space ($01C0 to $023F and $0340 to $0CFF) or I/O address space ($0000 to $003F). The illegal address reset will activate the internal pulldown device connected to the RESET pin.

5.4.4 Disabled STOP Instruction Reset

When the mask option is selected to disable the STOP instruction, execution of a STOP instruction results in an internal reset. This activates the internal pulldown device connected to theRESET pin.

5.4.5 Low-Voltage Reset (LVR)

The internal low voltage (LVR) reset is generated when VDD falls below the LVR threshold, VLVRI, and will be released following a POR delay starting when VDD rises above VLVRR . The LVR threshold is tested to be above the minimum operating voltage of the microcontroller and is intended to assure that the CPU will be held in reset when the VDD supply voltage is below reasonable operating limits. A mask option is provided to disable the LVR when the device is expected to normally operate at low voltages. Note that the VDD rise and fall slew rates (SVDDR and SVDDF ) must be within the specification for proper LVR operation. If the specification is not met, the circuit will operate properly following a delay of VDD /slew rate. The LVR will generate the RST signal which will reset the CPU and other peripherals. The low-voltage reset will activate the internal pulldown device connected to theRESET pin. If any other reset function is active at the end of the LVR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Resets General Release Specification MC68HC05V12 — Rev. 1.0 Resets

5.4.6 LVR Operation in Stop and Wait Modes

If enabled, the LVR supply voltage sense option is active during stop and wait modes. Any reset source can bring the MCU out of stop or wait mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Low-Power Modes NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 6. Low-Power Modes

6.1 Contents

6.2 Introduction

The MC68HC705V12 is capable of running in one of several low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP watchdog timer is enabled. A programmable mask option is provided to convert the STOP instruction to an internal reset. The flow of the stop and wait modes is shown inFigure 6-2.

6.3 STOP Instruction

The STOP instruction can result in one of two operations depending on the state of the mask option. If the STOP option is enabled, the STOP instruction operates like the STOP in normal MC68HC05 Family members and places the device in the low-power stop mode. If the STOP option is disabled, the STOP instruction will cause a chip reset when executed. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes General Release Specification MC68HC05V12 — Rev. 1.0 Low-Power Modes

6.4 Stop Mode

Execution of the STOP instruction with the mask option enabled places the MCU in its lowest power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including the COP watchdog timer. During stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared and the IRQE mask is set in the ICSR to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the stop mode only by:

• A n IRQ pin external interrupt
• An externally generated reset
• A falling edge on any port C pin (if enabled) or
• A rising edge on the BDLC RXP pin When exiting the stop mode, the internal oscillator will resume after a 4064 internal processor clock cycle oscillator stabilization delay as shown inFigure 6-1. NOTE: Entering stop mode will cause the oscillator to stop and, therefore, disable the COP watchdog timer. If the COP watchdog timer is to be used, stop mode should be disabled by disabling the mask option. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Low-Power Modes NON-DISCLOSURE AGREEMENT REQUIRED Figure 6-1. Stop Recovery Timing Diagram 3FFE 3FFE 3FFE 3FFE 3FFF INTERNAL ADDRESS BUS INTERNAL CLOCK IRQ3 IRQ2 RESET OSC11 tILCH 4064 tcyc RESET OR INTERRUPT VECTOR FETCH (RESET SHOWN) tLIH tRL NOTES: 1. Represents the internal gating of the OSC1 pin 2.IRQ pin edge-sensitive mask option or port C pin 3.IRQ pin level- and edge-sensitive mask option RXP IDLE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes General Release Specification MC68HC05V12 — Rev. 1.0 Low-Power Modes Figure 6-2. Stop/Wait Flowcharts PORT C FALLING EDGE? Y N RXP RISING EDGE? Y N RXP RISING EDGE? Y N 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE WAIT STOP ENABLED? Y N EXTERNAL RESET? Y N IRQ EXTERNAL INTERRRUPT? Y N STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, AND RESET STARTUP DELAY RESTART EXTERNAL OSCILLATOR, AND STABILIZATION DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR END OF STARTUP DELAY Y N IRQ EXTERNAL INTERRUPT? Y N EXTERNAL OSCILLATOR ACTIVE, AND INTERNAL TIMER CLOCK ACTIVE RESTART INTERNAL PROCESSOR CLOCK STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR TIMER INTERNAL INTERRUPT? Y N EXTERNAL RESET? Y N STOP PORT C FALLING EDGE? Y N RESET CHIP GAUGE SEQUENCE INTERRUPT? Y N SPI INTERRUPT? Y N Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Low-Power Modes NON-DISCLOSURE AGREEMENT REQUIRED

6.5 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode, which consumes more power than stop mode. In wait mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register. All other registers, memory, and input/output lines remain in their previous states. If timer interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode and resume normal operation. The timer may be used to generate a periodic exit from the wait mode. The MCU can be brought out of the wait mode by:

• A TIMER interrupt from either timer
• An SPI interrupt
• A n IRQ pin external interrupt
• An externally generated RESET
• A falling edge on any port C pin (if enabled)
• A rising edge on the BDLC RXP pin or
• A gauge sequence interrupt Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes General Release Specification MC68HC05V12 — Rev. 1.0 Low-Power Modes Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Parallel Input/Output (I/O) NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 7. Parallel Input/Output (I/O)

7.1 Contents

7.2 Introduction

In single-chip mode, 23 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O ports (ports B and C), and one 7-bit I/O port (port A). There is one 5-bit input port (port D). The individual bits in the I/O ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). The port C pins also have the additional property of acting as IRQ interrupt input sources. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC05V12 — Rev. 1.0 Parallel Input/Output (I/O)

7.3 Port A

Port A is a 7-bit bidirectional port which functions as shown in Figure 7-1. Each pin is controlled by the corresponding bit in a data direction register and a data register. The port A data register is located at address $0000. The port A data direction register (DDRA) is located at address $0004. Reset clears DDRA. The port A data register is unaffected by reset. Figure 7-1. Port A I/O Circuitry

7.3.1 Port A Data Register

Each port A I/O pin has a corresponding bit in the port A data register. When a port A pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port A pin is programmed as an input, any read of the port A data register will return the logic state of the corresponding I/O pin. The port A data register is unaffected by reset. READ $0000 WRITE $0000 READ $0004 DATA REGISTER BIT I/O PINOUTPUT INTERNAL HC05 DATA BUS RESET (RST) WRITE $0004 DATA DIRECTION REGISTER BIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Parallel Input/Output (I/O) Port B MC68HC05V12 — Rev. 1.0 General Release Specification Parallel Input/Output (I/O) NON-DISCLOSURE AGREEMENT REQUIRED

7.3.2 Port A Data Direction Register

Each port A I/O pin may be programmed as an input by clearing the corresponding bit in the DDRA or programmed as an output by setting the corresponding bit in the DDRA. The DDRA can be accessed at address $0004 and is cleared by reset.

7.4 Port B

Port B is an 8-bit bidirectional port. Each port B pin is controlled by the corresponding bits in a data direction register and a data register as shown inFigure 7-2. PB5 and PB4 are shared with the PWMs as shown inSection 11. Pulse Width Modulators (PWMs), PB7 and PB6 are shared with 16-bit timer functions. SeeSection 9. 16-Bit Timer for timer description. PB0-PB3 are shared with the SPI as shown inSection 10. Serial Peripheral Interface (SPI). The port B data register is located at address $0001. The port B data direction register (DDRB) is located at address $0005. Reset clears the DDRB register. The port B data register is unaffected by reset. Figure 7-2. Port B I/O Circuitry 16-BIT TIMER, PMWs, AND SPI MUX LOGIC READ $0001 WRITE $0001 READ $0005 DATA REGISTER BIT I/O PINOUTPUT INTERNAL HC05 DATA BUS RESET (RST) WRITE $0005 DATA DIRECTION REGISTER BIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC05V12 — Rev. 1.0 Parallel Input/Output (I/O)

7.4.1 Port B Data Register

Each port B I/O pin has a corresponding bit in the port B data register. When a port B pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port B pin is programmed as an input, any read of the port B data register will return the logic state of the corresponding I/O pin. The port B data register is unaffected by reset.

7.4.2 Port B Data Direction Register

Each port B I/O pin may be programmed as an input by clearing the corresponding bit in the DDRB or programmed as an output by setting the corresponding bit in the DDRB. The DDRB can be accessed at address $0005. The DDRB is cleared by reset.

7.5 Port C

Port C is an 8-bit bidirectional port shared with the IRQ interrupt subsystem as shown inFigure 7-3. Each pin is controlled by the corresponding bits in a data direction register and a data register. The port C data register is located at address $0002. The port C data direction register (DDRC) is located at address $0006. Reset clears DDRC. The port C data register is unaffected by reset. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Parallel Input/Output (I/O) Port C MC68HC05V12 — Rev. 1.0 General Release Specification Parallel Input/Output (I/O) NON-DISCLOSURE AGREEMENT REQUIRED Figure 7-3. Port C I/O Circuitry

7.5.1 Port C Data Register

Each port C I/O pin has a corresponding bit in the port C data register. When a port C pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port C pin is programmed as an input, any read of the port C data register will return the logic state of the corresponding I/O pin. The port C data register is unaffected by reset.

7.5.2 Port C Data Direction Register

Each port C I/O pin may be programmed as an input by clearing the corresponding bit in the DDRC or programmed as an output by setting the corresponding bit in the DDRC. The DDRC can be accessed at address $0006 and is cleared by reset.

7.5.3 Port C I/O Pin Interrupts

The inputs of all eight bits of port C are ANDed into the IRQ input of the CPU. See Figure 4-2. This port has its own interrupt request latch to enable the user to differentiate between the IRQ sources. The port IRQ RREAD $0002 WRITE $0002 READ $0006 DATA REGISTER BIT I/O PINOUTPUT INTERNAL HC05 DATA BUS RESET (RST) WRITE $0006 DATA DIRECTION REGISTER BIT TO IRQ SUBSYSTEM SEE FIGURE 4-2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC05V12 — Rev. 1.0 Parallel Input/Output (I/O) inputs are falling edge sensitive only. Any port C pin can be disabled as an interrupt input by setting the corresponding DDR bit or data register bit. To enable port pin interrupts, the corresponding DDR and data register bits must both be cleared. Any port C pin that is configured as an output will not cause a port interrupt when the pin transitions from a 1 to a 0. NOTE: The BIH and BIL instructions will apply only to the level on the IRQ pin itself and not to the internal IRQ input to the CPU. Therefore, BIH and BIL cannot be used to obtain the result of the logical combination of the eight pins of port C. NOTE: Caution should be exercised when writing to the port C data register and data direction register due to their interaction with the IRQ subsystem as depicted inFigure 4-2. Special care should be exercised in using read/modify/write instructions on these registers.

7.6 Port D

Port D is a 5-bit input-only port which shares all of its pins with the A/D converter (AD0 through AD4) as shown inFigure 7-4. The port D data register is located at address $0003. When the A/D converter is active, one of these five input ports may be selected by the A/D multiplexer for conversion. A logical read of a selected input port will always return 0. Figure 7-4. Port D Circuitry READ $0003/2B INPUT PIN INTERNAL HC05 DATA BUS VSS TO A/D SAMPLING CIRCUITRY TO A/D CHANNEL SELECT LOGIC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Core Timer NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 8. Core Timer

8.1 Contents

8.2 Introduction

The core timer for this device is a 12-stage multi-functional ripple counter. The features include timer overflow, power-on reset (POR), real-time interrupt (RTI), and computer operating properly (COP) watchdog timer. As seen inSection 8. Core Timer, the internal peripheral clock is divided by four then drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the core timer counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock(E)/1024. This point is then followed by two more stages, with the resulting clock (E/2048) driving the real-time interrupt circuit (RTI). The RTI circuit consists of three divider stages with a 1-of-4 selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location $08. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Core Timer General Release Specification MC68HC05V12 — Rev. 1.0 Core Timer Figure 8-1. Core Timer Block Diagram COP CLEAR INTERNAL BUS $09 CORE TIMER COUNTER REGISTER (CTCR) 5-BIT COUNTER CTOF RTIF TOFE RTIE RT1 INTERRUPT CIRCUIT $08 RTI SELECT CIRCUIT STATUS REGISTERRT0 TIMER CONTROL & OVERFLOW CIRCUIT DETECT COP WATCHDOG TIMER (÷ 8) TO RESET LOGIC RTFCTOFC E/210 CTSCR CTCR INTERNAL PERIPHERAL CLOCK (E) TO INTERRUPT LOGIC RTIout E / 212 POR E/22 DIVIDE E / 29 E / 214 E / 213 E / 212 E / 211 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Core Timer Status and Control Register MC68HC05V12 — Rev. 1.0 General Release Specification Core Timer NON-DISCLOSURE AGREEMENT REQUIRED

8.3 Core Timer Status and Control Register

The core timer status and control register (CTSCR) contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits.Figure 8-2 shows the value of each bit in the CTSCR when coming out of reset. CTOF — Core Timer Overflow CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. Clearing the CTOF is done by writing a 1 to TOFC. Writing to this bit has no effect. Reset clears CTOF. RTIF — Real Time Interrupt Flag The real-time interrupt circuit consists of a three-stage divider and a 1-of-4 selector. The clock frequency that drives the RTI circuit is E/2**11 (or E/2048) with three additional divider stages giving a maximum interrupt period of 7.8 milliseconds at a bus rate of 2.1 MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (1-of-4 selection) stage goes active. Clearing the RTIF is done by writing a 1 to RTFC. Writing has no effect on this bit. Reset clears RTIF. TOFE — Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears this bit. RTIE — Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. $08 Bit 7 654321 Bit 0 Read: CTOF RTIF TOFE RTIE RT1 RT0 Write TOFC RTFC Reset: 00000011 = Unimplemented Figure 8-2. Core Timer Status and Control Register (CTSCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Core Timer General Release Specification MC68HC05V12 — Rev. 1.0 Core Timer TOFC — Timer Overflow Flag Clear When a 1 is written to this bit, CTOF is cleared. Writing a 0 has no effect on the CTOF bit. This bit always reads as zero. RTFC — Real-Time Interrupt Flag Clear When a 1 is written to this bit, RTIF is cleared. Writing a 0 has no effect on the RTIF bit. This bit always reads as zero. RT1–RT0 — Real-Time Interrupt Rate Select These two bits select one of four taps from the real-time interrupt circuit. SeeTable 8-1 which shows the available interrupt rates with a 2.1 and 1.05 MHz bus clock. Reset sets bits RT1 and RT0, which selects the lowest periodic rate, and gives the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 8-1. RTI and COP Rates at 2.1 MHz RTI Rate RT1–RT0 Minimum COP Rates 2.1 MHz 1.05 MHz 2.1 MHz 1.05 MHz 0.97 ms 1.95 ms 2 11/E 00 (2 14–211)/E 6.83 ms 13.65 ms 1.95 ms 3.90 ms 2 12/E 01 (2 15–212)/E 13.65 ms 27.31 ms 3.90 ms 7.80 ms 2 13/E 10 (2 16–213)/E 27.31 ms 54.61 ms 7.80 ms 15.60 ms 2 14/E 11 (2 17–214)/E 54.61 ms 109.23 ms Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Computer Operating Properly (COP) Reset MC68HC05V12 — Rev. 1.0 General Release Specification Core Timer NON-DISCLOSURE AGREEMENT REQUIRED

8.4 Computer Operating Properly (COP) Reset

The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed inFigure 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout, or clearing the COP, is accomplished by writing a 0 to bit 0 of address $3FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared. The COP time out period will vary depending on when the COP is feed with respect to the RTI output clock. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. In addition theRESET pin will be pulled low for a minimum of 3 E clock cycles for emulation purposes. During a chip reset (regardless of the source), the entire core timer counter chain is cleared. The COP will remain enabled after execution of the WAIT instruction and all associated operations apply. If the STOP instruction is disabled, execution of STOP instruction will cause an internal reset. This COP’s objective is to make it impossible for this part to become “stuck” or “locked-up” and to be sure the COP is able to “rescue” the part from any situation where it might entrap itself in an abnormal or unintended behavior. This function is a mask option. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Core Timer General Release Specification MC68HC05V12 — Rev. 1.0 Core Timer

8.5 Core Timer Counter Register

The core timer counter register (CTCR) is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16- bit (or more) counter. The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, ifRESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted any time during operation (other than POR), the counter chain will be cleared.

8.6 Core Timer during Wait Mode

The CPU clock halts during wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. The COP watchdog timer, derived from the core timer, remains active in wait mode, if enabled via the MOR. $09 Bit 7 654321 Bit 0 Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 Write: Reset: 00000000 = Unimplemented Figure 8-3. Core Timer Counter Register (CTCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED 16-Bit Timer General Release Specification MC68HC05V12 — Rev. 1.0 16-Bit Timer Figure 9-1. 16-Bit Timer Block Diagram

9.3 Timer Counter Registers $18−$19 and $1A−$1B

The key element in the programmable timer is a 16-bit, free-running counter or counter register preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the free- running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register INPUT CAPTURE REGISTER CLOCK INTERNAL BUS OUTPUTCOMPARE REGISTER HIGH LOW BYTE $16 $17 □□□ INTERNAL PROCESSOR 16-BIT FREE- RUNNING COUNTER COUNTER ALTERNATE REGISTER LOW BYTE $1A $1B $18 $19 HIGH BYTE LOW BYTE $14 $15 OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT TIMER STATUS REGISTER ICF OCF TOF $13 ICIE IEDG OLVL OUTPUT LEVEL REGISTER RESETTIMER CONTROL REGISTER $12 OUTPUT LEVEL (TCMP) INTERRUPT CIRCUIT TOIEOCIE EDGE INPUT (TCAP) D CLK C Q PB6 PB7 BYTE 8-BIT BUFFER HIGH BYTE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Timer Counter Registers $18−$19 and $1A−$1B MC68HC05V12 — Rev. 1.0 General Release Specification 16-Bit Timer NON-DISCLOSURE AGREEMENT REQUIRED first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB also must be read to complete the sequence. The counter alternate register differs from the counter register in one respect: A read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. The free-running counter is configured to $FFFC during reset and is a read-only register only when the timer is enabled. During a power-on reset, the counter also is preset to $FFFC and begins running only after the TON bit in the timer control register is set. Because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. When counter roll-over occurs, an interrupt also can be enabled by setting its interrupt enable bit (TOIE). NOTE: To ensure that an interrupt does not occur, the I bit in the CCR should be set while manipulating both the high and low byte registers of a specific timer function. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED 16-Bit Timer General Release Specification MC68HC05V12 — Rev. 1.0 16-Bit Timer

9.4 Output Compare Register $16−$17

The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are continually compared with the contents of the free-running counter. If a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is clocked to an output level register. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear.

9.5 Input Capture Register $14−$15

Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Input Capture Register $14−$15 MC68HC05V12 — Rev. 1.0 General Release Specification 16-Bit Timer NON-DISCLOSURE AGREEMENT REQUIRED defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register MSB ($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. Figure 9-2. TCAP Timing NOTE: The input capture pin (TCAP) and the output compare pin (TCMP) are shared with PB7 and PB6 respectively. The timer’s TCAP input always is connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the miscellaneous control register is set. TCAP tTLTL tTL tTH See control timing specifications for TCAP timing requirements. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED 16-Bit Timer General Release Specification MC68HC05V12 — Rev. 1.0 16-Bit Timer 9.6 16-Bit Timer Control Register The 16-bit timer control register (TMRCR) is a read/write register containing six control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. ICIE – Input Capture Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCIE – Output Compare Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE – Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TON – Timer On When disabled, the timer is initialized to the reset condition. 1 = Timer enabled 0 = Timer disabled IEDG – Input Edge Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the input capture register. Reset clears this bit. 1 = Positive edge 0 = Negative edge $12 Bit 7 654321 Bit 0 Read: ICIE OCIE TOIE TON IEDG OLVL Write: Reset: 00000000 = Unimplemented Figure 9-3. Timer Control Register (TMRCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

16-Bit Timer Status Register (TMRSR) MC68HC05V12 — Rev. 1.0 General Release Specification 16-Bit Timer NON-DISCLOSURE AGREEMENT REQUIRED OLVL − Output Level Value of output level is clocked into output level register by the next successful output compare and will appear on the TCMP pin. 1 = High output 0 = Low output 9.7 16-Bit Timer Status Register (TMRSR) The 16-bit timer status register (TMRSR) is a read-only register containing three status flag bits. ICF – Input Capture Flag 1 = Flag set when selected polarity edge is sensed by input capture edge detector 0 = Flag cleared when TMRSR and input capture low register ($15) are accessed OCF – Output Compare Flag 1 = Flag set when output compare register contents match the free- running counter contents 0 = Flag cleared when TMRSR and output compare low register ($17) are accessed TOF – Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TMRSR and counter low register ($19) are accessed $13 Bit 7 654321 Bit 0 Read: ICF OCF TOF 00000 Write: Reset: 00000000 = Unimplemented Figure 9-4. Timer Status Register (TMRSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED 16-Bit Timer General Release Specification MC68HC05V12 — Rev. 1.0 16-Bit Timer Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set, and 2. The MSB of the free-running counter is read but not for the purpose of servicing the flag. The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 9.8 16-Bit Timer during Wait Mode The CPU clock halts during wait mode, but the timer remains active if turned on prior to entering wait mode. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 9.9 16-Bit Timer during Stop Mode In stop mode, the timer stops counting and holds the last count value if stop mode is exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if the timer is on and at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 10. Serial Peripheral Interface (SPI)

10.1 Contents

10.2 Introduction

The serial peripheral interface (SPI) allows several MC68HC05 MCUs or an MC68HC05 MCU plus peripheral devices to be interconnected within a single printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) General Release Specification MC68HC05V12 — Rev. 1.0 Serial Peripheral Interface (SPI)

10.3 Features

• Full Duplex, 3-Wire Synchronous Transfers
• Master or Slave Operation
• Internal MCU Clock Divided by Two (Maximum) Master Bit Frequency
• Internal MCU Clock (Maximum) Slave Bit Frequency
• Four Programmable Master Bit Rates
• Programmable Clock Polarity and Phase
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Master-Master Mode Fault Protection Capability

10.4 SPI Signal Description

The four pins (MOSI, MISO, SCK, andSS) are described in the following paragraphs. Each signal function is described for both the master and slave modes. To function properly, the SPI forces the direction on some of the pins to output. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Serial Peripheral Interface (SPI) SPI Signal Description MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED Figure 10-1. Data Clock Timing Diagram

10.4.1 Slave Select (SS/PB0)

The slave select (SS) pin is used to select the MCU as a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction. TheSS pin on the master must be set high. If it goes low, a mode fault error flag (MODF) is set in the SPSR. When CPHA = 0, the shift clock is the OR ofSS with SCK. In this clock phase mode,SS must go high between successive characters in an SPI message. When CPHA = 1,SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, itsSS pin could be set low as long as CPHA = 1 clock modes are used. NOTE: If the SPI is in master mode, this pin can be used as a general-purpose output pin. If configured as an input pin while in master mode, it must be set high. INTERNAL STROBE FOR DATA CAPTURE (ALL MODES) M S B 6543210 SS SCK SCK SCK SCK MISO/MOSI (CPOL = 0, CPHA = 0) (CPOL = 0, CPHA = 1) (CPOL = 1, CPHA = 0) (CPOL = 1, CPHA = 1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) General Release Specification MC68HC05V12 — Rev. 1.0 Serial Peripheral Interface (SPI)

10.4.2 Serial Clock (SCK/PB1)

The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown inFigure 10-1, four possible timing relationships may be chosen by using control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK) for the slave device to latch the data. Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.

10.4.3 Master In Slave Out (MISO/PB2)

The MISO line is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected.

10.4.4 Master Out Slave In (MOSI/PB3)

The MOSI line is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction with the most significant bit sent first. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Serial Peripheral Interface (SPI) SPI Functional Description MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED

10.5 SPI Functional Description

Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave via the MOSI line, the slave device responds by sending data to the master device via the master’s MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the I/O operation has been completed. The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is set. In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again. In a slave mode, the slave select start logic receives a logic low from the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave’s MISO line. Figure 10-3 illustrates the MOSI, MISO, SCK, andSS master-slave interconnections. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Serial Peripheral Interface (SPI) SPI Registers MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED

10.6 SPI Registers

Three registers in the SPI provide control, status, and data storage functions. These registers are called the serial peripheral control register (SPCR), serial peripheral status register (SPSR), and serial peripheral data I/O register (SPDR) and are described in the following paragraphs.

10.6.1 Serial Peripheral Control Register

SPIE −Serial Peripheral Interrupt Enable 1 = SPI interrupt if SPIF = 1 0 = SPIF interrupts disabled SPE − Serial Peripheral System Enable 1 = SPI system on; port B becomes SPI pins. 0 = SPI system off MSTR − Master Mode Select 1 = Master mode 0 = Slave mode CPOL −Clock Polarity When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. SeeFigure 10-1. $0A Bit 7 654321 Bit 0 Read: SPIE SPE MSTR CPOL CPHA SPR1 SPR0 Write: Reset: 000001U U = Unimplemented U = Unaffected Figure 10-4. SPI Control Register (SPCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) General Release Specification MC68HC05V12 — Rev. 1.0 Serial Peripheral Interface (SPI) CPHA − Clock Phase The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK withSS. As soon asSS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA = 1,SS may be thought of as a simple output enable control. SeeFigure 10-1. SPR1 and SPR0 − SPI Clock Rate Selects These two bits select one of four baud rates (seeTable 10-1) to be used as SCK if the device is a master; however, they have no effect in slave mode.

10.6.2 Serial Peripheral Status Register

Table 10-1. Serial Peripheral Rate Selection SPR1 SPR0 Internal MCU Clock Divided by 00 2 01 4 10 1 6 11 3 2 $0B Bit 7 654321 Bit 0 Read: SPIF WCOL 0 MODF 0000 Write: Reset: 00000000 = Unimplemented Figure 10-5. SPI Status Register (SPSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Serial Peripheral Interface (SPI) SPI Registers MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED SPIF − SPI Transfer Complete Flag The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an access of the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. WCOL − Write Collision The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA is zero, a transfer is said to begin whenSS goes low and the transfer ends whenSS goes high after eight clock cycles on SCK. When CPHA is one, a transfer is said to begin the first time SCK becomes active whileSS is low and the transfer ends when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access to SPDR. MODF − Mode Fault The mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. The MODF bit is normally clear, and is set only when the master device has itsSS pin set low. Setting the MODF bit affects the internal serial peripheral interface system in these ways: 1. An SPI interrupt is generated if SPIE = 1. 2. The SPE bit is cleared, disabling the SPI. 3. The MSTR bit is cleared, thus forcing the device into the slave mode. Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state after the MODF bit has been cleared. It is also necessary to restore the port B DDR bits after a mode fault. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) General Release Specification MC68HC05V12 — Rev. 1.0 Serial Peripheral Interface (SPI)

10.6.3 Serial Peripheral Data Register

The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission. $0C Bit 7 654321 Bit 0 Read: SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Write: Reset: Unaffected by reset Figure 10-6. SPI Data Register (SPDR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Serial Peripheral Interface (SPI) SPI in Stop Mode MC68HC05V12 — Rev. 1.0 General Release Specification Serial Peripheral Interface (SPI) NON-DISCLOSURE AGREEMENT REQUIRED

10.7 SPI in Stop Mode

When the MCU enters stop mode, the baud rate generator driving the SPI shuts down. This essentially stops all master mode SPI operation; thus, the master SPI is unable to transmit or receive any data. If the STOP instruction is executed during an SPI transfer, that transfer is halted until the MCU exits stop mode (provided it is an exit resulting from a viable interrupt source). If the stop mode is exited by a reset, then the appropriate control/status bits are cleared and the SPI is disabled. If the device is in slave mode when the STOP instruction is executed, the slave SPI will still operate. It can still accept data and clock information in addition to transmitting its own data back to a master device. At the end of a possible transmission with a slave SPI in stop mode, no flags are set until a viable interrupt results in an MCU wake up. Be cautious when operating the SPI (as a slave) during stop mode because none of the protection circuitry (write collision, mode fault, etc.) is active. Also note that when the MCU enters stop mode, all enabled output drivers (MISO, MOSI, and SCLK ports) remain active and any sourcing currents from these outputs will be part of the total supply current required by the device.

10.8 SPI in Wait Mode

The SPI subsystem remains active in wait mode. Therefore, it is consuming power. Before reducing power, the SPI should be shut off prior to entering wait mode. A non-reset exit from wait mode will result in the state of the SPI being unchanged. A reset exit will return the SPI to its reset state, which is disabled. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) General Release Specification MC68HC05V12 — Rev. 1.0 Serial Peripheral Interface (SPI) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Pulse Width Modulators (PWMs) NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 11. Pulse Width Modulators (PWMs)

11.1 Contents

11.2 Introduction

The pulse width modulator (PWM) system has two 6-bit PWMs (PWMA and PWMB). Preceding the 6-bit (÷64) counters are two programmable prescalers.The PWM frequency is selected by choosing the desired divide option from the programmable prescalers. Note that the PWM clock input is fOP . The PWM frequency will be fOP /(PSA*(PSB-1)*64) where PSA and PSB are the values selected by the A and B prescaler and 64 comes from the 6-bit modulus counter. SeeTable 11-1 for precise values. The fOP is the internal bus frequency fixed to half of the external oscillator frequency. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Pulse Width Modulators (PWMs) General Release Specification MC68HC05V12 — Rev. 1.0 Pulse Width Modulators (PWMs) Figure 11-1. PWM Block Diagram

11.3 PWM Functional Description

The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data register yields a low output (0%), but a $3F yields a duty of 63/64. To achieve the 100% duty (high output), the polarity control bit is set to zero while the data register has $00 in it. When not in use, the PWM system can be shut off to save power by clearing the clock rate select bits PSA0x and PSA1x in PWM control registers. Writes to the PWM data registers are buffered and can, therefore, be performed at any time without affecting the output signal. When the PWM subsystem is enabled, a write to the PWM control register will become effective immediately. When the PWM subsystem is enabled, a write to the PWM data register will not become effective until the end of the current PWM period has 6-BIT COUNTER (÷64) PWM DATA REGISTER MODULUS AND COMPARATOR PWMx PIN LOGIC PWMx ÷1,÷8, ÷16 fOP (CPU BUS CLOCK) PSA0x PSA1x PWM CONTROL REGISTERS AND BUFFERS HC05 DATA BUS POLx PWM DATA BUFFER SCLK ÷1–16 PSB2x PSB3x PSB0x PSB1x RCLK INTEGER DIVIDE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Pulse Width Modulators (PWMs) General Release Specification MC68HC05V12 — Rev. 1.0 Pulse Width Modulators (PWMs)

11.4 PWM Registers

Associated with each PWM system, there is a PWM data register and a control register. These registers can be written to and read at any time. Data written to the data register is held in a buffer and transferred to the PWM data register at the end of a PWM cycle. Reads of this register will always result in the read of the PWM data register and not the buffer. Upon RESET the user should write to the data register prior to enabling the PWM system (for example, prior to setting the PSAx and PSBx bits for PWM input clock rate). This will avoid an erroneous duty cycle from being driven. During user mode, the user should write to the PWM data register after writing the PWM control register. Figure 11-4. PWM Write Sequences INITIALIZE PWM DATA 0 WRITE PWM CONTROL OR RESET POR WRITE PWM CONTROL WRITE PWM DATA 1 NY Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Pulse Width Modulators (PWMs) PWM Registers MC68HC05V12 — Rev. 1.0 General Release Specification Pulse Width Modulators (PWMs) NON-DISCLOSURE AGREEMENT REQUIRED

11.4.1 PWMA Control Register

PSA1A, PSA0A, PSB3A −PSB0A — PWMA Clock Rate Bits These bits select the input clock rate and determine the period as shown inTable 11-1. Note that some output frequencies can be obtained with more than one combination of PSA and PSB values. For instance, a PWMA output of fOP /512 can be obtained with either PSA −PSA0 = 10 and PSB3−PSB0 = $0 or PSA1−PSA0 = 01 and PSB3 −PSB0 = $07. The frequency division provided by the PSB values will be one more that the value written to the register. For example, a $0 written to the PSB bits provides a÷1 and a $1 provides a ÷2,etc. This scheme allows for 38 unique frequency selections. NOTE: Any non-zero value of PSA1A−PSA0A forces PB4 to the PWMA output state. If PSA1A:PSA0A = 00, PB4 is determined by the port B data and data direction registers as described inSection 7. Parallel Input/Output (I/O). $37 Bit 7 654321 Bit 0 Read: PSA1A PSA0A PSB3A PSB2A PSB1A PSB0A Write: Reset: 00000000 = Unimplemented Figure 11-5. PWMA Control Register (PWMAC) Table 11-1. PWMA Clock Rates PSA1A– PSA0A PSB3A– PSB0A RCLKA SCLKA PWMA OUT 00 xxxx off off off 01 0000–1111 f OP /1 f OP /1–fOP /16 f OP /64–fOP /1024 10 0000–1111 f OP /8 f OP /8–fOP /128 f OP /512–fOP /8192 11 0000–1111 f OP /16 f OP /16–fOP /256 f OP /1024–fOP /16384 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Pulse Width Modulators (PWMs) General Release Specification MC68HC05V12 — Rev. 1.0 Pulse Width Modulators (PWMs)

11.4.2 PWMB Control Register

PSA1B, PSA0B, and PSB3B−PSB0B — PWM Clock Rate These bits select the input clock rate for PWMB and determine the period as shown inTable 11-2. These bits function exactly the same as the corresponding bits in the PWMA control register except they affect the PWMB output pin. NOTE: Any non-zero value of PSA1B−PSA0B forces PB5 to the PWMB output state. If PSA1B−PSA0B = 00, PB5 is determined by the port B data and data direction registers as described inSection 7. Parallel Input/Output (I/O). $39 Bit 7 654321 Bit 0 Read: PSA1B PSA0B PSB3B PSB2B PSB1B PSB0B Write: Reset: 00000000 = Unimplemented Figure 11-6. PWMB Control Register (PWMBC) Table 11-2. PWMB Clock Rates PSA1B– PSA0B PSB3B– PSB0B RCLKB SCLKB PWMB OUT 00 xxxx off off off 01 0000–1111 f OP /1 f OP /1–fOP /16 f OP /64–fOP /1024 10 0000–1111 f OP /8 f OP /8–fOP /128 f OP /512–fOP /8192 11 0000–1111 f OP /16 f OP /16–fOP /256 f OP /1024–fOP /16384 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Pulse Width Modulators (PWMs) PWM Registers MC68HC05V12 — Rev. 1.0 General Release Specification Pulse Width Modulators (PWMs) NON-DISCLOSURE AGREEMENT REQUIRED

11.4.3 PWMA Data Register

The PWMA system has one 6-bit data register which holds the duty cycle information. The data bits in this register are unaffected by reset. A value of $00 in this register corresponds to a steady state output level (0% duty cycle) on the PWMA pin. The logic level of the output will depend on the value of the POLA bit in the PWMA control register. POLA — PWMA Polarity 1 = PWMA pulse is active high. 0 = PWMA pulse is active low.

11.4.4 PWMB Data Register

The PWMB system has one 6-bit data register which holds the duty cycle information. These bits work the same way as the data bits in the PWMA data register except they affect the PWMB output pin. The data bits in this register are unaffected by reset. POLB — PWMB Polarity 1 = PWMB pulse is active high. 0 = PWMB pulse is active low. $36 Bit 7 654321 Bit 0 Read: POLA D5 D4 D3 D2 D1 D0 Write: Reset: 0 0 UUUUUU = Unimplemented U = Unaffected Figure 11-7. PWMA Data Register $38 Bit 7 654321 Bit 0 Read: POLB D5 D4 D3 D2 D1 D0 Write: Reset: 0 0 UUUUUU = Unimplemented U = Unaffected Figure 11-8. PWMB Data Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Pulse Width Modulators (PWMs) General Release Specification MC68HC05V12 — Rev. 1.0 Pulse Width Modulators (PWMs)

11.5 PWMs during Wait Mode

The PWM continues normal operation during wait mode. To decrease power consumption during wait mode, it is recommended that the rate select bits in the PWM control registers be cleared if the PWM is not being used.

11.6 PWMs during Stop Mode

In stop mode, the oscillator is stopped causing the PWM to cease functioning. Any signal in process is aborted in whatever phase the signal happens to be in.

11.7 PWMs during Reset

Upon reset the PSA0X and PSA1X bits in PWMX control registers are cleared. This disables the PWM system and sets the PWM outputs low. The user should write to the data registers prior to enabling the PWM system (for example, prior to setting PSA1X or PSA0X). This will avoid an erroneous duty cycle from being driven. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification EEPROM NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 12. EEPROM

12.1 Contents

12.2 Introduction

The MC68HC05V12 contains EEPROM memory. This section describes the programming mechanisms for EEPROM memory. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED EEPROM General Release Specification MC68HC05V12 — Rev. 1.0 EEPROM

12.3 EEPROM Programming Register

The contents and use of the programming register are discussed here. NOTE: Any reset including LVR will abort any write in progress when it is asserted. Data written to the addressed byte will, therefore, be indeterminate. CPEN — Charge Pump Enable When set, CPEN enables the charge pump which produces the internal programming voltage. This bit should be set with the EELAT bit. The programming voltage will not be available until EEPGM is set. The charge pump should be disabled when not in use. CPEN is readable and writable and is cleared by reset. ER1 −ER0 — Erase Select Bits ER1 and ER0 form a 2-bit field which is used to select one of three erase modes: byte, block, or bulk.Table 12-1 shows the modes selected for each bit configuration. These bits are readable and writable and are cleared by reset. In byte erase mode, only the selected byte is erased. In block mode, a 64-byte block of EEPROM is erased. The EEPROM memory space is divided into four 64-byte blocks ($0240-$027F, $0280-$02BF, $02C0-$02FF, and $0300-$033F), and doing a block erase to any address within a block will erase the entire block. In bulk erase mode, the entire 256 byte EEPROM section is erased. $1C Bit 7 654321 Bit 0 Read: 0 CPEN ER1 ER0 EELAT EERC EEPGM Write: Reset: 00000000 = Unimplemented Figure 12-1. EEPROM Programming Register (EEPROG) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

EEPROM Programming Register MC68HC05V12 — Rev. 1.0 General Release Specification EEPROM NON-DISCLOSURE AGREEMENT REQUIRED EELAT — EEPROM Programming Latch When set, EELAT configures the EEPROM address and data bus for programming. When EELAT is set, writes to the EEPROM array cause the data bus and the address bus to be latched. This bit is readable and writable, but reads from the array are inhibited if the EELAT bit is set and a write to the EEPROM space has taken place. When clear, address and data buses are configured for normal operation. Reset clears this bit. EERC — EEPROM RC Oscillator Control When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. After setting the EERC bit, delay a time, tRCON , to allow the RC oscillator to stabilize. This bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5 MHz. Reset clears this bit. EEPGM — EEPROM Programming Power Enable EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, this power is switched off. This will enable pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be written to if EELAT = 1. If EELAT is not set, then EEPGM cannot be set. Reset clears this bit. Table 12-1. Erase Mode Select ER1 ER0 Mode 0 0 No Erase 0 1 Byte Erase 1 0 Block Erase 1 1 Bulk Erase Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED EEPROM General Release Specification MC68HC05V12 — Rev. 1.0 EEPROM

12.4 EEPROM Programming/Erasing Procedure

To program a byte of EEPROM, set EELAT = CPEN = 1, set ER1 = ER0 = 0, write data to the desired address, and then set EEPGM for a time, tEEPGM . In general, all bits should be erased before being programmed. However, if write/erase cycling is a concern, a procedure can be followed to minimize the cycling of each bit in each EEPROM byte. The erased state is 1; therefore, if any bits within the byte need to be changed from a 0 to a 1, the byte must be erased before programming. The decision whether to erase a byte before programming is summarized in Table 12-2. To erase abyte of EEPROM, set EELAT = 1, CPEN = 1, ER1 = 0 and ER0 = 1, write to the address to be erased, and set EEPGM for a time, tEBYT . To erase ablock of EEPROM, set EELAT = 1, CPEN = 1, ER1 = 1 and ER0 = 0, write to any address in the block, and set EEPGM for a time, tEBLOCK . For abulk erase, set EELAT = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any address in the array, and set EEPGM for a time, tEBULK . To terminate the programming or erase sequence, clear EEPGM, delay for a time, tFPV, to allow the programming voltage to fall, and then clear EELAT and CPEN to free up the buses. Following each erase or programming sequence, clear all programming control bits. Table 12-2. EEPROM Write/Erase Cycle Reduction EEPROM Data To Be Programed EEPROM Data Before Programming Erase Before Programming?

00 N o

01 N o

10 Y e s

11 N o

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Operation in Stop and Wait Modes MC68HC05V12 — Rev. 1.0 General Release Specification EEPROM NON-DISCLOSURE AGREEMENT REQUIRED

12.5 Operation in Stop and Wait Modes

The RC oscillator for the EEPROM is disabled automatically when entering stop mode. To help conserve power, the user should disable the RC oscillator before entering wait mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED EEPROM General Release Specification MC68HC05V12 — Rev. 1.0 EEPROM Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification A/D Converter NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 13. A/D Converter

13.1 Contents

13.2 Introduction

The MC68HC05V12 includes a 5-channel, 8-bit, multiplexed input, and a successive approximation analog-to-digital (A/D) converter. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED A/D Converter General Release Specification MC68HC05V12 — Rev. 1.0 A/D Converter

13.3 Analog Section

The following paragraphs describe the analog section.

13.3.1 Ratiometric Conversion

The A/D is ratiometric, with two dedicated pins supplying the reference voltages (VREFH and VREFL ). An input voltage equal to VREFH converts to $FF (full scale) and an input voltage equal to VREFL converts to $00. An input voltage greater than VREFH will convert to $FF with no overflow indication. For ratiometric conversions, the source of each analog input should use VREFH as the supply voltage and be referenced to VREFL .

13.3.2 VREFH and VREFL

The reference supply for the A/D is two dedicated pins rather than being driven by the system power supply lines. The voltage drops in the bonding wires of the heavily loaded system power pins would degrade the accuracy of the A/D conversion. VREFH and VREFL can be any voltage between VSSA and VCCA , as long as VREFH > VREFL ; however, the accuracy of conversions is tested and guaranteed only for VREFL = VSSA and VREFH = VCCA .

13.3.3 Accuracy and Precision

The 8-bit conversions shall be accurate to within± 1 LSB including quantization.

13.3.4 Conversion Process

The A/D reference inputs are applied to a precision internal digital-to- analog (D/A) converter. Control logic drives this D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. The conversion process is monotonic and has no missing codes. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification A/D Converter NON-DISCLOSURE AGREEMENT REQUIRED

13.4 Digital Section

The following paragraphs describe the digital section.

13.4.1 Conversion Times

Each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 MHz.

13.4.2 Internal and Master Oscillators

If the MCU bus (fOP ) frequency is less than 1.0 MHz, an internal RC oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by setting the ADRC bit in the A/D status and control registers to 1. In stop mode, the internal RC oscillator is turned off automatically, although the A/D subsystem remains enabled (ADON remains set). In wait mode the A/D subsystem remains functional. See13.7 A/D during Wait Mode. When the internal RC oscillator is being used as the conversion clock, three limitations apply: 1. The conversion complete flag (COCO) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the RC oscillator and its asynchronism with regard to the MCU bus clock. 2. The conversion process runs at the nominal 1.5 MHz rate, but the conversion results must be transferred to the MCU result registers synchronously with the MCU bus clock so conversion time is limited to a maximum of one channel per bus cycle. 3. If the system clock is running faster than the RC oscillator, the RC oscillator should be turned off and the system clock used as the conversion clock. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED A/D Converter General Release Specification MC68HC05V12 — Rev. 1.0 A/D Converter

13.4.3 Multi-Channel Operation

A multiplexer allows the A/D converter to select one of five external analog signals and four internal reference sources.

13.5 A/D Status and Control Register

The following paragraphs describe the function of the A/D status and control register. COCO — Conversions Complete This read-only status bit is set when a conversion is completed, indicating that the A/D data register contains valid results. This bit is cleared whenever the A/D status and control register is written and a new conversion automatically started, or whenever the A/D data register is read. Once a conversion has been started by writing to the A/D status and control register, conversions of the selected channel will continue every 32 cycles until the A/D status and control register is written again. In this continuous conversion mode the A/D data register will be filled with new data, and the COCO bit set, every 32 cycles. Data from the previous conversion will be overwritten regardless of the state of the COCO bit prior to writing. ADRC — RC Oscillator Control When ADRC is set, the A/D section runs on the internal RC oscillator instead of the CPU clock. The RC oscillator requires a time, tRCON , to stabilize, and results can be inaccurate during this time. $1E Bit 7 654321 Bit 0 Read: COCO ADRC ADON CH4 CH3 CH2 CH1 CH0 Write: Reset: 00000000 = Unimplemented Figure 13-1. A/D Status and Control Register (ADSCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification A/D Converter NON-DISCLOSURE AGREEMENT REQUIRED ADON — A/D On When the A/D is turned on (ADON = 1), it requires a time, tADON , for the current sources to stabilize, and results can be inaccurate during this time. This bit turns on the charge pump. CH4–CH0 — Channel Select Bits CN4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of nine A/D channels, including four internal references. Channels $0−4 correspond to port D input pins on the MCU. Channels $10−$13 are used for internal reference points. In single-chip mode, channel $13 is reserved and converts to $00.Table 13-1 shows the signals selected by the channel select field.

13.6 A/D Data Register

An 8-bit result register is provided. This register is updated each time the COCO bit is set. Table 13-1. A/D Channel Assignments CH4 –CH0 Signal 00–04 AD0–AD4 $10 V REFH $11 (V REFH –VREFL )/2 $12 V REFL $13 Factory Test $1D Bit 7 654321 Bit 0 Read: D7 D6 D5 D4 D3 D2 D1 D0 Write: Reset: Unaffected by reset = Unimplemented Figure 13-2. A/D Data Register (ADDR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED A/D Converter General Release Specification MC68HC05V12 — Rev. 1.0 A/D Converter

13.7 A/D during Wait Mode

The A/D converter continues normal operation during wait mode. To decrease power consumption during wait mode, it is recommended that both the ADON and ADRC bits in the A/D status and control registers be cleared if the A/D converter is not being used. If the A/D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit be cleared. NOTE: As the A/D converter continues to function normally in wait mode, the COCO bit is not cleared.

13.8 A/D during Stop Mode

In stop mode, the comparator and charge pump are turned off and the A/D ceases to function. Any pending conversion is aborted. When the clocks begin oscillation upon leaving stop mode, a finite amount of time passes before the A/D circuits stabilize enough to provide conversions to the specified accuracy. Normally, the delays built into the device when coming out of stop mode are sufficient for this purpose so that no explicit delays need to be built into the software. NOTE: Although the comparator and charge pump are disabled in stop mode, the A/D data and status/control registers are not modified. Disabling the A/D prior to entering stop mode will not affect the stop mode current consumption. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 14. Byte Data Link Controller-Digital (BDLC-D)

14.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) Introduction MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.2 Introduction

The byte data link controller (BDLC) provides access to an external serial communication multiplex bus, operating according to the SAE J1850 protocol.

14.3 Features

BDLC module features include:

• SAE J1850 Class B Data Communications Network Interface Compatible
• 10.4 kbps Variable Pulse Width (VPW) Bit Format
• Digital Noise Filter
• Collision Detection
• Hardware Cyclical Redundancy Check (CRC) Generation and Checking
• Two Power-Saving Modes with Automatic Wakeup on Network Activity
• Polling and CPU Interrupts
• Receive and Transmit Block Modes Supported
• Supports 4X Receive Mode (41.6 kbps)
• Digital Loopback Mode
• Analog Loopback Mode
• In-Frame Response (IFR) Types 0, 1, 2, and 3 Supported Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.4 Functional Description

Figure 14-1. BDLC Block Diagram The CPU interface contains the software addressable registers and provides the link between the CPU and the buffers. The buffers provide storage for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for the encoding and decoding of data bits and special message symbols during transmission and reception. The MUX interface provides the link between the BDLC digital section and the analog physical interface. The wave shaping, driving, and digitizing of data is performed by the physical interface. Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data Communication Network Interface Specification. TO CPU PROTOCOL HANDLER MUX INTERFACE CPU INTERFACE Rx/Tx BUFFERS TO J1850 TRANSCEIVER BDLC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC Operating Modes MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.5 BDLC Operating Modes

The BDLC has five main modes of operation which interact with the power supplies, pins, and the rest of the MCU as shown inFigure 14-2. Figure 14-2. BDLC Operating Modes State Diagram VDD > VDD (MIN) AND Power Off Reset BDLC Stop Run VDD ≤ VDD (MIN) STOP INSTRUCTIONOR FROM ANY MODE BDLC Wait NETWORK ACTIVITY OR WAIT INSTRUCTION AND WCM = 1 WAIT INSTRUCTION AND WCM = 0 ANY MCU RESET SOURCE ASSERTED NO MCU RESET SOURCE ASSERTED ANY MCU RESET SOURCE ASSERTED NETWORK ACTIVITY OR OTHER MCU WAKEUP OTHER MCU WAKEUP (COP, ILLADDR, PU, RESET, LVR, POR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.5.1 Power Off Mode

Power off mode is entered from the reset mode whenever the BDLC supply voltage VDD drops below its minimum specified value for the BDLC to guarantee operation. The BDLC will be placed in the reset mode by low-voltage reset (LVR) before being powered down. In this mode, the pin input and output specifications are not guaranteed.

14.5.2 Reset Mode

This mode is entered from the power off mode whenever the BDLC supply voltage VDD rises above its minimum specified value (VDD(MIN)) and some MCU reset source is asserted. To prevent the BDLC from entering an unknown state, the internal MCU reset is asserted while powering up the BDLC. BDLC reset mode also is entered from any other mode as soon as one of the MCU’s possible reset sources (such as LVR, POR, COP watchdog, reset pin, etc.) is asserted. In this mode, the internal BDLC voltage references are operative, VDD is supplied to the internal circuits, which are held in their reset state, and the internal BDLC system clock is running. Registers will assume their reset condition. Outputs are held in their programmed reset state and inputs and network activity are ignored.

14.5.3 Run Mode

This mode is entered from reset mode after all MCU reset sources are no longer asserted. It is entered from BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from BDLC stop mode whenever network activity is sensed, although messages will not be received properly until the clocks have stabilized and the CPU is in the run mode also. In this mode, normal network operation takes place. The user should ensure that all BDLC transmissions have ceased before exiting this mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.5.4 BDLC Wait Mode

This power-conserving mode is entered automatically from run mode whenever the CPU executes a WAIT instruction and if the WCM bit in the BCR register is cleared previously. In this mode, the BDLC internal clocks continue to run, but the physical interface circuitry is placed in a low-power mode and waits for any activity on the bus. The first passive-to-active transition of the bus wakes up the BDLC and the CPU. If a valid byte is successfully received, a CPU interrupt request will be generated.

14.5.5 BDLC Stop Mode

This power-conserving mode is entered automatically from run mode whenever the CPU executes a STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR register is set previously. In this mode, the BDLC internal clocks are stopped, but the physical interface circuitry is placed in a low-power mode and awaits network activity. If network activity is sensed, then a CPU interrupt request will be generated, restarting the BDLC internal clocks.

14.5.6 Digital Loopback Mode

When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition is caused by failure in the node’s internal circuits or elsewhere in the network, including the node’s analog physical interface. In this mode, the receive digital input (RxPD) is connected to the transmit digital output (TxPD) to form the loopback connection. TxPD is not observable at the output pin.

14.6 BDLC CPU Interface

The CPU interface provides the interface between the CPU and the BDLC. It consists of five user registers. A full description of each register follows. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.6.1 BDLC Control Register 1

This register is used to configure and control the BDLC. IMSG — Ignore Message This bit is used to disable the receiver until a new start of frame (SOF) is detected. 1 = Disable receiver. When set, all BDLC interrupt requests will be masked and the status bits will be held in their reset state. If this bit is set while the BDLC is receiving a message, the rest of the incoming message will be ignored. 0 = Enable receiver. This bit is cleared automatically by the reception of an SOF symbol or a BREAK symbol. It will then generate interrupt requests and will allow changes of the status register to occur. However, these interrupts may still be masked by the interrupt enable (IE) bit. CLKS — Clock select The nominal BDLC operating frequency (fBDLC ) must always be 1.048576 MHz or 1 MHz for J1850 bus communications to take place. The CLKS register bit is provided to allow the user to indicate to the BDLC which frequency (1.048576 MHz or 1 MHz) is used so that each symbol time can be adjusted automatically. 1 = Binary frequency (1.048576 MHz) is used for fBDLC . 0 = Integer frequency (1 MHz) is used. for fBDLC. R1 and R0 — Rate Select These bits determine the amount by which the frequency of the MCU system clock signal (fOP ) is divided to form the MUX interface clock (fBDLC ) which defines the basic timing resolution of the MUX interface. $003A Bit 7 654321 Bit 0 Read: IMSG CLKS R1 R0 IE WCM Write: Reset: 11100000 = Unimplemented Figure 14-3. BDLC Control Register 1 (BCR1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED They may be written only once after reset and then they become read- only bits. The value programmed into these bits is dependent on the chosen MCU system clock frequency perTable 14-1 and Table 14-2. IE — Interrupt Enable This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not affect CPU interrupt requests when exiting BDLC stop or wait modes. By performing the specified actions upon the BDLC’s registers, interrupt requests will be maintained until all interrupt request sources are cleared. By performing the specified actions upon the BDLC’s registers, interrupts pending at the time that this bit is cleared may be lost. 1 = Enable interrupt requests from BDLC 0 = Disable interrupt requests from BDLC If the programmer does not want to use the interrupt capability of the BDLC, the BDLC state vector register (BSVR) can be polled periodically by the programmer to determine BDLC states. Refer to

14.6.3 BDLC State Vector Register for a description of BSVR

register. Table 14-1. BDLC Rate Selection for Binary Frequencies Clock Frequency R1 R0 Division fBDLC fOP =1.048576 MHz 0 0 1 1.048576 MHz fOP = 2.09715 MHz 0 1 2 1.048576 MHz fOP = 4.19430 MHz (see Note) 1 0 4 1.048576 MHz fOP = 8.38861 MHz (see Note) 1 1 8 1.048576 MHz NOTE: Invalid option on this MCU Table 14-2. BDLC Rate Selection for Integer Frequencies Clock Frequency R1 R0 Division fBDLC fOP = 1.00000 MHz 0 0 1 1.000000 MHz fOP = 2.00000 MHz 5 1 2 1.000000 MHz fOP = 4.00000 MHz (see Note) 1 0 4 1.000000 MHz fOP = 8.00000 MHz (see Note) 1 1 8 1.000000 MHz NOTE: Invalid option on this MCU Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) WCM — Wait Clock Mode This bit determines the operation of the BDLC during CPU wait mode. See 14.5.5 BDLC Stop Mode and14.5.4 BDLC Wait Mode for more details on its use. 1 = Stop BDLC internal clocks during CPU wait mode 0 = Run BDLC internal clocks during CPU wait mode

14.6.2 BDLC Control Register 2

This register controls transmitter operations of the BDLC. ALBE — Analog Loopback Mode This bit is used to reset the BDLC state machine to a known state after the user has put the off-chip analog transceiver in loopback mode. When the user clears ALBE to indicate that the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol before attempting to transmit. 1 = Indicates to the BDLC that the off-chip analog transceiver is being put in analog loopback mode. 0 = When ALBE is cleared, the BDLC requires the bus to be idle for a minimum of end-of-frame symbol (Ttv4) time before allowing a reception of a message. The BDLC requires the bus to be idle for a minimum of inter-frame separator symbol (Ttv6) time before allowing any message to be transmitted. DLBE — Digital Loopback Mode This bit determines the source to which the digital receive input is connected to and can be used to isolate the bus fault condition. If a fault condition has been detected on the bus, this control bit allows the programmer to connect the digital transmit output to the digital receive input. In this configuration, data sent from the transmit buffer should $003B Bit 7 654321 Bit 0 Read: ALBE DLBE RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 Write: Reset: 11000000 Figure 14-4. BDLC Control Register 2 (BCR2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED be reflected back into the receive buffer. If no faults exist in the digital block, the fault is in the physical interface block or elsewhere on the J1850 bus. 1 = When set, RxPD is connected to TxPD. The BDLC is now in digital loopback mode of operation and the TxPD signal is not observable on the TXP pin. 0 = When cleared, RxPD is connected to the RXP input pin and the BDLC is taken out of digital loopback mode. Now the BDLC can drive and receive from the J1850 bus normally after the bus is idle for at least a Ttv4 time for receive and a Ttv6 time for transmit. RX4XE — Receive 4X Enable This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature is useful for fast download of data into a J1850 node for diagnostic or factory programming. 1 = When set, the BDLC is put in 4X receive-only operation. 0 = When cleared, the BDLC transmits and receives at 10.4 kbps. Reception of a BREAK symbol automatically clears this bit and sets BSVR (see14.7.3 Rx and Tx Shadow Registers) register to $1C. NBFS — Normalization Bit Format Select This bit controls the format of the normalization bit (NB). SAE J1850 strongly encourages the use of an active long, 0, for in-frame responses containing CRC and active short, 1, for in-frame responses without CRC. 1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR) ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR) does not end with a CRC byte. 0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR) ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR) does not end with a CRC byte. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) TEOD — Transmit End of Data The programmer sets this bit to indicate the end of a message being sent by the BDLC. It will append an 8-bit CRC after completing transmission of the current byte. This bit also is used to end an IFR. If the transmit shadow register (refer to14.7.3 Rx and Tx Shadow Registers for a description of the transmit shadow register) is full when TEOD is set, the CRC byte will be transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have been transmitted. Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector register (BSVR) is cleared to allow lower priority interrupts to occur. 1 = Transmit EOD symbol 0 = The TEOD bit will be cleared automatically at the rising edge of the first CRC bit that is sent or whenever an error is detected. If TEOD is used to end an IFR transmission, it is cleared when the BDLC receives a valid EOD symbol or an error condition occurs. TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control These three bits control the type of in-frame response being sent. The programmer should not set more than one of these control bits to 1 at any given time. However, if more than one of these three control bits are set to 1, the priority encoding logic will force the internal register bits to a known value as shown inTable 14-3. But, when these bits are read, they will be the same as written earlier. For instance, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally they’ll be encoded as 010. However, when these bits are later read back, the value will still be 011. Table 14-3. Transmit In-Frame Response Control Bit Priority Encoding WRITE (then READ BACK) TSIFR WRITE (then READ BACK) TMIFR1 WRITE (then READ BACK) TMIFR0 ACTUAL TSIFR ACTUAL TMIFR1 ACTUAL TMIFR0 000 0 0 0 1XX 1 0 0 01X 0 1 0 001 0 0 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED The BDLC supports the in-frame response (IFR) feature of J1850. The three types of J1850 IFR are shown inFigure 14-5. Figure 14-5. Types of In-Frame Response TSIFR — Transmit Single Byte IFR with No CRC (Type 1) This bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a single byte IFR with no CRC. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by the byte in the BDR. 0 = The TSIFR bit will be automatically cleared once the BDLC has successfully transmitted the byte in the BDR onto the bus, or TEOD is set by the CPU, or an error is detected on the bus. If a loss of arbitration occurs when the BDLC attempts to transmit the byte in the BDLC, once the IFR byte winning arbitration completes transmission, the BDLC will again attempt to transmit the byte in the BDR (with no normalization bit). The BDLC will continue transmission attempts until an error is detected on the bus, or TEOD is set by the CPU, or the BDLC transmission is successful. If loss of arbitration SOF HEADER DATA FIELD CRC EOD TYPE 0 — NO IFR HEADER DATA FIELD CRC EOD TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER HEADER DATA FIELD CRC EOD TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER HEADER DATA FIELD CRC EOD TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS ID1 ID N IFR DATA FIELD CRC NB NB NB ID SOFSOFSOF EOF EOD EOF EOD EOFEOD EOF NB = Normalized Bit ID = Identifier (usually the physical address of the responder(s)) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) occurs in the last two bits of the IFR byte, two additional 1 bits will not be sent out because the BDLC will attempt to retransmit the byte in the Tx shift register after the IFR byte winning arbitration completes transmission. If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received from the bus, the TSIFR bit will remain in the reset state, and no attempt will be made to transmit the IFR byte. TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) This bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. If this bit is set prior to a valid EOD being received with no CRC error and once the EOD symbol has been received, the BDLC will attempt to transmit the appropriate normalization/format symbol, followed by the byte in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt will occur, similar to the main message transmit sequence. The programmer should then load the next byte of the IFR into the BDR for transmission. When the last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the BCR register. This will instruct the BDLC to transmit a CRC byte once the byte in the BDR is transmitted, and then transmit an EOD symbol, indicating the end of the IFR portion of the message frame. The TMIFR1 bit will be automatically cleared once the BDLC has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR after the TDRE interrupt. If a loss of arbitration occurs when the BDLC is transmitting any multiple byte IFR, BDLC will go to the loss of arbitration state, set the appropriate flag, and cease transmission. If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be cleared and no attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will be sent out. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED If the programmer wishes to transmit a single byte followed by a CRC byte, the programmer should load the byte into the BDR before the EOD symbol has been received and then set the TMIFR1 bit. Once the EOD interrupt occurs, the programmer should then set the TEOD bit in the BCR. This will result in the byte in the BDR being the only byte transmitted before the IFR CRC byte, and no TDRE interrupt will be generated. If the programmer attempts to set the TMIFR1 bit immediately after the EOD symbol has been received from the bus, the TMIFR1 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into BDR register. After TEOD has been set and the last IFR byte has been transmitted, the CRC byte is transmitted. 0 = The TMIFR1 bit will be cleared automatically, once the BDLC has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR after the TDRE interrupt. TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 2) This bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR without CRC. If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received, the BDLC will attempt to transmit the appropriate normalization/format symbol, followed by the byte in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt will occur, similar to the main message transmit sequence. The programmer should then load the next byte of the IFR into the BDR for transmission. When the last byte of the IFR has been loaded into the BDR, the programmer should set Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) the TEOD bit in the BCR2 register. This will instruct the BDLC to transmit an EOD symbol, indicating the end of the IFR portion of the message frame. The BDLC will not append a CRC. The TMIFR0 bit will be cleared automatically, once the BDLC has successfully transmitted the EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR following the TDRE interrupt. If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will be cleared, and no attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte, two additional one bits (active short bits) will be sent out. If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the bus, the TMIFR0 bit will remain in the reset state and no attempt will be made to transmit an IFR byte. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into BDR register. After TEOD has been set, the last IFR byte to be transmitted will be the last byte which was written into the BDR register. 0 = The TMIFR0 bit will be cleared automatically once the BDLC has successfully transmitted the EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR after the TDRE interrupt.

14.6.3 BDLC State Vector Register

This register is provided to substantially decrease the CPU overhead associated with servicing interrupts while under operation of a MUX protocol. It provides an index offset that is directly related to the BDLC’s current state, which can be used with a user supplied jump table to rapidly enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state machine in software. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED I0, I1, I2, I3 — Interrupt Source These bits indicate the source of the interrupt request that is currently pending. The encoding of these bits is found inTable 14-4. Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except when the BDLC data register needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the BSVR register followed by a read of BDR. TDRE can either be cleared by a read of the BSVR register followed by a write to the BDLC BDR register or by setting the TEOD bit in BCR2. A read of the BSVR in either a symbol invalid or loss of arbitration condition will result in removal of a pending Tx data register empty condition. $003C Bit 7 654321 Bit 0 Read: 0 0 I3 I2 I1 I0 0 0 Write: Reset: 00000000 = Unimplemented Figure 14-6. BDLC State Vector Register (BSVR) Table 14-4. Interrupt Sources BSVR I3 I2 I1 I0 Interrupt Source Priority $ 0 0 0000 N o Interrupts Pending 0 (lowest) $ 0 4 0001 Received EOF 1 $ 0 8 0010 Received IFR byte (RXIFR) 2 $ 0 C 0011 R x data register full (RDRF) 3 $ 1 0 0100 T x data register empty (TDRE) 4 $ 1 4 0101 Loss of arbitration 5 $ 1 8 0110 CRC error 6 $ 1 C 0111 Symbol invalid or out of range 7 $ 2 0 1000 W a k e u p 8 (highest) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) Upon receiving a BDLC interrupt, the user may read the value within the BSVR, transferring it to the CPU’s index register. The value may then be used to index into a jump table with entries four bytes apart to quickly enter the appropriate service routine. For example: SERVICELDX BSVR Fetch State Vector Number JMP JMPTAB,XEnter service routine, * (must end in an ’RTI’) JMPTAB JMP SERVE0Service condition #0 NOP JMP SERVE1Service condition #1 NOP JMP SERVE2Service condition #2 NOP .. . . JMP SERVE8Service condition #8 END NOTE: The NOPs are just used to align the JMPs onto 4-byte boundaries so that the value in the BSVR may be used intact. Each of the service routines must end with an RTI instruction to guarantee correct continued operation of the device. Note also that the first entry can be omitted since it corresponds to no interrupt occurring. The service routines should clear all of the sources that are causing the pending interrupts. Note that the clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0, I1, and I2 of the BSVR will then reflect the source of the remaining interrupt request. If fewer states are used or if a different software approach is taken, the jump table may be made smaller or omitted altogether.

14.6.4 BDLC Data Register

This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass data received from the J1850 bus to the CPU. Each data byte (after the first one) should be written only after a Tx data register empty (TDRE) interrupt has occurred or the BSVR register has been polled indicating this condition. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED Data read from this register will be the last data byte received from the J1850 bus. This received data should only be read after a Rx data register full (RDRF) interrupt has occurred. The BDR register is double buffered via a transmit shadow register and a receive shadow register. After the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the TDRE flag is set, and the shadow register is ready to accept the next byte of data. The receive shadow register works similarly. Once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. The RDRF flag is set to indicate that a new byte of data has been received. The programmer has one BDLC byte reception time to read the shadow register and clear the RDRF flag before the shadow register is overwritten by the newly received byte. To abort an in-progress transmission, the programmer should simply stop loading more data into the BDR. This will cause a transmitter underrun error and the BDLC automatically will disable the transmitter on the next non-byte boundary. This means that the earliest a transmission can be halted is after at least one byte (plus two extra 1 bits) has been transmitted. The receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error.

14.6.5 BDLC Analog and Roundtrip Delay

This register is used to program the BDLC so that it compensates for various delays of different external transceivers. The default delay value is 16µs. The BARD offset bits range from 0 through 15.Table 14-1 illustrates the corresponding expected delays on the external $003D Bit 7 654321 Bit 0 Read: D7 D6 D5 D4 D3 D2 D1 D0 Write: Reset: Indeterminate after reset Figure 14-7. BDLC Data Register (BDR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) transceivers to be connected to the BDLC. This allows flexibility of timing adjustments from 9µs to 24 ms in 1µs steps. This register can be written to only once after a reset. Subsequent writes to the register will have no effect. Read: Any time Write: Once after reset ATE — Analog Transceiver Enable The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog transceiver. 1 = Select on-board analog transceiver 0 = Select off-chip analog transceiver NOTE: This device does not contain an on-board transceiver. This bit should be programmed to a logic 0 for proper operation. RXPOL — RXP Polarity Select 1 = Receiver polarity is J1850 protocol without an inversion 0 = Receiver polarity is inverted J1850 protocol $003E Bit 7 654321 Bit 0 Read: ATE RXPOL 0 0 BO3 BO2 BO1 BO0 Write: Reset: 11000111 Figure 14-8. BDLC Analog Roundtrip Delay Register (BARD) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED BO3 −BO0 — BARD Offset bits Table 14-5 shows the expected transceiver delay with respect to BARD offset values: Table 14-5. BARD Offset Delays BARD Offset Bits (BO3, BO2, BO1, BO0) Corresponding Expected Transceiver’s Delays (µs) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.7 BDLC Protocol Handler

The protocol handler is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The protocol handler conforms to “SAE J1850− Class B Data Communications Network Interface.”

14.7.1 Protocol Architecture

The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift register, Tx shift register, and loopback multiplexer as shown inFigure 14-9. Each block is described in more detail. Figure 14-9. BDLC Protocol Handler Outline Rx SHIFT REGISTER TO CPU INTERFACE AND Rx/Tx BUFFERS STATE MACHINE Rx DATA Tx DATA CONTROL Tx SHIFT REGISTER TxPD RxPD CONTROL Rx SHADOW REGISTER Tx SHADOW REGISTER LOOPBACK RXP LOOPBACK CONTROL TXP MULTIPLEXERDLBE FROM BCR2 ALBE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC Protocol Handler MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.7.2 Rx and Tx Shift Registers

The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850 bus.

14.7.3 Rx and Tx Shadow Registers

Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to the Rx shadow register and RDRF or RXIFR is set and interrupt is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new data byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to shift in the next byte of data. Data in Rx shadow register must be retrieved by the CPU before it is overwritten by new data from the Rx shift register. Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register is ready to accept new data from the CPU.

14.7.4 Digital Loopback Multiplexer

The digital loopback multiplexer connects RXP to TXP internally, when the DLBE bit in BCR2 register is set.

14.7.5 State Machine

All functions associated with performing the protocol are executed or controlled by the state machine. The state machine is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The following sections describe the BDLC’s actions in a variety of situations. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) 14.7.5.1 4X Mode The BDLC can exist on the same J1850 bus as modules which use a special 4X (41.6 kbps) mode of J1850 VPW operation. The BDLC cannot transmit in 4X mode, but can receive messages in 4X mode, if the RX4X bit is set in the BCR2 register. If the RX4X bit is not set in the BCR2 register, any 4X message on the J1850 bus is treated as noise by the BDLC and is ignored.

14.7.5.2 Receiving a Message in Block Mode

Although not a part of the SAE J1850 protocol, the BDLC does allow for a special block mode of operation of the receiver. As far as the BDLC is concerned, a block mode message is simply a long J1850 frame that contains an indefinite number of data bytes. All of the other features of the frame remain the same, including the SOF, CRC, and EOD symbols. Another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. This is usually accomplished by sending a special predefined message.

14.7.5.3 Transmitting a Message in Block Mode

A block mode message is transmitted inherently by simply loading the bytes one by one into the BDR register until the message is complete. The programmer should wait until the TDRE flag is set prior to writing a new byte of data into the BDR register. The BDLC does not contain any predefined maximum J1850 message length requirement. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC Protocol Handler MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.7.6 J1850 Bus Errors

The BDLC detects several types of transmit and receive errors which can occur during the transmission of a message onto the J1850 bus. If the BDLC is transmitting a message and the message received contains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmission error. When a transmission error is detected, the BDLC will immediately cease transmitting. The error condition is reflected in the BSVR register. If the interrupt enable bit (IE) is set, an interrupt request from the BDLC is generated.

14.7.6.1 CRC Error

A CRC error is detected when the data bytes and CRC byte of a received message are processed, and the CRC calculation result is not equal to $C4. The CRC code should detect any single-bit and 2- bit errors, as well as all 8-bit burst errors and almost all other types of errors. CRC error flag is set when a CRC error is detected.

14.7.6.2 Symbol Error

A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the J1850 bus. However, if the BDLC is transmitting when this happens, it will be treated as a loss of arbitration rather than a transmitter error. Symbol invalid or out-of- range flag is set when a symbol error is detected.

14.7.6.3 Framing Error

A framing error is detected if an EOD or EOF symbol is detected on a non-byte boundary from the J1850 bus. Symbol invalid or out-of-range flag is set when a framing error is detected.

14.7.6.4 Bus Fault

If a bus fault occurs, the response of the BDLC will depend upon the type of bus fault. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) If the bus is shorted to Vbatt, the BDLC will wait for the bus to fall to a passive state before it will attempt to transmit a message. As long as the short remains, the BDLC will never attempt to transmit a message onto the J1850 bus. If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit the message, and then detect a transmission error, since the short to ground would not allow the bus to be driven to the active (dominant) state. The BDLC will abort that transmission and wait for the next CPU command to transmit. In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC will resume normal operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850 bus.

14.7.6.5 Break (BREAK)

If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol interrupt will be generated. Reading the BSVR register will clear this interrupt condition. The BDLC will wait for bus to idle, then wait for SOF. The BDLC cannot transmit a BREAK symbol. It can receive only a BREAK symbol from the J1850 bus. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.8 BDLC MUX Interface

The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface.

14.8.1 Rx Digital Filter

The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the incoming message. An outline of the digital filter is shown inFigure 14-10. Table 14-6. BDLC J1850 Bus Error Summary Error Condition BDLC Function Bus short to Battery The BDLC will not transmit until the bus is idle. Bus short to Gnd Fault condition is reflected in BSVR as invalid symbol. Invalid symbol: BDLC receives invalid bits (noise). The BDLC will abort transmission immediately. Invalid symbol interrupt will be generated. Framing error Invalid symbol interrupt will be generated. The BDLC will wait for SOF . CRC error CRC error interrupt will be generated. The BDLC will wait for SOF . BDLC receives BREAK symbol The BDLC will wait for the next valid SOF . Invalid symbol interrupt will be generated. Invalid symbol: BDLC sends an EOD but receives an active symbol. Invalid symbol interrupt will be generated. The BDLC will wait for SOF . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) Figure 14-10. BDLC Rx Digital Filter Block Diagram

14.8.1.1 Operation

The clock for the digital filter is provided by the MUX interface clock. At each positive edge of the clock signal, the current state of the receiver physical interface (RxP) signal is sampled. The RxP signal state is used to determine whether the counter should increment or decrement at the next negative edge of the clock signal. The counter will increment if the input data sample is high but decrement if the input sample is low. The counter will thus progress up toward 15 if, on average, the RxP signal remains high or progress down towards 0 if, on average, the RxP signal remains low. When the counter eventually reaches the value 15, the digital filter decides that the condition of the RxP signal is at a stable logic level one and the data latch is set, causing the filtered Rx data signal to become a logic level 1. Furthermore, the counter is prevented from overflowing and can only be decremented from this state. Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition of the RxP signal is at a stable logic level zero and the data latch is reset, causing the filtered Rx data signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only be incremented from this state. The data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the RxP signal. 4-BIT UP/DOWN COUNTER UP/DOWN OUT dq FILTERED Rx DATA OUT MUX INTERFACE CLOCK INPUT SYNC dq Rx DATA FROM PHYSICAL INTERFACE (RxP)

4 EDGE AND

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.8.1.2 Performance

The performance of the digital filter is best described in the time domain rather than the frequency domain. If the signal on the RxP signal transitions, then there will be a delay before that transition appears at the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. This filter delay must be taken into account when performing message arbitration. For example, if the frequency of the MUX interface clock (fBDLC ) is 1.0486 MHz, then the period (tBDLC ) is 954ns and the maximum filter delay in the absence of noise will be 15.259µs. The effect of random noise on the RxP signal depends on the characteristics of the noise itself. Narrow noise pulses on the RxP signal will be completely ignored if they are shorter than the filter delay. This provides a degree of low pass filtering. If noise occurs during a symbol transition, the detection of that transition may be delayed by an amount equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is truly occurring within the noise. Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length will be detected by the next stage of the BDLC’s receiver as an invalid symbol. Noise pulses that are longer than the shortest allowable symbol length will normally be detected as an invalid symbol or as invalid data when the frame’s CRC is checked. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.8.2 J1850 Frame Format

All messages transmitted on the J1850 bus are structured using this format: Figure 14-11. J1850 Bus Message Format (VPW) SAE J1850 states that each message has a maximum length of 101 bit times or 12 bytes (excluding SOF, EOD, NB, and EOF). SOF — Start of Frame Symbol All messages transmitted onto the J1850 bus must begin with an SOF symbol. This indicates the start of a new message transmission to any listeners on the J1850 bus. The SOF symbol is not used in the CRC calculation. Data — In Message Data Bytes The data bytes contained in the message include the message priority/type, message ID byte, and any actual data being transmitted to the receiving node. The message format used by the BDLC is similar to the 3-byte consolidated header message format outlined by the SAE J1850 document. See “SAE J1850 - Class B Data Communications Network Interface,” for more information about 1- and 3-byte headers. Messages transmitted by the BDLC onto the J1850 bus must contain at least one data byte, and, therefore, can be as short as one data byte and one CRC byte. Each data byte in the message is eight bits in length and is transmitted MSB to LSB. SOF E O D EOF PRIORITY MESSAGE Datan CRC IFR I F SIDLE IDLEID (Data1)(Data0) OPTIONAL Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED CRC — Cyclical Redundancy Check Byte This byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message. The BDLC calculates the CRC byte and appends it onto any messages transmitted onto the J1850 bus, and also performs CRC detection on any messages it receives from the J1850 bus. CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1. The remainder polynomial is initially set to all ones, and then each byte in the message after the SOF symbol is serially processed through the CRC generation circuitry. The one’s complement of the remainder then becomes the 8-bit CRC byte, which is appended to the message after the data bytes, in MSB to LSB order. When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the SOF and EOD symbols, but including the CRC byte, are used to check the CRC. If the message is error free, the remainder polynomial will equal X7 + X6 + X2 ($C4), regardless of the data contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as a CRC error and set the CRC error flag in the BSVR register. EOD — End of Data Symbol The EOD symbol is a short passive period on the J1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. No flag is set upon reception of EOD symbol. IFR — In-Frame Response Bytes The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame response should review theSAE J1850 Class B Data Communications Network Interface Specification EOF — End of Frame Symbol This symbol is a passive period on the J1850 bus, longer than an EOD symbol, which signifies the end of a message. Since an EOF symbol is longer than an EOD symbol, if no response is transmitted Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) after an EOD symbol, it becomes an EOF, and the message is assumed to be completed. EOF flag is set upon receiving the EOF symbol. IFS — Inter-Frame Separation Symbol The IFS symbol is a passive period on the J1850 bus which allows proper synchronization between nodes during continuous message transmission. The IFS symbol is transmitted by a node following the completion of the EOF period. When the last byte of a message has been transmitted onto the J1850 bus, and the EOF symbol time has expired, all nodes must then wait for the IFS symbol time to expire before transmitting an SOF, marking the beginning of another message. However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a rising edge is detected before the IFS time has expired, it will internally synchronize to that edge. If a write to the BDR register (initiate transmission) occurred on or before 104 X tBDLC from the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU write to the BDR register occurred after

104 X tBDLC from the detection of the rising edge, then the BDLC will

not transmit, but will wait for the next IFS period to expire before attempting to transmit the byte. A rising edge may occur during the IFS period because of varying clock tolerances and loading of the J1850 bus, causing different nodes to observe the completion of the IFS period at different times. Receivers must synchronize to any SOF occurring during an IFS period to allow for individual clock tolerances. BREAK — Break If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission error had occurred, and halts transmission. The BDLC cannot transmit a BREAK symbol. If while receiving a message the BDLC detects a BREAK symbol, it treats the BREAK as a reception error and sets the invalid symbol flag. If while receiving a message in 4X mode, the BDLC detects a BREAK Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED symbol, it treats the BREAK as a reception error, sets BSVR register to $1C, and exits 4X mode. The RX4XE bit in BCR2 is cleared automatically upon reception of the BREAK symbol. Idle Bus An idle condition exists on the bus during any passive period after expiration of the IFS period. Any node sensing an idle bus condition can begin transmission immediately.

14.8.3 J1850 VPW Symbols

Huntsinger’s variable pulse width modulation (VPW) is an encoding technique in which each bit is defined by the time between successive transitions and by the level of the bus between transitions, active or passive. Active and passive bits are used alternately. Each logic 1 or logic 0 contains a single transition, and can be at either the active or passive level and one of two lengths, either 64µs or 128µs (tNOM at 10.4 kbps baud rate), depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS symbols will always be encoded at an assigned level and length. SeeFigure 14-12. Each message will begin with an SOF symbol, an active symbol, and therefore each data byte (including the CRC byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate.

14.8.3.1 Logic 0

A logic 0 is defined as either an active-to-passive transition followed by a passive period 64µs in length or a passive-to-active transition followed by an active period 128µs in length (Figure 14-12(a)). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.8.3.2 Logic 1

A logic 1 is defined as either an active-to-passive transition followed by a passive period 128µs in length or a passive-to-active transition followed by an active period 64µs in length (Figure 14-12(b)). Figure 14-12. J1850 VPW Symbols 128 µs ACTIVE PASSIVE 64 µsOR LOGIC 0 128 µs ACTIVE PASSIVE 64 µsOR LOGIC 1 200 µs ACTIVE PASSIVE START OF FRAME 200 µs END OF DATA 280 µs ACTIVE PASSIVE END OF FRAME □ 240µs BREAK (a) (b) (c) (d) (e) (f) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.8.3.3 Normalization Bit (NB)

The NB symbol has the same property as a logic 1 or a logic 0.

14.8.3.4 Start of Frame Symbol (SOF)

The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length (Figure 14-12(c)). This allows the data bytes which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.

14.8.4 EOD − End of Data Symbol

The EOD symbol is defined as an active-to-passive transition followed by a passive period 200µs in length (Figure 14-12(d)).

14.8.4.1 End of Frame Symbol (EOF)

The EOF symbol is defined as an active-to-passive transition followed by a passive period 280µs in length (Figure 14-12(e)). If there is no IFR byte transmitted after an EOD symbol is transmitted, after another 80µs the EOD becomes an EOF, indicating the completion of the message.

14.8.4.2 Inter-Frame Separation Symbol (IFS)

The IFS symbol is defined as a passive period 300µs in length. The IFS symbol contains no transition, since it always follows an EOF symbol when it is used.

14.8.4.3 Break Signal (BREAK)

The BREAK signal is defined as a passive-to-active transition followed by an active period of at least 240µs (Figure 14-12(f)). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.8.5 J1850 VPW Valid/Invalid Bits and Symbols

The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow for variations in oscillator frequencies. In many cases, the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol. Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a single period of the MUX interface clock (tBDLC ), an apparent separation in these maximum time/minimum time concurrences equal to one cycle of tBDLC occurs. This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols, without reducing the valid window for receiving bits and symbols from transmitters onto the J1850 bus having varying oscillator frequencies. In VPW bit encoding, the tolerances for the both passive and active data bits and symbols are defined with no gaps between definitions. For example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1, and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED Figure 14-13. J1850 VPW Passive Symbols

14.8.5.1 Invalid Passive Bit

If the passive-to-active transition beginning the next data bit or symbol occurs between the active-to-passive transition beginning the current data bit or symbol and ttrvp1(Min), the current bit would be invalid. See Figure 14-13(1).

14.8.5.2 Valid Passive Logic 0

If the passive-to-active transition beginning the next data bit or symbol occurs between ttrvp1(Min) and ttrvp1(Max), the current bit would be considered a logic 0. SeeFigure 14-13(2). ttrvp1(Min) ttrvp1(Max) trvp2(Max) ttrvp1(Max)ttrvp1(Min) (1) INVALID PASSIVE BIT (2) VALID PASSIVE LOGIC 0 (3) VALID PASSIVE LOGIC 1 64 µs 128 µs trvp2(Max) ttrvp3(Max) (4) VALID EOD SYMBOL 200 µs ACTIVE PASSIVE ACTIVE PASSIVE ACTIVE PASSIVE ACTIVE PASSIVE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.8.5.3 Valid Passive Logic 1

If the passive-to-active transition beginning the next data bit or symbol occurs between ttrvp1(Max) and ttrvp2(Max), the current bit would be considered a logic 1. SeeFigure 14-13(3).

14.8.5.4 Valid EOD Symbol

If the passive-to-active transition beginning the next data bit or symbol occurs between ttrvp2(Max) and ttrvp3(Max), the current symbol would be considered a valid EOD symbol. SeeFigure 14-13(4). Figure 14-14. J1850 VPW EOF and IFS Symbols ttv6(Min) (2) VALID EOF+ IFS SYMBOL 280 µs 300 µs ttrv4(Min) ttrv4(Max) (1) VALID EOF SYMBOL ACTIVE PASSIVE ACTIVE PASSIVE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.8.5.5 Valid EOF and IFS Symbol

InFigure 14-14(1), if the passive-to-active transition beginning the SOF symbol of the next message occurs between ttrv4(Min) and ttrv4(Max), the current symbol will be considered a valid EOF symbol. If the passive-to- active transition beginning the SOF symbol of the next message occurs after ttv6(Min), the current symbol will be considered a valid EOF symbol followed by a valid IFS symbol. SeeFigure 14-14(2). All nodes must wait until a valid IFS symbol time has expired before beginning transmission. However, due to variations in clock frequencies and bus loading, some nodes may recognize a valid IFS symbol before others and immediately begin transmitting. Therefore, any time a node waiting to transmit detects a passive-to-active transition once a valid EOF has been detected, it should begin transmission immediately, initiating the arbitration process.

14.8.5.6 Idle Bus

If the passive-to-active transition beginning the SOF symbol of the next message does not occur befored,the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. Figure 14-15. J1850 VPW Active Symbols ttrva2(Min) ttva2(Max) ttrva1(Max) ttrva2(Max)ttrva2(Min) (1) INVALID ACTIVE BIT (2) VALID ACTIVE LOGIC 1 (3) VALID ACTIVE LOGIC 0 64 µs 128 µs ttrva1(Max) ttva3(Max) (4) VALID SOF SYMBOL 200 µs ACTIVE PASSIVE ACTIVE PASSIVE ACTIVE PASSIVE ACTIVE PASSIVE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.8.5.7 Invalid Active Bit

If the active-to-passive transition beginning the next data bit or symbol occurs between the passive-to-active transition beginning the current data bit or symbol and ttrva2(Min), the current bit would be invalid. See Figure 14-15(1).

14.8.5.8 Valid Active Logic 1

If the active-to-passive transition beginning the next data bit or symbol occurs between ttrva2(Min) and ttrva2(Max), the current bit would be considered a logic 1. SeeFigure 14-15(2).

14.8.5.9 Valid Active Logic 0

If the active-to-passive transition beginning the next data bit or symbol occurs between ttrva2(Max) and ttva1(Max), the current bit would be considered a logic 0. SeeFigure 14-15(3).

14.8.5.10 Valid SOF Symbol

If the active-to-passive transition beginning the next data bit or symbol occurs between ttrva1(Max) and ttva3(Max), the current symbol would be considered a valid SOF symbol. SeeFigure 14-15(4). Figure 14-16. J1850 VPW BREAK Symbol (2) VALID BREAK 240 µs ttrv6(Min) SYMBOL ACTIVE PASSIVE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.8.5.11 Valid BREAK Symbol

If the next active-to-passive transition does not occur until after ttrv6(Min), the current symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a SOF symbol beginning the next message to be transmitted onto the J1850 bus. SeeFigure 14-16.

14.8.6 Message Arbitration

Message arbitration on the J1850 bus is accomplished in a non- destructive manner, allowing the message with the highest priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it automatically waits until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the SOF symbol and continue with each bit thereafter. The VPW symbols and J1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive type) simultaneously transmitted. Hence logic 0s are said to be dominant and logic 1s are said to be recessive. Whenever a node detects a dominant bit when it transmitted a recessive bit, it loses arbitration and immediately stops transmitting. This is known as bitwise arbitration. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) Figure 14-17. J1850 VPW Bitwise Arbitrations During arbitration, or even throughout the transmitting message, when an opposite bit is detected, transmission is immediately stopped unless it occurs on the eighth bit of a byte. In this case, the BDLC automatically will append two extra 1 bits and then stop transmitting. These two extra bits will be arbitrated normally and thus will not interfere with another message. The second 1 bit will not be sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two extra ones will not corrupt the current message. However, if the BDLC has lost arbitration due to noise on the bus, then the two extra ones will ensure that the current message will be detected and ignored as a noise- corrupted message. Since a 0 dominates a 1, the message with the lowest value will have the highest priority and will always win arbitration, for instance, a message with priority 000 will win arbitration over a message with priority 011. This method of arbitration will work no matter how many bits of priority encoding are contained in the message. Transmitter A Transmitter B J1850 Bus SOF Data Bit 1 Data Bit 4 Data Bit 5 TRANSMITTER A DETECTS AN ACTIVE STATE ON THE BUS AND STOPS TRANSMITTER B WINS PASSIVE ACTIVE PASSIVE ACTIVE PASSIVE ACTIVE Data Bit 2 Data Bit 3 ARBITRATION AND CONTINUES TRANSMITTING. TRANSMITTING. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Byte Data Link Controller-Digital (BDLC-D) MC68HC05V12 — Rev. 1.0 General Release Specification Byte Data Link Controller-Digital (BDLC-D) NON-DISCLOSURE AGREEMENT REQUIRED

14.9 BDLC Application Notes

14.9.1 Initialization

The MCU will first write to the BDLC control register (BCR1). This byte should configure the rate select bits to configure the MUX interface clock to its nominal value, clear the IMSG bit to enable normal BDLC operations, and set the interrupt enable bit if desired.

14.9.2 BDLC Stop Mode

This power-conserving mode is entered automatically from the run mode whenever the CPU executes a STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR register is previously set. This is the lowest power mode that the BDLC can enter. A subsequent passive-to-active transition on the J1850 bus will cause the BDLC to wake up and generate a non-maskable CPU interrupt request. When a STOP instruction is used to put the BDLC in stop mode, the BDLC will not correctly receive the byte that woke it up. This is due to a required oscillator stabilization delay for the BDLC internal operating clocks to restart. If a WAIT instruction is used to put the BDLC in stop mode, the BDLC is guaranteed to receive correctly the byte which woke it up, if and only if an EOF has been detected prior to issuing the WAIT instruction by the CPU. Otherwise the BDLC wil not correctly receive the byte that woke it up. If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC internal operating clocks to restart and stabilize before normal communications can resume. Therefore, the BDLC is not guaranteed to receive that message correctly. NOTE: It is important to ensure that all transmissions are complete or aborted prior to putting the BDLC into stop mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Byte Data Link Controller-Digital General Release Specification MC68HC05V12 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D)

14.9.3 BDLC Wait Mode

This power-conserving mode is entered automatically from run mode whenever the CPU executes a WAIT instruction and the WCM bit in the BCR register is previously clear. A subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the BDLC to wake up and generate a CPU interrupt request if the interrupt enable (IE) bit in the BCR register is previously set. This results in saving less power, but the BDLCis guaranteed to correctly receive the message which woke it up, since the BDLC internal operating clocks are kept running. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 15. Gauge Drivers

15.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.2 Introduction

The MC68HC05V12 contains on-chip circuitry to drive six cross coil air core gauges. Four of the gauge drivers are 3-pin drivers intended for 180° gauges (minor gauges) and two of the drivers are full 4-pin H- bridge drivers for 360° gauges (major gauges). The output drivers for both major and minor gauges operate in a current drive mode. That is, the current in the gauge coils is controlled rather than the voltage across the coil. The maximum amount of current that can be driven into any coil is set by the value of the resistance between the Imax and VSSA pins. The current driven into each coil is set by writing a hex value to the current magnitude registers and the direction of current is selected by setting or clearing the appropriate bits in the current direction registers. The ratio of the current used to set the gauge deflection angle is software configured. No particular drive technique is implemented in hardware.

15.3 Gauge System Overview

The circuitry contained within the MC68HC05V12 provides a great deal of flexibility for driving the coils. The user specifies coil currents rather than degrees of deflection. This allows the software to drive the coil currents in a variety of ways. The user must specify the magnitude of the current as well as the direction it should flow for full H-bridge drivers. Half H-bridge drivers require specification of a magnitude only. Eight full H- bridge drivers and four half H-bridge drivers support two 360° and four 180° gauges. Figure 15-1 is a block diagram of the gauge driver module within the MC68HC05V12. Each of the blocks requiring more description is described in the following subsections. There are 20 coil driver pins on the MC68HC05V12. These are grouped into two types. The pins whose names start with MAJ are full H-bridge coil drivers. A or B in the pin name indicates major gauge A or B. A 1 or 2 in the name refers to coil 1 or coil 2 within the same gauge. It is important to keep coils within the same gauge connected to the same A or B coil driver pins. The + or− in the pin name indicates the direction of current flow according to this convention: The current direction positive Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED current means current flow is out of the pin with the + in its name and into the pin with− in its name. Negative current means current is flowing into the pin with the + in its name and out of the pin with− in its name. Figure 15-1. Gauge Driver Block Diagram CPU BUS 8-BIT D/A

12 CURRENT

6 CURRENT

MAJA2− MAJA1+ MAJA1− MAJOR DRIVE A S&H COIL 1 12-TO-1 8-BITMUX 8 * 12 MAJB2+ MAJB2− MAJB1+ MAJB1− MAJOR DRIVE B MINA2+ MINA2− MINA1 MINOR DRIVE A MIND2+ MIND2− MIND1 COIL SEQUENCER AND CONTROL REGISTER SAMPLE AND HOLD MUX AND CURRENT SENSE MUX COIL DRIVERS MUX CONTROL I to V CONVERTER IMAX RMAX 1% Vref MINOR DRIVE D D/A AMP _ S&H COIL 2 S&H COIL 1 S&H COIL 2 S&H COIL 1 S&H COIL 2 S&H COIL 1 S&H COIL 2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.4 Coil Drivers

To support both 180° and 360° gauges and to keep the pin count as low as possible, it is necessary to use two different types of coil drivers. These are the full H-bridge drivers and the half H-bridge drivers. Major gauges will require two of the full H-bridge drivers and the minor gauges will require one full H-bridge driver and one half H-bridge driver. A full H- bridge driver uses two pins and is capable of driving a controlled current in either direction in a single coil. A half H-bridge driver uses only one pin and can sink a controlled amount of current in one direction only. The amount of current flowing through the coils and its direction in the case of the full H-bridge driver are controlled through the current magnitude registers (CMR) and the current direction registers (CDR) described here. All of the components shown inFigure 15-2 andFigure 15-3 are internal components except for the gauge coils. The resistive and inductive properties of the external coils are expected to fall within the ranges of Rcoil and Lcoil shown inSection 17. Electrical Specifications. The resistance is important for calculating minimum operating voltages and power dissipation (see15.12 External Component Considerations), and the inductance is important in determining settling time (a part of tgcs) and controlling the rate of change of the current driven in the coils. For consistency, note that the dot on the coil is always connected to the + pin in the coil driver, or, in the case of the half H-bridge driver, it is connected to the positive supply pin. The internal resistor RI is used to measure how much current is flowing in the coil. The op-amp shown in this diagram is actually built only once and is shared among all 12 coil drivers through a multiplexer to reduce manufacturing variability among drivers. To determine what voltage must come from the D/A output, the maximum current level set by the external RMAX resistor is converted to a reference voltage input to the D/A. This reference voltage sets the maximum output voltage of the D/A (with an input of $FF). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.5 Technical Note

An auto-zeroing scheme is implemented in the MC68HC705V12 to reduce errors internal to the chip. Prior to each coil update, during the auto-zero phase, the amplifier output is disconnected from all FET gates (seeFigure 15-2) while the input is connected to it’s new input voltage. On completion of the auto-zero cycle, the amplifier output is connected to the appropriate FET gate. Since the FET gate and amplifier output are typically not at the same potential, the FET gate is momentarily pulled down, until the amplifier control loop re-establishes the correct gate potential. This abrupt change in gate potential results in voltage spikes, and thus current spikes in the gauge coil. The magnitude, duration, and number of spikes are dependent on the coil resistance, gauge supply voltage (VGSUP ), and the coil current prior to the auto-zero cycle (Figure 15-4). Only the worst case spike durations, under the specified test conditions, are shown. Typically the spike duration and total spike duration is smaller. NOTE: Due to the positive and negative spikes, there is negligible D.C. error introduced. Figure 15-4. Specification for Current Spikes t1 t2 tMAX I0 = Current before spikes I1 = Maximum spike magnitude =( VGSUP + 0.9 V)/Rcoil t1 = Maximum negative spike duration = 300 µs t2 = Maximum positive spike duration = 200 µs tMAX = Maximum duration of all spikes = 500 µs Conditions: VGSUP = 8.00 V Lcoil= 30 mH R coil = 200 W (typical) TA = 27°C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Gauge Driver Control Registers MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.6 Gauge Driver Control Registers

The gauge driver module requires the use of four types of control registers:

• The gauge enable register enables or disables individual gauges.
• The current magnitude registers set the amount of current to flow in a particular coil.
• The current direction register determines which direction the current will flow in a coil.
• The scan control register controls how the 12 coil drivers will be sequenced and updated by the analog multiplexers and control logic. Each register is described in more detail in the following sections.

15.6.1 Gauge Enable Register

All bits in this register are used to select which of the six gauges will be driven when the gauge module is active. If any bit of bits 7-2 is set, the gauge module will become active. When all bits are cleared, the gauge module is considered off. As much circuitry as possible is shut off to conserve power. The D/A, the coil sequencing logic, and the coil current measurement circuits are turned off. All high-side drivers in the H-bridge drivers are left on to absorb any transient current that may be generated when the drivers are initially turned on or off; all low-side drivers are high-Z. The effects of these bits on the scanning sequence of the gauges are described in15.7 Coil Sequencer and Control Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers MJAON — Major Gauge A On Bit This bit controls whether major gauge A is on or off. 1 = Gauge is on. 0 = Gauge is off. MJBON — Major Gauge B On Bit This bit controls whether major gauge B is on or off. 1 = Gauge is on. 0 = Gauge is off. MIAON — Minor Gauge A On Bit This bit controls whether minor gauge A is on or off. 1 = Gauge is on. 0 = Gauge is off. MIBON — Minor Gauge B On Bit This bit controls whether minor gauge B is on or off. 1 = Gauge is on. 0 = Gauge is off. MICON — Minor Gauge C On Bit This bit controls whether minor gauge C is on or off. 1 = Gauge is on. 0 = Gauge is off. MIDON — Minor Gauge D On Bit This bit controls whether minor gauge D is on or off. 1 = Gauge is on. 0 = Gauge is off. $20 Bit 7 654321 Bit 0 Read: MJAON MJBON MIAON MIBON MICON MIDON CMPS R Write: Reset: 00000000 R = Reserved Figure 15-5. Gauge Enable Register (GER) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Gauge Driver Control Registers MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED CMPS — Feedback Compensation Select This bit is provided to enable the user to select between one of two gauge driver feedback paths, depending upon the characteristics of the load. 1 = Alternate feedback circuit 0 = Default feedback circuit

15.6.2 Current Magnitude Registers

Addr. Register Read/ Write Bit 7 6 5 4 3 2 1 Bit 0 $22 Magnitude Register - MAJA1 R B7 B6 B5 B4 B3 B2 B1 B0W $23 Magnitude Register - MAJA2 R B7 B6 B5 B4 B3 B2 B1 B0W $24 Magnitude Register - MAJB1 R B7 B6 B5 B4 B3 B2 B1 B0W $25 Magnitude Register - MAJB2 R B7 B6 B5 B4 B3 B2 B1 B0W $26 Magnitude Register - MINA1 R B7 B6 B5 B4 B3 B2 B1 B0W $27 Magnitude Register - MINA2 R B7 B6 B5 B4 B3 B2 B1 B0W $28 Magnitude Register - MINB1 R B7 B6 B5 B4 B3 B2 B1 B0W $29 Magnitude Register - MINB2 R B7 B6 B5 B4 B3 B2 B1 B0W $2A Magnitude Register - MINC1 R B7 B6 B5 B4 B3 B2 B1 B0W $2B Magnitude Register - MINC2 R B7 B6 B5 B4 B3 B2 B1 B0W $2C Magnitude Register - MIND1 R B7 B6 B5 B4 B3 B2 B1 B0W $2D Magnitude Register - MIND2 R B7 B6 B5 B4 B3 B2 B1 B0W Figure 15-6. Current Magnitude Registers Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers The naming convention used in the CMRs above indicates whether it is a major or minor gauge driver, which major or minor gauge (A, B, C, etc.), and which coil within the gauge is affected (coil 1 or coil 2). Each of the magnitude registers is double buffered to keep both coil currents within the same gauge as closely coupled as possible. Transfer of data from the master to the slave buffers in these registers is under control of the coil sequencer and control logic and is described in15.7 Coil Sequencer and Control. A read of any of the CMRs will return only the contents of the slave buffer. If a read of one of the CMRs takes place after a write of data but before the master-to-slave transfer takes place, the data read may be different from the data written. The master register will always hold the contents of the last write. Reset clears all bits. The 8-bit value written to these registers will determine the amount of current that will flow in each of the 12 coils. For example, MAJA1 controls the magnitude of the current between the MAJA1+ and MAJA1− pins. The theoretical current that will flow between the + and− pins is given by this equation: ICM is the maximum current that can be driven into any of the coil drivers and is given by this equation: ICM = (IMAX x 10) x (1 + ECA + EMAX ) ECA is the total internal error in generating ICM from IMAX and is shown in17.11 Gauge Driver Electricals. The EMAX is the error tolerance of the RMAX resistor and is shown in 17.11 Gauge Driver Electricals. The “reg value” is the base 10 representation of the value written to the magnitude registers. IMAX is set by the external resistor and is a reference current that is used to generate the coil currents. IMAX is related to the external RMAX resistor by the equation: I ICM() X reg value = IMAX 2.5  X4= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Gauge Driver Control Registers MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.6.3 Current Direction Registers

The bits in these registers control the direction of current flow in each of the full eight H-bridge drive outputs. Note that only coil 2 in the minor gauges requires a direction bit. Since coil 1 in each of the minor gauges is a half H-bridge driver, it only requires a current magnitude register. The CDR also contains a master and slave latch. A read of any of these registers will return the value in the slave buffer.

15.6.3.1 Current Direction Register for Major A

DMJA1 and DMJA2 — Current Direction Bits for Major Gauge A 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver. $2E Bit 7 654321 Bit 0 Read: RRRRR0 DMJA1 DMJA2 Write: Reset: 00000000 R = Reserved Figure 15-7. MAJA Current Direction Register (DMAJA) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.6.3.2 Current Direction Register for Major B

DMJB1 and DMJB2 — Current Direction Bits for Major Gauge B 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver.

15.6.3.3 Current Direction Register for Minor A

DMIA — Current Direction Bit for Minor Gauge A 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver. $2F Bit 7 654321 Bit 0 Read:

000000 DMJB1 DMJB2

Write: Reset: 00000000 Figure 15-8. MAJB Current Direction Register (DMAJB) $30 Bit 7 654321 Bit 0 Read:

0000000 DMIA

Write: Reset: 00000000 Figure 15-9. MINA Current Direction Register (DMINA) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Gauge Driver Control Registers MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.6.3.4 Current Direction Register for Minor B

DMIB — Current Direction Bit for Minor Gauge B 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver.

15.6.3.5 Current Direction Register for Minor C

DMIC — Current Direction Bit for Minor Gauge C 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver. $31 Bit 7 654321 Bit 0 Read:

0000000 DMIB

Write: Reset: 00000000 Figure 15-10. MINB Current Direction Register (DMINB) $32 Bit 7 654321 Bit 0 Read:

0000000 DMIC

Write: Reset: 00000000 Figure 15-11. MINC Current Direction Register (DMINC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.6.3.6 Current Direction Register for Minor D

DMID — Current Direction Bit for Minor Gauge D 1 = Current flow will be from the – pin to the + pin on the corresponding coil driver. 0 = Current flow will be from the + pin to the – pin on the corresponding coil driver.

15.7 Coil Sequencer and Control

As shown inFigure 15-1 the digital/analog converter is shared among all 12 coils. The sequence in which the coils are scanned and the events that take place during the scanning process are described in this section. The scan control and status register in15.7.2 Scan Status and Control Register controls how the coil sequencer will operate. This register contains control bits that affect how the gauge sequencer will scan through the six gauges as well as a status bit to indicate where the scanning sequencer is in the scanning operation.

15.7.1 Scanning Sequence Description

The coil sequencer can be operated in two basic modes: automatic or manual. In either mode, each coil is updated by the D/A, muxes, and sample and hold circuits in the sequence shown inFigure 15-1. One time through the coil sequence is referred to as a scan cycle. It takes a time, tgcs,to update each coil during the scanning sequence. Since there are 12 coils in the six gauge drivers, it will take a time, 12*tgcs, to complete one scan cycle. The differences between the automatic and manual modes are as follows. $33 Bit 7 654321 Bit 0 Read:

0000000 DMID

Write: Reset: 00000000 Figure 15-12. MIND Current Direction Register (DMIND) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Coil Sequencer and Control MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.7.1.1 Automatic Mode

Once all of the coils have been updated, the sequence repeats automatically. The transfer of data in the CMR and CDRs master-to- slave buffers is performed at the beginning of each gauge update time. When one of the coil registers associated with a gauge is written, the second register also must be written before either value will be used. The coil registers may be written in either order. For example, if the MIND1 register is written with any value, then the MIND2 register must also be written. Otherwise, minor gauge D will not be updated on subsequent scans and the currents driven into the coils will maintain their previously programmed values. This sequence must be followed even if the data written to one magnitude register is not different from the data already in the register. The hardware works off the write operation to the registers, not off the data written. Before the master-to-slave transfer takes place in the CDRs, each coil in a particular gauge must be updated. Because writes to the CMRs are the only requirement for transferring master to slave of the CDRs, the CDRs should be written before the CMRs are written.

15.7.1.2 Manual Mode

The user must set the SCNS bit in the scan status and control register (SSCR) to initiate a scan cycle. Once a single scan cycle takes place, the coil sequencer stops and waits for the SCNS bit to be set again before starting another scan cycle. The SCNS bit must be set at a fast enough rate (the scan period) to prevent the sample and hold circuits from drooping and introducing error and current fluctuations into the output currents. This minimum time is called the minimum scan period, tmsn (see17.11 Gauge Driver Electricals). The transfer of data from the CMR and CDRs master-to-slave buffers is performed at the beginning of each gauge update time even if all CMRs and CDRs were not updated. If any of the gauges are turned off by clearing the appropriate bits in the gauge enable register (GER), the time the coil sequencer would have spent updating the coils in the disabled gauge is still expended, but the Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers coil driver remains off. This provides for a consistent scan rate regardless of the number of gauges that are enabled. The scanning sequence for the coils is shown inTable 15-1. It takes a time, tgcs, to update each coil. This includes time to move the data from the CMR and CDR (automatic mode), perform the digital/analog conversion, update the sample and hold circuit at the coil driver, and wait for all transient currents to settle for each coil. Because several CPU write operations may be necessary to write to the CMRs and CDRs, all of the CMRs and the CDRs contain a master and a slave buffer to help prevent unwanted fluctuations in coil currents between the writes to the three registers on a given gauge. Only the slave buffers will affect the coil currents and direction. Table 15-1. Coil Scanning Sequencer Coil Number Coil Name Gauge Name

1 MAJA1 Major A

2 MAJA2 Major A

3 MAJB1 Major B

4 MAJB2 Major B

5 MINA1 Minor A

6 MINA2 Minor A

7 MINB1 Minor B

8 MINB2 Minor B

9 MINC1 Minor C

10 MINC2 Minor C

11 MIND1 Minor D

12 MIND2 Minor D

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Coil Sequencer and Control MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED For coil currents to remain as consistent as possible during the scanning and updating of the gauge coil currents, the sample and hold update operation must take place in a particular way. The control logic will perform this function. When the scanning control logic is ready to advance to the next coil, this operations sequence must take place: 1. Open all sample and hold switches. 2. Increment pointer to next CMR slave register. If both CMRs for this gauge have been written, transfer new master data to slave buffer for this CMR and corresponding CDR. If both CMRs have not been written, don’t transfer data from master to slave. 3. Move slave buffer data to the D/A input. 4. Wait for the D/A output to muxes. 5. Close sample and hold mux and update direction control from CDR. 6. Wait for sample and hold to settle. 7. Go back to step 1 above.

15.7.2 Scan Status and Control Register

Although the CDR and CMRs can be written at any time, the user may want to write the CDR and CMRs at a particular time in the scanning sequence. Some of the bits in the SSCR give the user the information need to synchronize the writes to the CDR and CMRs with the coil sequencer. In addition to the sychronization bits, this register also contains a bit that affects the type of scanning that will take place (automatic or manual) and a bit to initiate a scan cycle manually when using manual mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers SYNIE — Synchronize Interrupt Enable Bit When this bit is set, an interrupt signal will be sent to the CPU when the SYNF bit is set. The I bit in the CPU condition code register must be cleared in order for the interrupt to be recognized by the CPU. The interrupt vector assigned to the gauge module is shown in Table 15-2. 1 = Interrupt is enabled. 0 = Interrupt is disabled. SYNF — Synchronize Flag Bit This bit is a read-only status bit and indicates that the coil sequencer has begun to service coil 11 (minor D). At this point in the scanning cycle, it is safe to write any of the CMRs or CDRs without affecting the current scan cycle. Any time this bit is set and the SYNIE bit is set, a CPU interrupt will be generated. The bit will be set even if minor D is not enabled in the GER, since the scanning sequence time is not affected by the enabling or disabling of the gauges. This bit will function in either auto or manual mode and does not affect the scanning operation in any way. It serves only as a status flag. Note that once this bit is set, the software will have a time, 2*tgcs,to update the CDR and CMR register if new data is to be used in the next scan cycle. The bit is cleared by writing a 1 to the SYNR bit and by reset. SYNR — Synchronize Flag Reset Bit This bit is used to clear the SYNF bit. Writing a 1 to this bit will clear the SYNF bit if the SYNF bit was set during a read of the SSCR. This bit will always read 0. $21 Bit 7 654321 Bit 0 Read: SYNIE SYNF 0 R GCS1 GCS0 SCNS AUTOS Write: SYNR Reset: 00000000 = Unimplemented R = Reserved Figure 15-13. Scan Status and Control Register (SSCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Coil Sequencer and Control MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED GCS1–GCS0 — Gauge Clock Select Bits These bits determine the clock divide ratio for the clock used by the scan sequencer. This provides for the use of several different system clock rates while still providing the gauge driver module with the same scanning rate. SCNS — Scan Start Bit When the coil sequencer is being operated in manual mode, this bit is used to initiate a scan cycle. Setting this bit starts the scan cycle. All CMRs and CDRs will transfer data from the master to the slave when this bit is set. This bit clears automatically once the scan cycle begins to service coil 11 (minor D). The bit will clear at the proper time, even if the minor D gauge is not enabled in the GER, since the scan cycle time is not affected by the enabling or disabling of the gauges. The bit is cleared once coil 11 begins to be serviced because adequate time (2 * tgcs) for the software (either interrupt driven or polled) to recognize the flag and write new data to the CDR and CMR registers for the next scan cycle should be provided. Note that after the scan cycle has finished, a new scan cycle will not begin until this bit is set again. If a 1 is written to this bit before it clears, the write will be ignored. In automatic mode, this bit has no effect. Table 15-2. Gauge Module Clock Select Bits CPU Bus Clock Frequency GCS1 GCS0 Division Scan Cycle Time fop = 0.5 MHz 0 0 512 t gcs fop = 1.0 MHz 0 1 1024 t gcs fop = 2.0 MHz 1 0 2048 t gcs fop = 4.0 MHz (see Note) 1 1 4096 t gcs NOTE: Must not be selected Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers AUTOS — Automatic Mode Select Bit This bit selects whether the coil sequencer will operate in manual or automatic mode. 1 = Automatic mode 0 = Manual mode

15.8 Mechanism Diagram

The diagram inFigure 15-15 shows one way the gauge coils could be connected to the coil driver pins and how some of the other pins should be connected. The external components that have actual part numbers are merely examples of suitable components. Other components with similar operating characteristics also may be used.

15.9 Gauge Power Supply

The MC68HC05V12 contains most of the circuitry to provide the coil drivers with a regulated supply that is necessary to drive the coil. Referring toFigure 15-3, the gauge drive voltage, VGSUP , is derived with the aid of an external P-channel enhancement mode MOSFET device which serves as the series pass devices between a +12 V supply and the VGSUP pin. Two external resistors also are used to set the level of VGSUP. The drive to the gate of the external pass devices will be whatever is required to produce a VGVREF voltage of 2.5. The value of resistors Rg1 and Rg2 should be chosen so that VGSUP * [Rg2/(Rg1+R g2)] = 2.5 NOTE: The VGSUP pin requires a 100µF low ESR capacitor for regulator stability. In addition, the VDD and VCCA pins should have the usual 0.1 µF bypass capacitors to VSS and VSSA respectively. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED Figure 15-14. Sample Gauge Connections to the MC68HC05V12 VBATT EXTERNAL REGULATOR +5 VOLTS +/-5% 0.1 m IMAX RMAX VDD VCCA VSS VSSA 68HC05V12 VSSG VSS 0.1 m VGSUP VPGC VGVREF MINA1 MINA2+ MINA2− MINOR GAUGE A MAJA1+ MAJA1− MAJA2+ MAJA2− MAJOR GAUGE A MAJB1+ MAJB1− MAJB2+ MAJB2− MAJOR GAUGE B MINOR GAUGE B MINOR GAUGE C MINOR GAUGE D MINB1 MINB2+ MINB2− MINC1 MINC2+ MINC2− MIND1 MIND2+ MIND2− Rg1 Rg2 100 mF CIRCUITRY 0.1 mF 0.1 m VDD ~8 V 0.1 mF *100K5% LOW ESR MTP2955 RECOMMENDED 0.1 mF P6KE15A P6KE30A 1N5822 REVERSE BATTERY AND TRANSIENT PROTECTION RECOMMENDED VALUES Rg1 − 55 k Rg2 −25 k *R = PMOS VT(NOM)/50 x 10 –6 NOTE: PASS DEVICE AND RELATED COMPONENTS SHOULD BE AS PHYSICALLY CLOSE TO THE MCU AS POSSIBLE. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers To provide effective decoupling and to reduce radiated RF emissions, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness and could increase radiated RF emissions from the system. A low-value capacitor (470 pF to 0.01µF) placed in parallel with the other capacitors will improve the bandwidth and effectiveness of the network.

15.10 Gauge Regulator Accuracy

The on-chip portion of the regulator will contribute no more than Egs % to the variation in the VGSUP voltage. The remaining errors will come from the tolerances in the RG1 and RG2 resistors off-chip.

15.11 Coil Current Accuracy

The accuracy of the current flowing between the + and – coil pins of a particular coil driver pin pair is described here. Matching of currents between coils within the same gauge is specified in 17.11 Gauge Driver Electricals as ECM . The absolute accuracy of the coil current that can be driven into any coil is determined by the accuracy of ICM given by the equations in15.10 Gauge Regulator Accuracy and will be a total of (ECA + EMAX ). Because the D/A amp is shared among all coil drivers and between both sets of drivers in the full H-bridge drivers, there will be no difference in the magnitude of the current when the magnitude register value remains constant and only the polarity bit is changed in a coil driver. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

External Component Considerations MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.12 External Component Considerations

To determine the values and tolerances of the external components required to drive the air core gauge coils, the minimum VBATT voltage, at the V12 pin, and the power dissipation should be considered. Figure 15-15 shows the components in the path between the +12 V coming in through the external devices the internal devices and into VSSG . Figure 15-15. Coil Driver Current Path 1N5822 GAUGE COILS RI VSSG PAD +12 V VGSUP COIL DRIVER PAD COIL DRIVER PAD Rcoil Lcoil Vdiode Vpass PIN ON PACKAGE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers

15.12.1 Minimum Voltage Operation

To maintain accuracy to as low a VBATT voltage as possible, the following equations should be used to calculate the range of values for the external components. VBATT(min) = VGSUP(max) + VDIODE + VPASS VPASS is the drop across the external P-channel MOSFET at SF * 12 * ICOIL(max) SF = % of max current driven by all coil drivers in application. Worst case 0.707 (45o) assumes SIN/COS drive algorithm. VDIODE = Drop across reverse battery protection diode at 12 * ICOIL(max) To solve the above equation, the factors involved in generating the gauge supply voltage, VGSUP , must first be calculated due to both internal tolerances and the tolerances of external resistors RG1 and RG2 , VGSUP = VGSUP(nom) x (1± TOL ) VGSUP(nom) is the VGSUP voltage generated with all tolerances set to 0%. TOL = Egs + TOL(RG1) + TOL(RG2) and includes temperature effects. R G1 and RG2 are the external resistors used to set the VGSUP voltage. The internal tolerances are Egs. The minimum VGSUP voltage required for proper operation is given by, ICOIL(max) x [RCOIL(max) + RSI(max)] where

• R SI is the total of the internal resistances from the transistors and sense resistor and is found in the electrical specifications.
• I COIL is the minimum required coil current.
• R COIL is the minimum coil resistance including temperature effects. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

External Component Considerations MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED The minimum required VGSUP must agree with the minimum generated VGSUP of, VGSUP(min) = VGSUP(nom) x (1-TOL ) equating the two VGSUP(nom) x (1-TOL ) = ICOIL(max) x [ RCOIL(max) + RSI(max)]

15.12.2 Power Dissipation

To keep the junction temperature to a minimum, the power consumed by the gauge drivers must be factored into the chip power dissipation equation. The total chip power dissipation combined with the thermal resistance of the package cannot exceed the maximum junction temperature, TJ. The total chip power dissipation is given by this equation: PD = PGAUGE + PCHIP PCHIP is the power contribution by all chip modules that are connected to the VDD and VDDA sources including part of the gauge module. To calculate PCHIP , use this equation: PCHIP = (IDD xVDD ) + (ICCA x VCCA ) VGSUP nom() ICOIL max() X RCOIL max() RSI max()+[] Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers The power dissipation contributed by the gauge module is given by this equation. PGAUGE = [VGSUP(max) X IGSUP ] + PGDRIVERS where PGDRIVERS = [(VGSUP(max) x ICOIL(max)) – (ICOIL(max) 2 x RCOIL(min))] x 12 x SF where

• I GSUP = the current consumed by the gauge module from the VGSUP pin for functions other than generating coil currents.
• 12 is the number of coil drivers
• SF = % of max current driven in any coil; worse case for power dissipation purposes, 0.707 (45o) assumes SIN/COS drive algorithm
• I COIL(max) = maximum required coil current in each coil

15.12.3 Coil Inductance Limits

Since the MCU pins will drive the gauge coils directly without any external voltage limiting devices, precautions must be taken to avoid generating voltages and currents high enough to damage the MCU. The high voltages generated by the inductive impedance of the coil will be related directly to the coil drivers. This imposes a limit on the maximum coil inductance referred to as Lcoil in the electrical specifications.

15.13 Operation in Wait Mode

During wait mode, the gauge driver module will continue to operate normally. The gauges will continue to be driven to the currents and directions that were last written to the CMR and CDR. In manual mode, if the CPU will be put into wait mode between scan cycles, the SYNIE bit in the SSCR should be set to enable the gauge module to generate an interrupt request (which will take the CPU out of wait mode) to properly service the gauge coils. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Gauge Drivers NON-DISCLOSURE AGREEMENT REQUIRED

15.14 Operation in Stop Mode

During stop mode, the system clocks will stop operating. All bits in the GER register will be cleared automatically when stop mode is entered. No other bits in any other gauge module registers will be affected. The gauge controller sequence and control logic will be reset/initialized such that a new scan sequence will begin once the gauges are turned on during the user’s stop mode recovery sequence. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Gauge Drivers General Release Specification MC68HC05V12 — Rev. 1.0 Gauge Drivers Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 16. Instruction Set

16.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.2 Introduction

The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.

16.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED

16.3.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.

16.3.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

16.3.3 Direct

Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.

16.3.4 Extended

Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

16.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.

16.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED

16.3.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

16.4 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 16-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED

16.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence be- cause it does not write a replacement value. Table 16-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left (Same as LSL) ASL Arithmetic Shift Right ASR Bit Clear BCLR (1) Bit Set BSET (1) Clear Register CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left (Same as ASL) LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST (2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED Table 16-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch ifIRQ Pin High BIH Branch ifIRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 16-4. Bit Manipulation Instructions Instruction Mnemonic Bit Clear BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Bit Set BSET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED

16.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation during program execution. Table 16-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and EnableIRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable InterruptsWAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set

16.5 Instruction Set Summary

Table 16-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ← (A) + (M) ↕×— ↕× ↕↕ IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left (Same as LSL) — — ↕× ↕↕ DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ↕× ↕↕ DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 +rel ? C = 0 — — — — — REL 24 rr 3 BCLR n opr Clear Bit n Mn ← 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +rel ? C = 1 — — — — — REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 +rel ? Z = 1 — — — — — REL 27 rr 3 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 +rel ? H = 0 — — — — — REL 28 rr 3 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 +rel ? H = 1 — — — — — REL 29 rr 3 BHI rel Branch if Higher PC ← (PC) + 2 +rel ? C∨ Z = 0 — — — — — REL 22 rr 3 BHS rel Branch if Higher or Same PC ← (PC) + 2 +rel ? C = 0 — — — — — REL 24 rr 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED BIH rel Branch if IRQ Pin High PC ← (PC) + 2 +rel ? IRQ = 1 — — — — — REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 +rel ? IRQ = 0 — — — — — REL 2E rr 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte (A) ∧ (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 +rel ? C = 1 — — — — — REL 25 rr 3 BLS rel Branch if Lower orSame PC ← (PC) + 2 +rel ? C∨ Z = 1 — — — — — REL 23 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 +rel ? I = 0 — — — — — REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 +rel ? N = 1 — — — — — REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +rel ? I = 1 — — — — — REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 +rel ? Z = 0 — — — — — REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 +rel ? N = 0 — — — — — REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 +rel ? 1 = 1 — — — — — REL 20 rr 3 BRCLR n opr relBranch if Bit n Clear PC ← (PC) + 2 +rel ? Mn = 0 — — — — ↕× DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← (PC) + 2 +rel ? 1 = 0 — — — — — REL 21 rr 3 BRSET n opr relBranch if Bit n Set PC ← (PC) + 2 +rel ? Mn = 1 — — — — × ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BSET n opr Set Bit n Mn ← 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) +rel CLC Clear Carry Bit C ← 0 — — — — 0 INH 98 2 CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2 Table 16-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte (A) – (M) — — ↕× ↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (A) X ← (X) = $FF – (X) M ← (M) = $FF – (M) M ← (M) = $FF – (M) DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte (X) – (M) — — ↕××↕ ×↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff INC opr INCA INCX INC opr,X INC ,X Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ← Jump Address — — — — — DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff Table 16-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP← (SP) – 1 Push (PCH); SP← (SP) – 1 PC ← Effective Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ← (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ← (M) — — ↕× ↕×— IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left (Same as ASL) — — ↕× ↕↕ DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 ↕↕ DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ← (X)× (A) 0 — — — 0 INH 42 1 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX dd ff NOP No Operation — — — — — INH 9D 2 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory A ← (A)∨ (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit — — ↕× ↕↕ DIR INH INH IX1 IX dd ff Table 16-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 C b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit — — ↕× ↕↕ DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ← $00FF — — — — — INH 9C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)— — — — — INH 81 6 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ← 1 — — — — 1 INH 99 2 SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory M ← (A) — — ↕× ↕ — DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ← (X) — — ↕× ↕ — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator A ← (A) – (M) — — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte — 1 — — — INH 83 1 TAX Transfer Accumulator to Index Register X ← (A) — — — — — INH 97 2 Table 16-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Instruction Set NON-DISCLOSURE AGREEMENT REQUIRED TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 — — ↕↕ — DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator A ← (X) — — — — — INH 9F 2 WAIT Stop CPU Clock and Enable Interrupts — 0× — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected Table 16-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIREDGeneral Release Specification MC68HC05V12 — Rev. 1.0 Instruction Set Instruction SetTable 16-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

0123456789 ABCDEF

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 17. Electrical Specifications

17.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.2 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS ≤ (VIN or VOUT )≤ VDD . Connect unused inputs to the appropriate voltage level, either VSS or VDD . NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to17.6 DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol Value Unit Supply Voltage VPGC, VGSUP , and VGREF VDD VCCA –0.5 to +42.0 –0.5 to +7.0 VDD V Input Voltage V IN VSS –0.3 to VDD +0.3 V Current Drain Per Pin (I/O) Current Drain Per Pin (Gauge) I 25 50 mA Storage Temperature Range T stg –65 to +150 °C Write/Erase Cycles (@ 10 ms write time and –40°C, +25 °C, and +85°C) — 10,000 Cycles Data Retention EEPROM (–40°C, to + 85°C) — 10 Y ears Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

Operating Temperature Range MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED

17.3 Operating Temperature Range

17.4 Thermal Characteristics

Characteristic Symbol Value Unit Operating Temperature Range Standard Extended TA TL to TH 0 to +70 –40 to +85 Maximum Junction Temperature T J 150 °C Characteristic Symbol Value Unit Thermal Resistance PLCC (68 Pin) θJA 50 °C/W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.5 Power Considerations

The average chip junction temperature, TJ, in°C can be obtained from: (1) where: TA = ambient temperature in°C θJA = package thermal resistance, junction to ambient in °C/W PD = PINT + PI/O PINT = ICC × VCC = chip internal power dissipation PI/O = power dissipation on input and output pins (user-determined) For most applications, PI/O PINT and can be neglected. Ignoring PI/O , the relationship between PD and TJ is approximately: (2) Solving equations (1) and (2) for K gives: (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. TJ TA P D θ× JA()+= P D K PD TA 273 °C+() θ JA PD() 2×+×= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED

17.6 DC Electrical Characteristics

Characteristic Symbol Min Max Unit Output Voltage ILOAD = 10.0 µA ILOAD =−10.0µA VOL VOH VDD − 0.1 0.1 V Output High Voltage (ILOAD −0.8 mA) Port A, Port B, Port C, TXP VOH VDD − 0.8 — V Output Low Voltage (ILOAD = 1.6 mA) Port A, Port B, Port C, TXP VOL — 0.4 V Input High Voltage Port A, Port B, Port C Port D,IRQ,RESET, OSC1, RXP VIH 0 . 7xVDD VDD V Input Low Voltage Port A, Port B, Port C, Port D,IRQ,RESET, OSC1, RXP VIL VSS 0.3 x VDD V Supply Current (see Notes) Run Wait SPI, TIMER, A/D, PWM, COP , LVR On Wait Above Modules Off Stop LVR Enabled LVR Disabled IDD 300 200 mA mA mA µA µA I/O Ports Hi-Z Leakage Current Port A, Port B, Port C IOZ —1 µA Input Current RESET, IRQ, OSC1, PD0-PD4 IIN —1 µA Capacitance (see Note 9) Ports (as Input or Output) RESET, IRQ C OUT C INT pF Low-Voltage Reset Inhibit V LVRI 3.5 4.2 V Low-Voltage Reset Recover V LVRR 3.6 4.5 V Low-Voltage Reset Inhibit/Recover Hysteresis H LVR 0.1 0.3 V VDD Slew Rate Rising (see Note 9) S VDDR — 0.1 V/ µs VDD Slew Rate Falling (see Note 9) S VDDF — 0.05 V/ µs NOTES: 1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85 °°C, unless otherwise noted. 2. All values shown reflect average measurements. 3. Run (Operating) IDD , wait IDD : Measured using external square wave clock source to OSC1 (fOSC = 4.2 MHz), all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 4. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 5. Stop IDD measured with OSC1 = VSS . 6. Wait IDD is affected linearly by the OSC2 capacitance. 7. Total 8. All coil drivers are set to the maximum current in automatic mode with no loading on the gauge pins. 9. Not Tested Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.7 Control Timing

Characteristic Symbol Min Max Unit Frequency of Operation Crystal Oscillator Option External Clock Source fOSC fOSC 0.1 dc 4.2 4.2 MHz Internal Operating Frequency Crystal (fOSC /2) External Clock (fOSC /2) fOP fOP dc 2.1 2.1 MHz Cycle Time (1/fOP ) tCYC 476 — ns Crystal Oscillator Startup Time (Crystal Oscillator Option)tOXON — 100 ms Stop Recovery Startup Time (Crystal Oscillator Option) tILCH — 100 ms RESET Pulse Width Low (SeeFigure 5-2) tRL 120 — ns Interrupt Pulse Width Low (Edge-Triggered) tILIH 120 — ns Interrupt Pulse Period tILIL See Note 3 — t CYC Port C Interrupt Pulse Width High (Edge-Triggered) tILHI 120 — ns Port C Interrupt Pulse Period tIHIH See Note 3 — t CYC OSC1 Pulse Width tOSC1 90 — ns EEPROM Programming Time per Byte tEEPGM 10 — ms EEPROM Erase Time per Byte tEBYT 10 — ms EEPROM Erase Time per Block tEBLOCK 10 — ms EEPROM Bulk Erase Time tEBULK 10 — ms EEPROM Programming Voltage Discharge Period tFPV — 10.0 µs RC Oscillator Stabilization Time tRCON —5 t CYC 16-Bit Timer Resolution (See Note 2) Input Capture Pulse Width Input Capture Period tRESL tTH , tTL tTLTL 4.0 See Note 4 tCYC ns tCYC NOTES: 1. V DD = 5.0 Vdc, VSS = 0 Vdc, TA = –40°C to +85 °°C, unless otherwise noted. 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC . 4. The minimum period, tTLTL, should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 tCYC . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED Figure 17-1. Stop Recovery Timing Diagram 3FFE 3FFE 3FFE 3FFE 3FFF 4 tRL tILIH OSC11 RESET IRQ2 IRQ3 INTERNAL CLOCK INTERNAL ADDRESS BUS tILCH 4064 tCYC NOTES: 1. Represents the internal gating of the OSC1 pin. 2. IRQ pin is edge-sensitive mask option. 3.IRQ pin is level- and edge-sensitive mask option. 4.RESET vector address is shown for timing example. RESET OR INTERRUPT VECTOR FETCH Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.8 A/D Converter Characteristics

Characteristic Min Max Unit Comments Resolution 8 8 Bits Absolute Accuracy (VREFL = 0.0 V, VREFH = VDD ) — +1 LSB Include quantization Conversion Range VREFH VREFL VREFL VREFL −0.1 VREFH VDD VREFH V V V A/D accuracy decreases proportionately as VREFH is reduced below VCCA min. (see Note 3) Power-Up Time — 100 µs Input Leakage PD0–PD4 VREFL , VREFH µA µA Conversion Time (Includes Sampling Time) 32 32 TAD (see Note 2) Monotonicity Inherent (Within Total Error) Zero Input Reading 00 01 Hex V IN = 0 V Full-Scale Reading FE FF Hex V IN = VREFH Sample Time 12 12 TAD (see Note 2) Input Capacitance — 8 pF Not Tested Analog Input Voltage V REFL VREFH V A/D On Current Stabilization Time (tADON ) — 100 µs RC Oscillator Stabilization Time (tRCON )— 5 µs NOTES: 1V CCA = 5.0±10% Vdc +10%, VSSA = 0.0 Vdc, TA =−40 °°C to +85 °°C, unless otherwise noted. 2. TAD = tCYC if clock source equals MCU. 3. Not Tested Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED

17.9 LVR Timing Diagram

Figure 17-2. LVR Timing Diagram tVDDF = VDD/SVDDF tVDDR = VDD/SVDDR VLVRI VLVRRVDD INTERNAL LVR RESET PIN Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.10 Serial Peripheral Interface (SPI) Timing

Num Characteristic Symbol Min Max Unit Operating Frequency Master Slave fOP(M ) fOP(S) dc dc 0.5 4.2 fOP MHz Cycle Time Master Slave tCYC(m) tCYC(s) 2.0 240 tCYC ns Enable Lead Time Master Slave tLEAD(M) lLEAD(S) see Note 2 240 ns ns Enable Lag Time Master Slave tLAG(m) tLAG(s) see Note 2 240 ns ns Clock (SCK) High Time Master Slave tw(SCKH)m tw(SCKH)s 340 190 ns ns Clock (SCK) Low Time Master Slave tw(SCKL)m tw(SCKL)s 340 190 ns ns Data Setup Time (Inputs) Master Slave tSU (m) tSU (s) 100 100 ns ns Data Hold Time (Inputs) Master Slave tH (m) tH (s) 100 100 ns ns

8 Access Time (Time to Data Active from High-Impedance State)

9 Disable Time (Hold Time to High-Impedance State)

Slave tDIS — 240 ns

10 Data Valid (After Enable Edge) (see Note 3) t V(s) — 240 ns

11 Data Hold Time (Output) (After Enable Edge) t HO 0— n s

Rise Time (20% VDD to 70% VDD , CL = 200 pF) SPI Outputs (SCK, MOSI, and MISO) SPI Inputs (SCK, MOSI, MISO, andSS) tRM tRS 100 2.0 ns µs Fall Time (20% VDD to 70% VDD , CL = 200 pF) SPI Outputs (SCK, MOSI, and MISO) SPI Inputs (SCK, MOSI, MISO, andSS) tFM tFS 100 2.0 ns µs NOTES: 1. V DD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications

17.11 Gauge Driver Electricals

Characteristic Symbol Min Max Unit Input Current on VGSUP with No Coil Current Input Current on VGSUP with Coil Current (see Note 3) Input Current on VGSUP in Stop Mode IGSUP 135 mA mA µA Maximum Reference Current I MAX 0.47 0.57 mA Internal Total Series Impedance R SI 20 60 Ω Manual Scan Cycle Period t MSN 12 * tGCS 20 ms Coil Inductance (see Note 4) L COIL —3 1 m H Coil Resistance (see Note 4) R COIL 140 270 Ω Error Tolerance of RMAX EMAX ±1% Coil Current Matching Error (as % of ICM )E CM 0 ±1% Coil Current Absolute Error E CA 0 ±9% Coil Current Update Time t GCS TBD 1.67 ms Coil Current Maximum I CM —2 3 m A Gauge Supply Regular Error E GS — ±5% Monotonicity See Note 5 Coil Current Step Size I Step (ICM /255) * 0.50 (ICM /255) * 1.50 mA NOTES: 1. V GSUP = 7.6 Vdc, TA =−40 °C to +85°C, unless otherwise noted. 2. Minimum/Maximum is dependent upon power calculation. 3. Assumes sin/cos 4. Coil is not on chip; values stated are indicative of the intended application. 5. Inherent within total error. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Electrical Specifications NON-DISCLOSURE AGREEMENT REQUIRED

17.12 BDLC Electricals

17.12.1 Transmitter VPW Symbol Timings

17.12.2 Receiver VPW Symbol Timings

NOTE: The receiver symbol timing boundaries are subject to an uncertainty of □1 tBDLC µs due to sampling considerations. Table 17-1. BDLC Transmitter VPW Symbol Timings (BARD Bits BO[3:0] = 0111) Characteristic Number Symbol Min Typ Max Unit Passive Logic 0 10 t TVP 1 62 64 66 µs Passive Logic 1 11 t TVP 2 126 128 130 µs Active Logic 0 12 t TVA 1 126 128 130 µs Active Logic 1 13 t TVA 2 62 64 66 µs Start of Frame (SOF) 14 t TVA 3 198 200 202 µs End of Data (EOD) 15 t TVP 3 198 200 202 µs End of Frame (EOF) 16 t TV 4 278 280 282 µs Inter-Frame Separator (IFS) 17 t TV 6 298 300 302 µs NOTE: fBDLC = 1.048576 MHz or 1.0 MHz Table 17-2. BDLC Receiver VPW Symbol Timings (BARD Bits BO[3:0] = 0111) Characteristic Number Symbol Min Typ Max Unit Passive Logic 0 10 t TRVP 1 34 64 96 µs Passive Logic 1 11 t TRVP 2 96 128 163 µs Active Logic 0 12 t TRVA 1 96 128 163 µs Active Logic 1 13 t TRVA 2 34 64 96 µs Start of Frame (SOF) 14 t TRVA 3 163 200 239 µs End of Data (EOD) 15 t TRVP 3 163 200 239 µs End of Frame (EOF) 16 t TRV 4 239 280 320 µs Break 18 t TRV 6 239 — — µs NOTE: fBDLC = 1.048576 MHz or 1.0 MHz Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Electrical Specifications Figure 17-5. BDLC Variable Pulse Width Modulation (VPW) Symbol Timings 13 11 10 12 SOF 0 0

11 EOD

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification Mechanical Specifications NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 18. Mechanical Specifications

18.1 Contents

18.2 Introduction

This section describes the dimensions of the dual in-line package (DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip carrier (PLCC), and quad flat pack (QFP) MCU packages. Package dimensions available at the time of this publication are provided in this section. To make sure that you have the latest case outline specifications, contact one of the following:

• Local Motorola Sales Office
• Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://design-net.com Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED Mechanical Specifications General Release Specification MC68HC05V12 — Rev. 1.0 Mechanical Specifications 18.3 68-Lead Plastic Leaded Chip Carrier (PLCC) Figure 18-1. 68-Lead PLCC, Case 779-02 NOTES: 1. DATUMS L, M, AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM T, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012. DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037. THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025. –N– –L– –M– BRKY W V D D 68 1 A R G E J VIEW S C Z SL–MM0.007 N ST 0.004 –T– SEATING PLANE X Z VIEW D–D U B DIM MIN MAX INCHES A 0.985 0.995 B 0.985 0.995 C 0.165 0.180 E 0.090 0.110 F 0.013 0.019 G 0.050 BSC H 0.026 0.032 J 0.020 ––– K 0.025 ––– R 0.950 0.956 U 0.950 0.956 V 0.042 0.048 W 0.042 0.048 X 0.042 0.056 Y ––– 0.020 Z 2 10 G1 0.910 0.930 K1 0.040 ––– /C0095/C0095 K F H VIEW S SL–MM0.007 N ST SL–MS0.010 N ST SL–MM0.007 N ST SL–MM0.007 N ST SL–MM0.007 N ST SL–MM0.007 N ST SL–MS0.010 N ST Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification

Ordering Information

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05V12 Section 19. Ordering Information

19.1 Contents

19.2 Introduction

This section contains ordering information.

19.3 MCU Ordering Forms

To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs:

• A current MCU ordering form that iscompletely filled out (Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU
• Customer’s application program on one of the media listed in19.4 Application Program Media Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC05V12 — Rev. 1.0 The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lowercase letters. Then press the return key to start the BBS software.

19.4 Application Program Media

Please deliver the application program to Motorola in one of the following media:

• Macintosh®1 3-1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M)
• MS-DOS ®2 or PC-DOSTM 3 3-1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M)
• MS-DOS ® or PC-DOSTM 5-1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette On diskettes, the application program must be in Motorola’s S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

MC68HC05V12 — Rev. 1.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if non-user areas contain any non-zero code. If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code.

19.5 ROM Program Verification

The primary use for the on-chip ROM is to hold the customer’s application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer’s application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC05V12 — Rev. 1.0

19.6 ROM Verification Units (RVUs)

After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer’s application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces ten MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer’s user ROM pattern was properly implemented. The ten RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance.

19.7 MC Order Number

Table 19-1 shows the MC order number for the available package type. Table 19-1. MC Order Number Package Type Temperature Range Order Number 68-Lead Plastic Leaded Chip Carrier (PLCC) –40 °°C to 85 □°C MC68HC05V12CFN NOTES: 1. FN = Plastic-leaded chip carrier (PLCC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006