68HC05P4A

68HC05P4A_1 FREESCALE | Alldatasheet

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REV 2.0 68HC05P4A SPECIFICATION (General Release)  December 27, 1995 CSIC MCU Design Group Oak Hill, Texas Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 iii SECTION 1 GENERAL DESCRIPTION SECTION 2 MEMORY SECTION 3 CENTRAL PROCESSING UNIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION iv Rev. 2.0 TABLE OF CONTENTS Section Title Page SECTION 4 INTERRUPTS SECTION 5 RESETS SECTION 6 LOW POWER MODES SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 v SECTION 9 COMPUTER OPERATING PROPERLY (COP) SECTION 10 SELF-CHECK MODE SECTION 11 INSTRUCTION SET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION vi Rev. 2.0 TABLE OF CONTENTS Section Title Page SECTION 13 MECHANICAL SPECIFICATIONS SECTION 14

ORDERING INFORMATION

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GENERAL RELEASE SPECIFICATION Rev. 2.0 vii LIST OF FIGURES Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION viii Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 ix Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION x Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 1-1 SECTION 1 GENERAL DESCRIPTION The MC68HC05P4A is a 28-pin device based on the MC68HC05P4. The memory map includes 4160 bytes of user ROM and 176 bytes of RAM. The MCU has two 8-bit input/output (I/O) ports, A and C. Port B has three I/O pins and port D has two pins, one that is I/O and the other input only. The MC68HC05P4A includes a simple serial I/O peripheral (SIOP) and an on-chip mask programmable computer operating properly (COP) watchdog circuit.

1.1 Features

• Low Cost
• HC05 Core
• 28-Pin Package
• On-Chip Oscillator with RC or Crystal/Ceramic Resonator Mask Options
• 4160 Bytes of User ROM Including 16 User Vector Locations
• ROM Security Feature
• 176 Bytes of On-Chip RAM
• 16-Bit Timer Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 1-2 Rev. 2.0

• Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger Mask Option
• Simple Serial Input/Output Port
• Mask Option Selectable Watchdog Timer (COP)

1.2 Mask Options

There are 13 mask options on the MC68HC05P4A:

• CLOCK (RC or Crystal)
• IRQ (Edge-Sensitive Only or Edge- and Level-Sensitive)
• SIOP (MSB or LSB First)
• COP Watchdog Timer (Enable/Disable)
• Keyscan Pullups and Interrupts on Port A (Enable/Disable by Pin).
• Stop Instruction (Option to Convert to Halt) All mask options and the user ROM are programmed on the 01 layer in fabrication. NOTE Negative true signals likeRESET and IRQ will be denoted with an overline. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 1-3

1.3 MCU Structure

Figure 1-1 shows the structure of the MC68HC05P4A. SDO/PB5 SDI/PB6 SCK/PB7 ACCUMULATOR INDEX REGISTER CONDITION CODE REGISTER STACK POINTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW CPU CONTROL ALU CPU OSCILLATOR AND DIVIDE BY □ 2 DATA DIR REG PORT B I/O LINES INTERNAL PROCESSOR CLOCK RESET IRQ OSC1 OSC2 TIMER SYSTEM COP SYSTEM PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 DATA DIR REG PORT A REGPORT A I/O LINES PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 DATA DIR REG PORT C REG PORT C I/O LINES PD5 TCMP DATA DIR REG PORT D REG PORT D I/O LINES TCAP/PD7 PORT B REG SIOP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 1-4 Rev. 2.0

1.4 Pin Assignments

The MC68HC05P4A pin assignments are shown in Figure 1-2.. Figure 1-2. Pin Assignments

1.5 Signal Description

The following paragraphs provide a description of the signals.

28 VDD

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GENERAL RELEASE SPECIFICATION Rev. 2.0 1-5

1.5.3 OSC1 and OSC2

These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins and provides a system clock. A mask option selects either a crystal/ceramic resonator or a resistor/capacitor as the frequency determining element. The oscillator frequency is two times the internal bus rate.

1.5.4 RESET

This active low pin is used to reset the MCU to a known start-up state by pulling RESET low. TheRESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity.

1.5.5 TCMP

This pin provides an output for the output compare feature of the on-chip timer system.

1.5.6 PA0 through PA7

Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000, and the data direction register is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Port A has mask option enabled pullup devices and interrupt capability by pin. For a detailed description of I/O programming, refer to1.6 Input/Output Programming. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 1-6 Rev. 2.0

1.5.7 SDO/PB5, SDI/PB6, and SCK/PB7

Port B is a 3-bit bidirectional port. These pins are shared with the SIOP subsystem. Refer toSECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT for a detailed description of the SIOP. The address of the port B data register is $0001 and the data direction register is at address $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.

1.5.8 PC0 through PC7

Port C is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port C data register is $0002 and the data direction register is at address $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Two of the port C pins, PC0 and PC1, have a higher current drive capability. SeeSECTION 12 ELECTRICAL SPECIFICATIONS .

1.5.9 PD5 and TCAP/PD7

Port D is a 2-bit port. PD5 is I/O and TCAP/PD7 is input-only shared with the timer input capture. The address of the port D data register is $0003 and the data direction register is at address $0007. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. The TCAP/PD7 pin controls the input capture feature for the on-chip programmable timer. This pin can be read at any time even if the TCAP function is enabled.

1.6 Input/Output Programming

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GENERAL RELEASE SPECIFICATION Rev. 2.0 1-7 Table 1-1. I/O Pin Functions R/W DDR I/O Pin Function 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in an output mode. The output data latch is read. R/W is an internal signal. Data Direction Register Bit Latched Output Data Bit I/O Pin Input Reg Bit Input I/O Output Internal HC05 Connections Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 1-8 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 2-1 SECTION 2 MEMORY The MC68HC05P4A has a 8 Kbyte memory map, consisting of user ROM, user RAM, self-check ROM, and I/O. See Figure 2-1 and Figure 2-2. $0000 I/O

32 Bytes

$0020 User ROM (Page Zero)

48 Bytes

$0050 RAM

176 Bytes

↑ Stack

64 Bytes

$0100 User ROM

4096 Bytes

$1100 4352 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 2-2 Rev. 2.0 ADDRESS $0000 to $001F DATA 76543210 $00 PORT A DATA $01 PORT B DATA 00000 $02 PORT C DATA $03 PORT D DATA 0 10000 $04 PORT A DDR $05 PORT B DDR 11111 $06 PORT C DDR $07 PORT D DDR 0 0 00000 $08 UNUSED $09 UNUSED $0A SERIAL CTRL SPE MSTR $0B SERIAL STAT SPF DCOL $0C SERIAL DATA $0D UNUSED $0E UNUSED $0F UNUSED $10 UNUSED $11 UNUSED $12 TIMER CONTROL ICIE OCIE TOIE IEDG OLVL $13 TIMER STATUS ICF OCF TOF $14 CAPTURE HIGH $15 CAPTURE LOW Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 2-3

2.1 ROM

The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 4096 bytes of ROM from $0100 to $10FF, and 16 bytes of user vectors from $1FF0 to $1FFF. The self-check ROM and vectors are located from $1F00 to $1FEF.

2.2 ROM Security Feature

A security feature has been incorporated into the MC68HC05P4A to help prevent external reading of code in the ROM. Placing unique customer code at ROM locations $0028-$002F aids in keeping customer developed software proprietary.

2.3 RAM

The user RAM consists of 176 bytes of a shared stack area. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. NOTE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 2-4 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 3-1 SECTION 3 CENTRAL PROCESSING UNIT This section describes the five CPU registers. CPU registers are not part of the memory map.

3.1 Accumulator (A)

The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.

3.2 Index Register (X)

The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register also may be used as a temporary storage area.

3.3 Condition Code Register (CCR)

A X Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 3-2 Rev. 2.0

3.3.2 I — Interrupt

When this bit is set, timer and external interrupts are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared.

3.3.3 N — Negative

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative.

3.3.4 Z — Zero

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.

3.3.5 C — Carry/Borrow

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.

3.4 Stack Pointer (SP)

The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits are permanently set to Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 3-3

3.5 Program Counter (PC)

The program counter is a 13-bit register that contains the address of the next byte to be fetched. NOTE The HC05 CPU core is capable of addressing a 64 Kbyte memory map. For this implementation, however, the addressing registers are limited to an 8 Kbyte memory map. 12 0 PC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 3-4 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 4-1 SECTION 4 INTERRUPTS The MCU can be interrupted four different ways: the two maskable hardware interrupts (IRQ and timer), the non-maskable software interrupt instruction (SWI), and by the optional external asynchronous interrupt on each port A pin (enabled by pullup mask option). Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. UnlikeRESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. NOTE The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 4-2 Rev. 2.0

4.1 Hardware Controlled Interrupt Sequence

The following three functions (RESET, STOP, and WAIT) are not interrupts in the strictest sense. However, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-1, and for STOP and WAIT in Figure 6- 1. A discussion is provided below. 1. RESET — A low input on theRESET input pin causes the program to vector to its starting address, which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register also is set. Much of the MCU is configured to a known state during this type of reset as described in SECTION 5 RESETS . 2. STOP — The STOP instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (IRQ) or reset occurs.See6.1 Stop Mode. 3. WAIT or HALT — The WAIT or HALT instruction causes all processor clocks to stop, but leaves the timer clock running. This rest state of the Table 4-1. Vector Address for Interrupts and Reset Register Flag Name Interrupts CPU Interrupt Vector Address N/A N/A Reset RESET $1FFE-$1FFF N/A N/A Software SWI $1FFC-$1FFD N/A N/A External Interrupt IRQ $1FFA-$1FFB TSR ICF Timer Input Capture TIMER $1FF8-$1FF9 TSR OCF Timer Output Capture TIMER $1FF8-$1FF9 TSR TOF Timer Overflow TIMER $1FF8-$1FF9 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 4-3 From RESET External Interrupt IRQ Internal Interrupt Timer I Bit Set Is Load PC From: IRQ: $1FFA-$1FFB Timer: $1FF8-$1FF9 Set I Bit Stack PC, X, A, CC ClearIRQ Request Latch Complete Interrupt Routine Fetch Next Instruction Execute Instruction Y Y Y N N N Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 4-4 Rev. 2.0

4.3 External Interrupt

The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flip- flop is latched on the falling edge ofIRQ. If either the output from the internal edge detector flip-flops or the level on theIRQ pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive only mask 0ption is selected, the output of the internal edge detector flip-flop is sampled and the input level on theIRQ pin is ignored. The interrupt service routine address is specified by the contents of memory locations $1FFA and $1FFB. A block diagram of the IRQ function is shown in Figure 4-2. NOTE The internal interrupt latch is cleared nine PH2 clock cycles after the interrupt is recognized (after location $1FFA is read). Therefore, another external interrupt pulse can be latched during the IRQ service routine. NOTE When the edge- and level-sensitive mask option is selected, the voltage applied to theIRQ pin must return to the high state before the RTI instruction in the interrupt service routine is executed to avoid the processor re-entering the IRQ service routine. IRQ PIN TO BIH & BIL INSTRUCTION SENSINGPA0 DDRA0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 4-5 The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the port A pins (PA0 thru PA7) to act as other IRQ interrupt sources. These sources are all combined into a single ORing function to be latched by the IRQ latch. Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of theIRQ pin or a port A pin if port A interrupts have been enabled. If edge-only sensitivity is chosen by a mask option, only the IRQ latch output can activate a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Falling edge on theIRQ pin with all enabled port A interrupt pins at a high level. 2. Falling edge on any enabled port A interrupt pin with all other enabled port A interrupt pins and theIRQ pin at a high level. If level sensitivity is chosen, the active high state of the IRQ input can also activate an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Low level on theIRQ pin. 2. Falling edge on theIRQ pin with all enabled port A interrupt pins at a high level. 3. Low level on any enabled port A interrupt pin. 4. Falling edge on any enabled port A interrupt pin with all enabled port A interrupt pins on theIRQ pin at a high level. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. The IRQ latch is automatically Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 4-6 Rev. 2.0

4.4 Optional External Interrupts (PA0-PA7)

The IRQ interrupt can be triggered by the inputs on the PA0 thru PA7 port pins if enabled by individual mask options. With pullup enabled, each port A pin can activate the IRQ interrupt function and the interrupt operation will be the same as for inputs to theIRQ pin. Once enabled by mask option, each individual port A pin can be disabled as an interrupt source if its corresponding DDR bit is configured for output mode. NOTE The BIH and BIL instructions apply to the output of the logic OR function of the enabled PA0 thru PA7 interrupt pins and theIRQ pin. The BIH and BIL instructions to do not exclusively test the state of theIRQ pin. NOTE If enabled, the PA0 thru PA7 pins will cause an IRQ interrupt only if these individual pins are configured as inputs.

4.5 Software Interrupt (SWI)

The SWI is an executable instruction and a non-maskable interrupt. It is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 5-1 SECTION 5 RESETS The MCU can be reset three ways: by the initial power-on reset function, by an active low input to theRESET pin, and by a computer operating properly (COP) watchdog-timer timeout.

5.1 Power-On Reset (POR)

An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay after the oscillator becomes active. If theRESET pin is low at the end of this 4064- cycle delay, the MCU will remain in the reset condition untilRESET goes high.

5.2 RESET Pin

The MCU is reset when a logic zero is applied to theRESET input for a period of one and one-half machine cycles (tcyc).

5.3 Computer Operating Properly (COP) Reset

The MCU contains a watchdog timer that automatically times out if not reset Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 5-2 Rev. 2.0 OSC1 2 RESET Internal Clock 1 Internal Address Bus 1 1FFE 1FFF New New New Op PCHPCL VDD VDD Threshold (1-2 V Typical) tVDDR tOXOV 4064 tcyc tcyc tRL Internal Data Bus 1 1FFE1FFE1FFE 1FFE New1FFF PCH PCL Op CodeCodePCLPCH NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge ofRESET initiates the reset sequence. PCPC Figure 5-1. Power-On Reset andRESET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 6-1 SECTION 6 LOW POWER MODES The MC68HC05P4A is capable of running in a low-power mode in each of its configurations. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on- chip oscillator. The STOP and WAIT instructions are not normally used if the COP watchdog timer is enabled. The stop conversion mask option is used to modify the behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes is shown in Figure 6-1.

6.1 STOP Instruction

The STOP instruction can result in one of two modes of operation, depending on the stop conversion mask option. If the stop conversion is not chosen, the STOP instruction will behave like a normal STOP instruction in the MC68HC05 Family and place the MCU in the stop mode. If the stop conversion is chosen, the STOP instruction will behave like a WAIT instruction (with the exception of a variable delay at startup) and place the MCU in the halt mode.

6.1.1 Stop Mode

Execution of the STOP instruction without conversion to halt places the MCU in its lowest power consumption mode. In the stop mode the internal oscillator is turned off, haltingall internal processing, including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 6-2 Rev. 2.0

6.1.2 Halt Mode

Execution of the STOP instruction with the conversion to halt places the MCU in this low-power mode. Halt mode consumes the same amount of power as wait mode. (Both halt and wait modes consume more power than stop mode.) In halt mode the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register enabling theIRQ external interrupt. All other registers, memory, and input/output lines remain in their previous states. If the 16-bit timer interrupt is enabled, the processor will exit the halt mode and resume normal operation. The halt mode can also be exited when anIRQ external interrupt or externalRESET occurs. When exiting the halt mode, the PH2 clock will resume after a delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode). NOTE The halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed.

6.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode, which consumes more power than the stop mode. In wait mode, the PH2 clock is halted, Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 6-3 WAIT STOP TO HALT MASK Y N EXTERNAL RESET? Y N IRQ EXTERNAL INTERRUPT? Y N STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET STARTUP DELAY RESTART EXTERNAL OSCILLATOR, RESTART STABILIZATION DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR END OF STABILIZATION DELAY? Y N IRQ EXTERNAL INTERRUPT? Y N EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE RESTART INTERNAL PROCESSOR CLOCK STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR TIMER INTERNAL INTERRUPT? Y N EXTERNAL RESET? Y N STOP HALT EXTERNAL RESET? Y N IRQ EXTERNAL INTERRUPT? Y N STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE TIMER INTERNAL INTERRUPT? Y N COP INTERNAL RESET? Y N COP INTERNAL RESET? Y N Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 6-4 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 7-1 SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT This device includes a simple synchronous serial I/O port. The SIOP is a three wire master/slave system including serial clock (SCK), serial data input (SDI), and serial data output (SDO). A mask programmable option determines whether the SIOP is MSB or LSB first.

7.1 Signal Format

The following paragraphs describe the SIOP signal format. Figure 7-1. SIOP Block Diagram 8-BIT SHIFT REGISTER D QR C RESET SDO SCK SDI MSB/LSB MASK OPTION DATA BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 7-2 Rev. 2.0 In master mode, the format is identical except that the SCK pin is an output and the shift clock now originates internally. The master mode transmission frequency is fixed at E/4.

7.1.2 Serial Data Out (SDO)

A mask programmable option will be included to allow data to be transmitted in either MSB first format or LSB first format. In either case, the state of the SDO pin always will reflect the value of the first bit received on the previous transmission if there was one. Prior to enabling the SIOP, PB5 can be initialized to determine the beginning state if necessary. While the SIOP is enabled, PB5 can not be used as a standard output since that pin is coupled to the last stage of the serial shift register. On the first falling edge of SCK, the first data bit to be shifted out is presented to the output pin.

7.1.3 Serial Data In (SDI)

The SDI pin becomes an input as soon as the SIOP is enabled. New data may be presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. SDO BIT 1 BIT 2 BIT 3 BIT 7 SCK BIT 8 SDI BIT 1 BIT 2 BIT 3 BIT 7 BIT 8 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 7-3

7.2 SIOP Registers

The following paragraphs describe the SIOP registers.

7.2.1 SIOP Control Register (SCR)

This register is located at address $000A and contains two bits. SPE — Serial Peripheral Enable When set, this bit enables the serial I/O port and initializes the port B DDR such that PB5 (SDO) is output, PB6 (SDI) is input and PB7 (SCK) is input (slave mode only). The port B DDR can be altered subsequently as the application requires and the port B data register (except for PB5) can be manipulated as usual. However, these actions could affect the transmitted or received data. When SPE is cleared, port B reverts to standard parallel I/O without affecting the port B data register or DDR. SPE is readable and writable any time but clearing SPE while a transmission is in progress will abort the transmission, reset the bit counter, and return port B to its normal I/O function. Reset clears this bit. MSTR — Master Mode When set, this bit configures the SIOP for master mode. This means that the transmission is initiated by a write to the data register and the SCK pin becomes an output providing a synchronous data clock at a fixed rate of E (bus clock) divided by four. While the device is in master mode, the SDO and SDI $0A 0 SPE 0 MSTR 0000 RESET: 00000000 Figure 7-3. SIOP Control Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION 7-4 Rev. 2.0

7.2.2 SIOP Status Register (SSR)

This register is located at address $000B and contains only two bits. SPIF — Serial Peripheral Interface Flag This bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. It has no effect on any further transmissions and can be ignored without problem. SPIF is cleared by reading the SSR with SPIF set followed by a read or write of the serial data register. If it is cleared before the last edge of the next byte, it will be set again. Reset clears this bit. DCOL — Data Collision This is a read-only status bit which indicates that an invalid access to the data register has been made. This can occur any time after the first falling edge of SCK and before SPIF is set. A read or write of the data register during this time will result in invalid data being transmitted or received. DCOL is cleared by reading the status register with SPIF set followed by a read or write of the data register. If the last part of the clearing sequence is done after another transmission has been started, DCOL will be set again. If the DCOL bit is set and the SPIF is not set, clearing the DCOL requires turning the SIOP off then turning it back on. Reset also clears this bit. $0B SPIF DCOL 000000 RESET: 00000000 Figure 7-4. SIOP Status Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 7-5

7.2.3 SIOP Data Register (SDR)

This register is located at address $000C and is both the transmit and receive data register. This system is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time, but if a transmission is in progress the results may be ambiguous. Writes to the SDR while a transmission is in progress can cause invalid data to be transmitted and/or received. This register can be read and written only when the SIOP is enabled (SPE=1). $0C RESET: UUUUUUUU Figure 7-5. SIOP Data Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION SIMPLE SERIAL INPUT/OUTPUT PORT MC68HC05P4A 7-6 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER Rev. 2.0 8-1 SECTION 8 TIMER The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. Refer to Figure 8-1 for a timer block diagram. Each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte also is accessed. NOTE The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER MC68HC05P4A 8-2 Rev. 2.0

8.1 Counter

The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several Figure 8-1. Timer Block Diagram Input Capture Register Clock Internal Bus Output Compare Register High Byte Low Byte $16 $17 □□□ Internal Processor 16-Bit Free Running Counter Counter Alternate Register 8-Bit Buffer High Byte Low Byte $1A $1B $18 $19 High Byte Low Byte $14 $15 Output Compare Circuit Overflow Detect Circuit Edge Detect Circuit Timer Status Reg. ICF OCF TOF $13 ICIE IEDG OLVL Output Level Reg. RESET Timer Control Reg. $12 Output Level (TCMP) Interrupt Circuit TOIEOCIE Edge Input (TCAP) D CLK C Q Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER Rev. 2.0 8-3 times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB also must be read to complete the sequence. The counter alternate register differs from the counter register in one respect: Aread of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled when counter rollover occurs by setting its interrupt enable bit (TOIE).

8.2 Output Compare Register

The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are compared with the contents of the free- running counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is clocked to an output level register. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER MC68HC05P4A 8-4 Rev. 2.0

8.3 Input Capture Register

Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER Rev. 2.0 8-5

8.4 Timer Control Register (TCR) $12

The TCR is a read/write register containing five control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. ICIE — Input Capture Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCIE — Output Compare Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE — Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled IEDG — Input Edge Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the input capture register 1 = Positive edge 0 = Negative edge Reset does not affect the IEDG bit (U=unaffected). OLVL — Output Level Value of output level is clocked into output level register by the next successful output compare and will appear on the TCMP pin 1 = High output 0 = Low output Bits 2, 3, and 4 — Not used Always read zero $12 ICIE OCIE TOIE 0 0 0 IEDG OLVL RESET: 00000000 Figure 8-2. Timer Control Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER MC68HC05P4A 8-6 Rev. 2.0

8.5 Timer Status Register (TSR) $13

The TSR is a read-only register containing three status flag bits. ICF — Input Capture Flag 1 = Flag set when selected polarity edge is sensed by input capture edge detector 0 = Flag cleared when TSR and input capture low register ($15) are accessed OCF — Output Compare Flag 1 = Flag set when output compare register contents match the free- running counter contents 0 = Flag cleared when TSR and output compare low register ($17) are accessed TOF — Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register ($19) are accessed Bits 0-4 — Not used Always read zero Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free- running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set, and 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag. The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. $ 1 3 I C F O C F T O F 00000 RESET: U U U 00000 Figure 8-3. Timer Status Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER Rev. 2.0 8-7

8.6 Timer During Wait or Halt Mode

The CPU clock halts during the wait or halt mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode.

8.7 Timer During Stop Mode

In the stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. IfRESET is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags wake up the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. IfRESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION TIMER MC68HC05P4A 8-8 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION COMPUTER OPERATING PROPERLY (COP) Rev. 2.0 9-1 SECTION 9 COMPUTER OPERATING PROPERLY (COP) This device includes a watchdog COP feature as a mask option. The COP is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should timeout, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (POR) or external reset.

9.1 Resetting The COP

Preventing a COP reset is done by writing a zero to the COPR bit. This action will reset the counter and begin the timeout period again. The COPR bit is bit 0 of address $1FF0. A read of address $1FF0 will access the user-defined ROM data at that location.

9.2 COP During Wait or Halt Mode

The COP will continue to operate normally during wait or halt mode. The software should pull the device out of wait or halt mode periodically and reset the COP by writing a logic zero to the COPR bit to prevent a COP reset.

9.3 COP During Stop Mode

Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. NOTE The halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION COMPUTER OPERATING PROPERLY (COP) MC68HC05P4A 9-2 Rev. 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION SELF-CHECK MODE Rev. 2.0 10-1 SECTION 10 SELF-CHECK MODE The self-check program resides at mask ROM locations $1F00 to $1FEF. This program is designed to check the part’s functionality with a minimum of support hardware. The COP subsystem is disabled in the self-check mode so that routines that feed the COP do not exist in the self-check program. The self-check mode is entered on the rising edge ofRESET if theIRQ pin is driven to double the supply voltage and the TCAP/PD7 pin is at logic one.RESET must be held low for 4064 cycles after POR or for a time tRL for any other reset. After reset, the I/O, RAM, ROM, timer, SIOP and Interrupts are tested. Self-check results (using LED’s as monitors) are shown in Table 10-1. It is not recommended that the user code use any of the self-check code. The self-check code is subject to change at any time to improve testability or manufacturability. Table 10-1. Self-Check Results PC2 PC1 PC0 REMARKS 0 0 1 Bad I/O 0 1 0 Bad RAM 0 1 1 Bad Timer 1 0 0 Bad ROM 1 0 1 Bad Serial 1 1 0 Bad Interrupt Flashing Good Device All Others Bad Device 0 indicates LED is on; 1 indicates LED is off. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION SELF-CHECK MODE MC68HC05P4A 10-2 Rev. 2.0 Figure 10-1. Self-Check Circuit 10 KΩ VDD VDD

4.7 KΩ RESET

1 µf 20 pF 10 MΩ

4 MHz

10 KΩ 470 Ω 10 KΩ VTST = 10.0 V VDD = 5.0 V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-1 SECTION 11 INSTRUCTION SET This section describes the M68HC05P4A addressing modes and instruction types.

11.1 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative

11.1.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-2 Rev. 2.0

11.1.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

11.1.3 Direct

Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination.

11.1.4 Extended

Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.

11.1.5 Indexed, No Offset

Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

11.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-3 Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.

11.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing the Motorola assembler determines the shortest form of indexed addressing.

11.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-4 Rev. 2.0

11.2 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions

11.2.1 Register/Memory Instructions

Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1 lists the register/memory instructions. Table 11-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-5

11.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 11-2 lists the read-modify-write instructions.

11.2.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding Table 11-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left ASL Arithmetic Shift Right ASR Clear Bit in Memory BCLR Set Bit in Memory BSET Clear CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-6 Rev. 2.0 the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 11-3 lists the jump and branch instructions. Table 11-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch ifIRQ Pin High BIH Branch ifIRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-7

11.2.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 11-4 lists these instructions.

11.2.5 Control Instructions

These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 11-5, use inherent addressing. Table 11-4. Bit Manipulation Instructions Instruction Mnemonic Clear Bit BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Set Bit BSET Table 11-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and EnableIRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-8 Rev. 2.0

11.3 Instruction Set Summary

Table 11-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 11-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ← (A) + (M) + (C) ↕ — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ← (A) + (M) ↕ — ↕↕↕ IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ↕↕↕ DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ← 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ← (PC) + 2 +rel ? Z = 1 ————— R E L 2 7 r r 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-9 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 +rel ? H = 0 ————— R E L 2 8 r r 3 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 +rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ← (PC) + 2 +rel ? C∨ Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch ifIRQ Pin High PC ← (PC) + 2 +rel ?IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch ifIRQ Pin Low PC ← (PC) + 2 +rel ?IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff p BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch ifLower or Same PC ← (PC) + 2 +rel ? C∨ Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 +rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ← (PC) + 2 +rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ← (PC) + 2 +rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ← (PC) + 2 +rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ← (PC) + 2 +rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if bit n clear PC ← (PC) + 2 +rel ? M n = 0 ———— ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRSET n opr relBranch if Bit n Set PC ← (PC) + 2 +rel ? M n = 1 ———— ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← (PC) + 2 +rel ? 1 = 0 ————— R E L 2 1 r r 3 Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-10 Rev. 2.0 BSET n opr Set Bit n Mn ← 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) +rel CLC Clear Carry Bit C ← 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) —— ↕↕ 1 DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C M A X M M Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-11 INC opr INCA INCX INC opr,X INC ,X Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ← Jump Address ————— DIR EXT IX2 IX1 IX BC C C D C EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP← (SP) – 1 Push (PCH); SP← (SP) – 1 PC ← Conditional Address DIR EXT IX2 IX1 IX BD C D D D ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ← (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ← (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 ↕↕ DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ← (X)× (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX ii ff NOP No Operation ————— I N H 9 D 2 Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET MC68HC05P4A 11-12 Rev. 2.0 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit —— ↕↕ × DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit —— ↕↕ × DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ← $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) INH SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ← 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and EnableIRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ← (X) — — ↕↕ — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION INSTRUCTION SET Rev. 2.0 11-13 SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 ————— DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

INSTRUCTION SET MC68HC05P4A 11-14 Rev. 2.0 Table 11-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

0123456789 AB C D EF

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS Rev. 2.0 12-1 SECTION 12 ELECTRICAL SPECIFICATIONS

12.1 Maximum Ratings

(Voltages referenced to VSS This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout)≤ VDD . Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD ).

12.2 Thermal Characteristics

Supply Voltage V DD -0.3 to +7.0 V Input Voltage V IN VSS -0.3 to VDD +0.3 V Self-Check Modes (IRQ Pin Only) V IN VSS -0.3 to 2 x VDD +0.3 V Current Drain Per Pin Excluding VDD and VSS I2 5 m A Operating Temperature Range 68HC05P4AP (Standard) 68HC05P4ACP (Extended) TA TL to TH 0 to +70 -40 to +85 Storage Temperature Range T stg -65 to +150 °C Characteristic Symbol Value Unit Thermal Resistance Plastic DIP Plastic SOIC θJA 60 °C/W °°C/W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS MC68HC05P4A 12-2 Rev. 2.0

12.3 DC Electrical Characteristics

Table 12-1. DC Electrical Characteristics (VDD = 5 V) (VDD = 5.0 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Output Voltage ILOAD = 10.0µA ILOAD = -10.0µA VOL VOH VDD -0.1 0.1 V V Output High Voltage (ILOAD = -0.8 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5 (ILOAD = -5.0 mA) PC0-PC1 VOH VOH VDD -0.8 VDD -0.8 V V Output Low Voltage (ILOAD = 1.6 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5 (ILOAD = 15 mA) PC0-PC1 VOL VOL 0.4 0.4 V V Input High Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ,RESET, OSC1 VIH 0.7× VDD —V DD V Input Low Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ,RESET, OSC1 VIL VSS — 0.2 × VDD V Supply Current Run Wait/Halt Stop 25°C 0°C to +70°C (Standard) IDD IDD IDD IDD TBD TBD TBD TBD TBD TBD TBD mA mA µA µA I/O Ports Hi-Z Leakage Current PA0-PA7, PB5-PB7, PC0-PC7, PD5 I OZ —— ±10 µA Input Current RESET, IRQ, OSC1, TCAP/PD7 I IN —— □ ±1 µA Capacitance Ports (as Input or Output) RESET, IRQ C OUT C IN pF pF NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25°C. 3. Wait IDD : Only timer system active. 4. Run (Operating) IDD , Wait IDD : Measured using external square wave clock source (fosc= 4.2 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V. 6. Wait IDD is affected linearly by the OSC2 capacitance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS Rev. 2.0 12-3 Table 12-2. DC Electrical Characteristics (VDD = 3.3 V) (VDD = 3.3 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Output Voltage ILOAD = 10.0µA ILOAD = -10.0µA VOL VOH VDD -0.1 0.1 V V Output High Voltage (ILOAD = -0.2 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = 6.0 mA) PC0-PC1 VOH VOH VDD -0.3 VDD -0.3 V V Output Low Voltage (ILOAD = 0.4 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = 6.0 mA) PC0-PC1 VOL VOL 0.3 0.3 V V Input High Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ,RESET, OSC1 VIH 0.7× VDD —V DD V Input Low Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ,RESET, OSC1 VIL VSS — 0.2 × VDD V Supply Current Run Wait/Halt Stop 25°C 0°C to +70°C (Standard) IDD IDD IDD IDD TBD TBD TBD TBD TBD TBD TBD mA mA µA µA I/O Ports Hi-Z Leakage Current PA0-PA7, PB5-PB7, PC0-PC7, PD5 I OZ —— ±10 µA Input Current RESET, IRQ, OSC1, TCAP/PD7 I IN —— □ ±1 µA Capacitance Ports (as Input or Output) RESET, IRQ C OUT C IN pF pF NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25°C. 3. Wait IDD : Only timer system active. 4. Run (Operating) IDD , Wait IDD : Measured using external square wave clock source (fosc= 2.0 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V. 6. Wait IDD is affected linearly by the OSC2 capacitance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS MC68HC05P4A 12-4 Rev. 2.0 SDO BIT 0 BIT 1 BIT 6 SCK BIT 7 SDI BIT 0 BIT 1 BIT 6 BIT 7 3 4 Figure 12-1. SIOP Timing Diagram Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS Rev. 2.0 12-5

12.4 SIOP Timing

Table 12-3. SIOP Timing (VDD = 5 V) (VDD = 5.0 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted) Table 12-4. SIOP Timing (VDD = 3.3 V) (VDD = 3.3 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted) Num. Characteristic Symbol Min Max Unit Operating Frequency Master Slave fop(m) fop(s) 0.25 dc 0.25 0.25 fop fop

1 Cycle Time

tcyc(m) tcyc(s) 4.0 4.0 4.0 tcyc tcyc

2 Clock (SCK) Low Time t cyc 932 — ns

3 SDO Data Valid Time t v — 200 ns

4 SDO Hold Time t ho 0— n s

5 SDI Setup Time t s 100 — ns

6 SDI Hold Time t h 100 — ns

NOTE: fop = 2.1 MHz maximum Num. Characteristic Symbol Min Max Unit Operating Frequency Master Slave fop(m) fop(s) 0.25 dc 0.25 0.25 fop fop tcyc(m) tcyc(s) 4.0 4.0 4.0 tcyc tcyc

2 Clock (SCK) Low Time t cyc 1980 — ns

3 SDO Data Valid Time t v — 400 ns

5 SDI Setup Time t s 200 — ns

6 SDI Hold Time t h 200 — ns

NOTE: fop = 1.0 MHz maximum Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ELECTRICAL SPECIFICATIONS MC68HC05P4A 12-6 Rev. 2.0

12.5 Control Timing

Table 12-5. Control Timing (VDD = 5 V) (VDD = 5.0 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted Table 12-6. Control Timing (VDD = 3.3 V) (VDD = 3.3 Vdc± 10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted Characteristic Symbol Min Max Unit Frequency of Operation Crystal Option External Clock Option fosc fosc dc 4.2 4.2 MHz MHz Internal Operating Frequency Crystal (fosc ÷ 2) External Clock (fosc ÷ 2) fop fop dc 2.1 2.1 MHz MHz Cycle Time t cyc 480 — ns Crystal Oscillator Startup Time t OXOV — 100 ms Stop Recovery Startup Time (Crystal Oscillator) t ILCH — 100 ms RESET Pulse Width t RL 1.5 — t cyc Interrupt Puolse Width Low (Edge-Triggered) t ILIH 125 — ns Interrupt Pulse Period t ILIL *— t cyc OSC1 Pulse Width t OH, tOL 90 — ns *The minimum period TILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. Characteristic Symbol Min Max Unit Frequency of Operation Crystal Option External Clock Option fosc fosc dc 2.0 2.0 MHz MHz Internal Operating Frequency Crystal (fosc ÷ 2) External Clock (fosc ÷ 2) fop fop dc 1.0 1.0 MHz MHz Cycle Time t cyc 1000 — ns Crystal Oscillator Startup Time t OXOV — 100 ms Stop Recovery Startup Time (Crystal Oscillator) t ILCH — 100 ms RESET Pulse Width, Excluding Powerup t RL 1.5 — t cyc Interrupt Pulse Width Low (Edge-Triggered) t ILIH 250 — ns Interrupt Pulse Period t ILIL *— t cyc OSC1 Pulse Width t OH, tOL 200 — ns *The minimum period TILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION MECHANICAL SPECIFICATIONS Rev. 2.0 13-1 SECTION 13 MECHANICAL SPECIFICATIONS This section describes the dimensions of the dual in-line package (DIP) and small outline integrated circuit (SOIC) MCU packages. 13.1 28-Pin Plastic Dual In-Line Package (Case 710-02) /C0052 /C0052 /C0077/C0073 /C0077/C0073/C0077 /C0077 /C0077/C0073 /C0073/C0077 /C0073 /C0073/C0077 /C0051 /C0052 /C0051/C0055 /C0051/C0052 /C0051 /C0051/C0055 /C0052 /C0051 /C0051/C0052/C0051 /C0052/C0051 /C0052 /C0052 /C0052 /C0052 /C0051 /C0052 /C0074 /C0077 %%! $"! /C0051 11 4 1528 B A C N K M J D /C0073 F HG L Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION MECHANICAL SPECIFICATIONS 13-2 Rev. 2.0 13.2 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) /C0077/C0073 /C0077/C0073/C0077 /C0077 /C0077/C0073 /C0073/C0077 /C0073 /C0073/C0077 /C0074 /C0077 /C0055 /C0055/C0052 /C0051 /C0051 /C0052 /C0051 /C0051 /C0055 /C0052 /C0051 /C0055 /C0055 /C0051 /C0052 /C0051 /C0055 /C0052 /C0051 /C0051 /C0052 /C0055 /C0089/C0052 /C0051 /C0052 $" /C0051 !$"! -A- -B- 11 4 1528 -T- C /C0073 M J -T- K 26X G 28X D 14X P R X 45° F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 14-1 SECTION 14 This section contains instructions for ordering custom-masked ROM MCUs.

14.1 MCU Ordering Forms

To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs:

• A current MCU ordering form that iscompletely filled out (Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU
• Customer’s application program on one of the media listed in14.2 Application Program Media The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, typebbs in lower-case letters. Then press the return key to start the BBS software. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION ORDERING INFORMATION MC68HC05P4A 14-2 Rev. 2.0

14.2 Application Program Media

Please deliver the application program to Motorola in one of the following media:

• Macintosh  1 3 1/2-inch diskette (double-sided 800K or double-sided high-density 1.4M)
• MS-DOS  2 or PC-DOS TM 3 3 1/2-inch diskette (double-sided 720K or double-sided high-density 1.44M)
• MS-DOS  or PC-DOS TM 5 1/4-inch diskette (double-sided double- density 360K or double-sided high-density 1.2M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette On diskettes, the application program must be in Motorola’s S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. NOTE Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map.Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re- submission if non-user areas contain any non-zero code. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION Rev. 2.0 14-3 If the memory map has two user ROM areas with the same address, then write the two areas in separate files on the diskette. Label the diskette with both file names. In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the file name of the source code.

14.3 ROM Program Verification

The primary use for the on-chip ROM is to hold the customer’s application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer’s application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask.

14.4 ROM Verification Units (RVUs)

After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer’s application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer’s user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...