68HC05CL16

68HC05CL48 MOTOROLA | Alldatasheet

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REV 2.0 ª Motorola, Inc., 1997 68HC05CL48 68HC705CL48 68HC05CL16 68HC705CL16 SPECIFICATION (General Release) © June 11, 1997 Hong Kong Design Center CSIC Group Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 i TABLE OF CONTENTS Section Page SECTION 1 GENERAL DESCRIPTION 1.4.1 V DD and V SS 1.4.12 SS SECTION 2 MEMORY

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 ii REV 2.0 TABLE OF CONTENTS Section Page SECTION 3 CPU SECTION 4 INTERRUPTS

4.3.2 External Interrupts (IRQ0

5.1 EXTERNAL RESET (RESET

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 iii TABLE OF CONTENTS Section Page SECTION 8 TIMER SECTION 9 SERIAL PERIPHERAL INTERFACE SECTION 10 ANALOG TO DIGITAL CONVERTER 10.1.2 V RH and V

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 iv REV 2.0 TABLE OF CONTENTS Section Page SECTION 11 CALLER-ID SECTION 12 LCD DRIVER SECTION 13 PHASE-LOCKED LOOP

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 v TABLE OF CONTENTS Section Page SECTION 14 INSTRUCTION SET SECTION 15 ELECTRICAL SPECIFICATIONS SECTION 16 MECHANICAL SPECIFICATIONS APPENDIX A MC68HC705CL48

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 vi REV 2.0 TABLE OF CONTENTS Section Page APPENDIX B MC68HC05CL16 APPENDIX C MC68HC705CL16

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 vii LIST OF FIGURES Figure Title Page

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 viii REV 2.0 LIST OF FIGURES Figure Title Page

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 ix LIST OF TABLES Table Title Page

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 x REV 2.0 LIST OF TABLES Table Title Page

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 GENERAL DESCRIPTION MOTOROLA REV 2.0 1-1 SECTION 1 GENERAL DESCRIPTION The MC68HC05CL48 HCMOS Microcontroller is a member of the M68HC05 family of low cost single chip microcontrollers. It is particularly suitable as a Caller ID telephone controller. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, I/O, Timer, Watchdog Timer, SPI, A/D, Caller ID subsystem, LCD driver and a 32kHz PLL.

1.1 FEATURES

• Industry standard M68HC05 8-bit CPU core
• 32kHz PLL to generate the 3.6MHz system clock
• On-chip clock generator can be driven by crystal or external clock
• 47.5k-bytes of user ROM
• 2k-bytes of user RAM (64 bytes for stack)
• 16-bit Timer with 2 input captures and 2 output compares, the two output compare are used for interrupt generation only
• 15-stage Multi-function Timer
• One second Watch Timer
• COP (Computer Operating Properly) Watchdog Reset
• Serial Peripheral Interface (SPI)
• Four channel 8-bit A/D Converter
• Hardware Caller-ID subsystem
• 45 x 16 or 53 x 8 LCD driver
• 24 Bidirectional I/O lines
• Three software programmable external interrupts in addition to the standard IRQ interrupt.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA GENERAL DESCRIPTION MC68HC05CL48 1-2 REV 2.0

• Five keyboard interrupts.
• Power saving STOP and WAIT modes
• Available in 112-pin TQFP package NOTE A line over a signal name indicates an active low signal. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified in Section 15

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 GENERAL DESCRIPTION MOTOROLA REV 2.0 1-3

1.2 MCU STRUCTURE

The block diagram of the MC68HC05CL48 is shown in Figure 1-1 Figure 1-1. MC68HC05CL48 Block Diagram 0 000000011 CPU CONTROL ARITHMETIC/LOGIC UNIT ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER M68HC05 MCU RESET CONDITION CODE REGISTER 111HI N C Z DATA DIRECTION REGISTER A PORT A PTA7/KB7 PTA6/KB6 PTA5/KB5 PTA4/KB4 PTA3/KB3 PTA2/IRQ2 PTA1/IRQ1 PTA0/IRQ0 COP INTERNAL OSCILLATOR DIVIDE BY TWO IRQ/VPP VDD VSS OSC1 OSC2 USER RAM — 2.0k BYTES RESET DATA DIRECTION REGISTER B PORT B PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 USER ROM — 47.5k BYTES TIMER TCAP2 TCAP1 WATCHDOG CPU CLOCK POWER INTERNAL CLOCK SPI PLL XFC CALLER ID RT_L RD1 RD2 A/D AD0 AD1 SS SCK MISO MOSI LCD DRIVER FP[44:0] BP[15:0] VLCD DATA DIRECTION REGISTER C PORT C PTC7/TCAP2 PTC6/TCAP1 PTC5/AD3 PTC4/AD2 PTC3/ SS PTC2/MOSI PTC1/MISO PTC0/SCK CONFIGURATION REGISTER C AD2 AD3 FSK– FSK+ WTIMER

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA GENERAL DESCRIPTION MC68HC05CL48 1-4 REV 2.0

1.3 PIN ASSIGNMENT

The MC68HC05CL48 pin assignments for the 112-pin TQFP package is shown in Figure 1-2 Figure 1-2. MC68HC05CL48 Pin Assignments FP43 FP42 FP41 FP40 FP39 FP38 FP37 FP36 FP35 FP34 FP33 FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 NC 112 111 110 109 108 107 106 105 104 103 102 101 100 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6FP5 FP4 FP3 FP2 FP1 FP0 PTA0/IRQ0B PTA1/IRQ1B PTA2/IRQ2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 NC PTA6/KBI6 IRQ/VPP* XFC RESET PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 VDD VSS AD1 AD0 FSK+ FSK- RT_L OSC2 OSC1 RD2 RD1 PTA7/KBI7 NC BP1 BP0 VLCD PTC0/SCK PTC1/MISO PTC2/MOSI PTC3/SS PTC4/AD2 PTC5/AD3 PTC6/TCAP1 FP44 BP15/FP45 BP14/FP46 BP13/FP47 BP12/FP48 BP11/FP49 BP10/FP50 BP9/FP51 BP8/FP52 BP7 BP6 BP5 BP4 BP3 BP2 NC NC PTC7/TCAP2 NC NC *VPP is available on MC68HC705CL48 only

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 GENERAL DESCRIPTION MOTOROLA REV 2.0 1-5

1.4 SIGNAL DESCRIPTION

The following paragraphs give a description of the general function of each pin. 1.4.1 V DD and V SS Power is supplied to the MCU through V DD and V SS pins. V DD is connected to a regulated positive supply and V SS is connected to ground. These pins are located close to each other for low EMI, Electro Magnetic Interference, emission. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency characteristics, and position them as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. Figure 1-3. Power Supply Decoupling 1.4.2 R ESET This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to VDD, when the power is removed. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. The RESET pin has an internal pulldown device that pulls the RESET pin low when there is an internal COP Watchdog reset or during the power-on reset cycles. Refer to Section 5 1.4.3 I RQ This pin has an option in the option register that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 4 VDD VSS 0.47uF (Ceramic)1uF

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA GENERAL DESCRIPTION MC68HC05CL48 1-6 REV 2.0

1.4.4 IRQ0, IRQ1, IRQ2

These three pins provide additional sources of interrupt. They are all edge- triggered only. IRQ0 and IRQ1 are both negative-edge triggered only and IRQ2 can be triggered on both rising and falling edges. Refer to Section 4.3.2 . The IRQ0, IRQ1 and IRQ2 pins contain internal Schmitt trigger as part of its input to improve noise immunity.

1.4.5 OSC1, OSC2

These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator or an external signal to these pins provides the clock to the on chip PLL. The OSC1 and OSC2 pins can accept the following: 1. A crystal as shown in Figure 1-4(a) 2. A ceramic resonator as shown in Figure 1-4(a) 3. An external clock signal as shown in Figure 1-4(b) The system clock can either be the 32kHz external clock or a higher frequency clock from the PLL. See Section 13.

1.4.5.1 Crystal with no Internal Components

The circuit in Figure 1-4(a) shows a typical oscillator circuit for an AT -cut, parallel resonant crystal. Follow the crystal manufacturer’s recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitance. Mount the crystal and components as close as possible to the pins for start-up stabilization and to minimize output distortion.

1.4.5.2 Ceramic Resonator

In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use the circuit in Figure 1-4(a) for a ceramic resonator and follow the resonator manufacturer’s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitance. Mount the resonator and components as close as possible to the pins for start-up stabilization and to minimize output distortion

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 GENERAL DESCRIPTION MOTOROLA REV 2.0 1-7 Figure 1-4. Oscillator Connections

1.4.6 External Clock

An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-4 (b)

1.4.7 PTA0-PTA7

These I/O lines comprise Port A. The state of any pin is software programmable and all port lines are configured as inputs during power-on or reset. PTA0-PTA7 are also associated with three external IRQ and five Keyboard interrupt functions. See Section 7 for more details on the I/O ports.

1.4.8 PTB0-PTB7

These I/O lines comprise Port B. The state of any pin is software programmable and all port lines are configured as inputs during power-on or reset.

1.4.9 PTC0-PTC7

These I/O lines comprise Port C. The state of any pin is software programmable and all port lines are configured as inputs during power-on or reset. PTC0-PTC7 To VDD (or STOP) (b) External Clock Source Connections MCU OSC1 OSC2 unconnected External Clock To VDD (or STOP) (a) Crystal or Ceramic* Resonator Connections X-tal = Nitsuko EX-0228-0150-NTK OSC1 OSC2 MCU *: Additional capacitance may be required for Ceramic Resonator option. Follow the Ceramic Resonator manufacturer’s recommendations. 10M 100k 27pF 27pF

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA GENERAL DESCRIPTION MC68HC05CL48 1-8 REV 2.0 when not used as I/O pins can be configured as two A-to-D pins, two Timer pins and four SPI pins. See Section 7 for more details on the I/O ports.

1.4.10 SCK

This is the serial clock signal of the SPI. This pin can be configured as PTC0 pin when the SPI function is not used.

1.4.11 MISO, MOSI

These are the master-in slave-out (MISO) and master-out slave-in (MOSI) data pins for the SPI. These two pins can be configured as PTC1 and PTC2 pins respectively when the SPI function is not used. 1.4.12 S S This is the slave select pin for the SPI. This pin can be configured as PTC3 pin when the SPI function is not used.

1.4.13 AD0-AD3

These four lines are the A/D inputs. AD2 and AD3 can be configured as PTC4 and PTC5 pins respectively when not used as A-to-D inputs.

1.4.14 TCAP1

The TCAP1 input controls the input capture 1 feature of the on-chip programmable timer system. Refer to Section 8 for additional information. This pin can be configured as PTC6 pin when the timer input capture function is not used.

1.4.15 TCAP2

The TCAP2 input controls the input capture 2 feature of the on-chip programmable timer system. Refer to Section 8 for additional information. This pin can be configured as PTC7 pin when the timer input capture function is not used.

1.4.16 FSK+, FSK–

These two inputs are the non-inverting and inverting FSK signals respectively.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 GENERAL DESCRIPTION MOTOROLA REV 2.0 1-9

1.4.17 RT_L

This pin should be connected with an external pull-up resistor to vDD. This pin will be pulled low when RDI1 rises above one volt.

1.4.18 RD1, RD2

These inputs are incoming ring qualifiers.

1.4.19 BP0 - BP15

These are the back plane drivers dedicated to the LCD subsystem. BP8 - BP15 will be used as FP45 - FP52 when the LCD driver is only driving 8 back planes.

1.4.20 FP0 - FP44

These are the front plane drivers dedicated to the LCD subsystem.

1.4.21 VLCD, V0, V1, V2, V3, V4

VLCD is the power supply input for the LCD voltage generator. V0, V1, V2, V3 and V4 are the internal resistor ladder node voltage. An external cap with one terminal connected to GND should be connected to each of these four pins.

1.4.22 XFC

One terminal of the Phase-Locked Loop external capacitor should be connected here, the other terminal should be connected to GND. XFC 0.1uF Phase-Locked Loop External Capacitor

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA GENERAL DESCRIPTION MC68HC05CL48 1-10 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MEMORY MOTOROLA REV 2.0 2-1 SECTION 2 MEMORY The MC68HC05CL48 has a 64k-byte memory map, consisting of user ROM, user RAM, Self-Check ROM, LCD RAM and I/O as shown in Figure 2-1.

2.1 MEMORY MAP

The MC68HC05CL48 memory map is shown in Figure 2-1.

2.2 I/O AND CONTROL REGISTERS

The I/O and Control Registers reside in locations $0000-$002F . The overall organization of these registers is shown in Figure 2-1. The bit assignments for each register are shown in Figure 2-2, Figure 2-3 and Figure 2-4. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored.

2.2.1 Option Register ($1F)

This register can be written to only once following a Power-On-Reset (POR) but can be read at any time. This register configures the MCU options to suit the user’s application. OSC_ON 1 = Oscillator is switched on in STOP mode. 0 = Oscillator is switched off in STOP mode. COP Refer to Section 8 for detailed informations on COP . 1 = Enable the COP watchdog reset. 0 = Disable the COP watchdog reset. 76543210 OPT $001F READ OSC_ON COP INTO WRITE POR 1 1 U U U U 1 U U = UNAFFECTED

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MEMORY MC68HC05CL48 2-2 REV 2.0 INTO 1 = allow negative edge-triggered interrupt on IRQ pin. 0 = allow ‘low’ level-triggered and negative edge-triggered interrupt on IRQ pin.

2.3 LCD RAM

The LCD RAM consists of 90 bytes at locations ($0930 thru $095C) and ($0A30 thru $0A5C).

2.4 RAM

The total RAM consists of 2.0k bytes (including the stack) at locations $0030 thru $082F . The stack begins at address $00FF and proceeds down to $00C0. The stack pointer can access 64 locations from $00FF to $00C0. Using the stack area for data storage or temporary work locations requires care to prevent it from being over written due to stacking from an interrupt or subroutine call.

2.5 ROM

There are a total of 47.5k bytes of user ROM from locations $4000 thru $FDFF for user program storage and 16 bytes for user vectors at locations $FFF0 thru $FFFF .

2.6 I/O MAPPED REGISTERS

There are 48 internal registers at locations $0000 thru $002F . These are illustrated in Figure 2-2, Figure 2-3 and Figure 2-4.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MEMORY MOTOROLA REV 2.0 2-3 Figure 2-1. MC68HC05CL48 Memory Map Ctimer/WTimer $FFF0 $FFF1 IRQn/KBI $FFF2 $FFF3 Caller_ID $FFF4 $FFF5 SWI $FFFC $FFFD SPI $FFF6 $FFF7 Timer $FFF8 $FFF9 IRQ $FFFA $FFFB Reset $FFFE $FFFF I/O Register

48 Bytes

$0000 $002F RAM

144 Bytes

$00FF Not Used $0030 Stack

64 Bytes

$082F $3FFF ROM 47.5k Bytes $4000 Self-check ROM

496 Bytes

$FFEF Self-check Vectors

16 Bytes

$FE00 User Vectors $FFF0 $FFFF $FFE0 $FFDF $00C0 Port A Data Register $00 Port B Data Register $01 $02 Port A Direction Register $03 Timer Pin Configuration Register $04 $05 $06 $07 Core Timer Control/Status Register$08 Core Timer Register $09 $0A $0B $0C $0D Caller ID Data Register $0E $0F $10 $11 Timer Status Register $12 $13Input Capture High Register 1 $14Input Capture Low Register 1 $15Output Compare High Register 1 $16Output Compare Low Register 1 $17 Counter High Register $18 Counter Low Register $19 Alternate Counter High Register $1A Alternate Counter Low Register $1B External Interrupt Control Register $1C External Interrupt Status Register $1D $1E Option Register $1F Not Used $095C

1840 Bytes

45 Bytes Block1

Input Capture Low Register 2 Timer Control Register Output Compare Low Register 2 Output Compare High Register 2 Input Capture High Register 2 Caller ID Control/Status Register 2 Caller ID Control/Status Register 1 LCD Control Register Caller ID Control/Status Register 3 PLL Status/Data Register $FDFF $20 $21 $22 $23 $24 $25 $26 $2F $27 SPI Control Register SPI Status Register SPI Data Register Port C Data Register Port B Direction Register Port C Direction Register Watch Timer Control & Status Register A/D Control and Status Register A/D Data Register Reserved for EPROM (EPCR) Reserved $0930 $0830 $0100 LCD RAM

45 Bytes Block2

$0A5D $0A5C $0A30 Not Used $092F $095D $0A2F

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MEMORY MC68HC05CL48 2-4 REV 2.0 ADDR REGISTER ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0000 PORTA R PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 W $0001 PORTB R PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 W $0002 PORTC R PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 W $0003 DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W $0004 DDRB R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W $0005 DDRC R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W $0006 TIMCONF R CONF7 CONF6 W $0007 LCDCR R CC3 CC2 CC1 CC0 MX8 BIAS5 DISONW $0008 CTCSR R CTOF RTIF CTOFE RTIE RT1 RT0 W $0009 CTCR R CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 W $000A CLCSR1 R RDIF RDIE CDIF CDIE RDO CDO W $000B CLCSR2 R RDPW CDPW CIDSD RD CD W $000C CLCSR3 R SDSL CDRE DRIE CDRF RDOE CDOE W $000D PCSR R PON PCLK FREQ1 FREQ0 W $000E CDDR R CDD7 CDD6 CDD5 CDD4 CDD3 CDD2 CDD1 CDD0W $000F IC2H R IC2:15 IC2:14 IC2:13 IC2:12 IC2:11 IC2:10 IC2:9 IC2:8 W Figure 2-2. MC68HC05CL48 I/O Registers $0000-$000F

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MEMORY MOTOROLA REV 2.0 2-5 ADDR REGISTER ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0010 IC2L R IC2:7 IC2:6 IC2:5 IC2:4 IC2:3 IC2:2 IC2:1 IC2:0 W $0011 TCR R IC1IE IC2IE OC1IE OC2IE TOIE IEDG2 IEDG1W $0012 TSR R IC1F IC2F OC1F OC2F TOF W $0013 IC1H R IC1:15 IC1:14 IC1:13 IC1:12 IC1:11 IC1:10 IC1:9 IC1:8 W $0014 IC1L R IC1:7 IC1:6 IC1:5 IC1:4 IC1:3 IC1:2 IC1:1 IC1:0 W $0015 OC1H R OC1:15 OC1:14 OC1:13 OC1:12 OC1:11 OC1:10 OC1:9 OC1:8 W $0016 OC1L R OC1:7 OC1:6 OC1:5 OC1:4 OC1:3 OC1:2 OC1:1 OC1:0 W $0017 OC2H R OC2:15 OC14 OC2:13 OC2:12 OC2:11 OC2:10 OC2:9 OC2:8 W $0018 OC2L R OC2:7 OC2:6 OC2:5 OC4 OC2:3 OC2:2 OC2:1 OC2:0 W $0019 TCH R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W $001A TCL R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W TIMER RESET $001B ACH R AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 W $001C ACL R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W TIMER RESET $001D EXICR R KBE7 KBE6 KBE5 KBE4 KBE3 IRQE2 IRQE1 IRQE0W $001E EXISR R KBIF7 KBIF6 KBIF5 KBIF4 KBIF3 IRQF2 IRQF1 IRQF0 W $001F OPT R OSC_ON COP INTOW Figure 2-3. MC68HC05CL48 I/O Registers $0010-$001F

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MEMORY MC68HC05CL48 2-6 REV 2.0 ADDR REGISTER ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0020 SPCR R SPIE SPE - MSTR CPOL CPHA SPR1 SPR0W $0021 SPSR R SPIF WCOL 0 MODF 0000 W $0022 SPDR R SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 W $0023 WTCSR R WTOFF WTOIE WTOF W WTR $0024 ADSCR R COCO ADRC ADON CH2 CH1 CH0 W $0025 ADDR R ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 W $0026 Reserved for EPROM (EPCR) R W $0027 Not Used R W $0028 Not Used R W $0029 Not Used R W $002A Not Used R W $002B Not Used R W $002C Not Used R W $002D Not Used R W $002E Reserved for TEST R W $002F TEST R W Figure 2-4. MC68HC05CL48 I/O Registers $0020-$002F

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CPU MOTOROLA REV 2.0 3-1 SECTION 3 CPU The MC68HC05CL48 has an 64k memory map. Therefore it uses all 16 bits of the address bus. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap- around to $00FF . All other instructions and registers behave as described in this chapter.

3.1 REGISTERS

The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1 and are described in the following paragraphs. Figure 3-1. MC68HC05 Programming Model

3.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations A X SP PC CC HALF CARRY INTERRUPT MASK NEGATIVE ZERO CARRY 76 543210 15 14 13 12 11 10 9 8 ACCUMULATOR INDEX REGISTER STACK POINTER CONDITION CODE REGISTER 00000 0 0110 HI NZC111 PROGRAM COUNTER

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CPU MC68HC05CL48 3-2 REV 2.0 or non-arithmetic operations. The accumulator is unaffected by a reset of the device.

3.1.2 Index Register (X)

The index register shown in Figure 3-1 is an 8-bit register that can perform two functions:

• Indexed addressing
• Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register contents to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register contents to a 16-bit immediate value The index register can also serve as an auxiliary accumulator for temporary storage.The index register is unaffected by a reset of the device.

3.1.3 Stack Pointer (SP)

The stack pointer shown in Figure 3-1 is a 16-bit register internally. In devices with memory maps less than 64 kbytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF . The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 ($40) locations. If 64 locations are exceeded, the stack pointer wraps around and writes over the previously stored information. A subroutine call occupies two locations on the stack, and an interrupt uses five locations.

3.1.4 Program Counter (PC)

The program counter shown in Figure 3-1 is a 16-bit register internally. In devices with memory maps less than 64 Kbytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CPU MOTOROLA REV 2.0 3-3 Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

3.1.5 Condition Code Register (CCR)

The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register.

3.1.5.1 Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.

3.1.5.2 Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), STOP , or WAIT instructions.

3.1.5.3 Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CPU MC68HC05CL48 3-4 REV 2.0 to the state of the flag.

3.1.5.4 Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero.

3.1.5.5 Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or DEC instruction.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INTERRUPTS MOTOROLA REV 2.0 4-1 SECTION 4 INTERRUPTS Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $FFF0 thru $FFFF as defined in Table 4-1. An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing. Table 4-1. Vector Address for Interrupts and Reset Interrupts CPU Interrupt Vector Addresses Reset RESET $FFFE-$FFFF Software SWI $FFFC-$FFFD External Interrupt IRQ $FFFA-$FFFB Timer TCAP1,TCAP2,TCMP1,TCMP2 $FFF8-$FFF9 SPI SPI $FFF6-$FFF7 Caller ID CDI, RDI, CDRI, RT_L $FFF4-$FFF5 External Interrupt/Keyboard Interrupt IRQ0, IRQ1, IRQ2, KBI[7:3] $FFF2-$FFF3 Core Timer/Watch Timer Ctimer, WTimer $FFF0-$FFF1

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INTERRUPTS MC68HC05CL48 4-2 REV 2.0 Figure 4-1. Interrupt Processing Flowchart Clear IRQ Latch From RESET Is I-Bit Set? Y N IRQn/KBI Interrupt? Y N Caller_id Interrupt? Y N CTimer/WTimer Interrupt? Y N PC -> (SP ,SP-1) X -> (SP-2) A -> (SP-3) CC -> (SP-4) Set I-Bit in CCR CC,A,X,PC Fetch Next Instruction Load Interrupt Vectors To PC SWI Instruction? Y N RTI Instruction? Y N Execute Instruction Restore Registers From Stack IRQ Interrupt? Y N SPI Interrupt? Y N Timer Interrupt? Y N

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INTERRUPTS MOTOROLA REV 2.0 4-3

4.1 RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or internal generated reset signal causes the program to vector to its starting address which is specified by the contents of memory locations $FFFE and $FFFF . The I-bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in Section 5.

4.2 SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched, or before interrupts if interrupts were generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $FFFC and $FFFD.

4.3 HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are six types of hardware interrupts which are explained in the following sections.

4.3.1 External Interrupt (IRQ

If the IRQ option is both level and edge sensitive triggering (INTO=0), a low level or an negative edge at the IRQ pin and the interrupt mask bit of the condition code register is cleared will cause an EXTERNAL Interrupt to occur. If the MCU has finished with the interrupt service routine, but the IRQ pin is still low, the EXTERNAL Interrupt will start again. In fact, the MCU will keep on servicing the EXTERNAL Interrupt as long as the IRQ pin is low. If the IRQ pin goes low for a while and resumes to high (a negative pulse) before the interrupt mask bit is cleared, the MCU will not recognize there was an interrupt request, and no interrupt will occur after the interrupt mask bit is cleared, i.e. there is no latch for the interrupt signal for the level sensitive triggering. If the IRQ option is negative edge sensitive triggering (INTO=1), a negative edge occurs at the IRQ pin and the interrupt mask bit of the condition code register is cleared will cause an EXTERNAL Interrupt to occur. If the MCU has finished with the interrupt service routine, but the IRQ pin has not resumed back to high, no further interrupt will be generated. The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) only. If the negative edge occurs during the interrupt mask bit is set, the interrupt signal will be latched, an

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INTERRUPTS MC68HC05CL48 4-4 REV 2.0 interrupt will occur as soon as the interrupt mask bit is cleared. The latch will be cleared by RESET or cleared automatically during fetch of the EXTERNAL Interrupt vectors. Therefore, one (and only one) external interrupt edge could be latched during the interrupt mask bit is set. The service routine address is specified by the contents of $FFFA and $FFFB. Figure 4-2 shows both a block diagram and the two methods for the interrupt line (IRQ) to the processor. The first method is single pulses on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a function of the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the next interrupt is recognized. NOTE INTO is located at bit-1 of the Option Register at $001F , and is set by reset. The Option Register can only be written once after reset.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INTERRUPTS MOTOROLA REV 2.0 4-5 Figure 4-2. External Interrupts IRQ pin INTO bit I bit (CCR) External Power-On Reset External Reset External Interrupt DQ CK R Being Serviced Interrupt Request (read of vectors) (a) Interrupt Functional Block Diagram IRQ IRQ1 IRQn IRQ (MCU) tILIH tILIL tILIH Edge-sensitive Trigger Condition The minimum pulse width tILIH is one The period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 cycles Level-sensitive Trigger Condition If after servicing an interrupt, the IRQ Normally used with pull-up resistor for remains low, then the next interrupt is recognized. Wire-Ore connected (b) Interrupt Mode Diagram internal bus period.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INTERRUPTS MC68HC05CL48 4-6 REV 2.0

4.3.2 External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7])

4.3.2.1 IRQ0, IRQ1, IRQ2

IRQ0, IRQ1, IRQ2 interrupt function is associated with PTA[0:2]. IRQ[0:2] interrupts behave similar to IRQ except these are edge-triggered only. IRQ0 and IRQ1 are both negative-edge triggered only and IRQ2 can be triggered on both rising and falling edges. To enable this function, IRQE0, IRQE1 and IRQE2 bit of the external interrupt control register (EXICR $1D) should be set first. When an appropriate edge occurring at the IRQ0 , IRQ1 or IRQ2 pin and the interrupt mask bit of the condition code register is cleared will cause an external interrupt to occur. If the MCU has finished with the service routine, but the external interrupt pin has not resumed backed to high, no further interrupt will be generated. If the appropriate triggering edge occurs when the interrupt mask bit is set, the interrupt signal will be latched, and interrupt will occur as soon as the interrupt mask bit is cleared. The latch for IRQ0 , IRQ1 and IRQ2 are cleared by reset or cleared by writing a ‘0’ to the IRQF0, IRQF1 and IRQF2 bit in the external interrupt status register ($1E EXISR) in the service routine. The interrupt service routine is specified by the contents of the memory locations $FFF2 and $FFF3. To prevent unwanted interrupts generated on RQ0 , IRQ1 pins. A logic ‘1’ should be written to these pins before setting their corresponding interrupt enable bits. Likewise, A logic ‘1’ should be written to IRQ2 pin prior to setting the IRQ2 interrupt enable bit.

4.3.2.2 Keyboard Interrupts

Keyboard Interrupt function is associated with PTA[3:7]. The keyboard interrupt function is enabled by setting the individual interrupt enable bits KBE[3:7] (bits[3:7] of EXICR at $001D). When the KBE bit is set, the corresponding Port A pin will be configured as an input pin, regardless of the DDR setting, and a 100k ohm pull-up resistor is connected to the pin, as shown in Figure 4-3. When a high to low transition is sensed on the pin, a keyboard interrupt will be generated, provided the I-bit in the CCR is cleared. The interrupt signal is latched, and it should be cleared by writing a ‘0’ to the corresponding KBIF bit in the external interrupt status register ($1E EXISR) in the interrupt service routine. This should be cleared after the key is debounced, or unwanted keyboard interrupt signal will be generated. The Keyboard Interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the contents of the memory locations $FFF2 and $FFF3.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INTERRUPTS MOTOROLA REV 2.0 4-7 To prevent unwanted interrupts generated on KBI[3:7] pins. A logic ‘1’ should be written to these pins before setting their corresponding interrupt enable bits. Figure 4-3. Keyboard Interrupt Circuitry

4.3.2.3 External Interrupt Control Register (EXICR $001D)

KBE[7:3] 1 = Enable Keyboard interrupt on PTA[7:3] respectively. 0 = Disable Keyboard interrupt on PTA[7:3] respectively. IRQE[2:0] 1 = Enable IRQ interrupt on PTA[2:0] respectively. 0 = Disable IRQ interrupt PTA[2:0] respectively. 76543210 EXICR $001D READ KBE7 KBE6 KBE5 KBE4 KBE3 IRQ2E IRQ1E IRQ0E WRITE RESET 00000000 VDD External pins PTA[3.7] Pad LogicInternal Data bits [3.7], Port A DDR(3-7) KBE[3.7] 100k KBI[3.7]

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INTERRUPTS MC68HC05CL48 4-8 REV 2.0

4.3.2.4 External Interrupt Status Register (EXISR)

KBIF[7:3] The keyboard interrupt flag bit is set to ‘1’ when a negative edge has been detected at the pin and the corresponding enable bit has been set. Writing a ‘0’ to this bit will clear the corresponding interrupt flag. This bit should be cleared by software in the keyboard interrupt service routine, or the CPU will keep on serving this interrupt. IRQF[2:0] The external IRQ flag bit is set to ‘1’ when an appropriate edge has been detected at the pin and the corresponding enable bit has been set. Writing a “0” to this bit will clear the IRQ interrupt flag. This bit should be cleared by software in the keyboard interrupt service routine, or the CPU will keep on serving this interrupt.

4.3.3 Caller ID Interrupt (RDI/CDI,CDRI)

This interrupt is caused by the Caller ID module when a valid RT_L signal, a Ring is detected, a Carrier is detected or when the 8-bit Called ID data is ready to be read. The enable and flag bits for the Ring Detect and the Carrier detect are located in CLCSR1 register and the enable and flag bits for the Called ID data ready are located in CLCSR3 register. The RT_L is always active once it is enabled by a metal mask, see Section 11. All four interrupts will vector to the same interrupt service routine located at the addresses specified by the contents of memory locations $FFF4-$FFF5. The RT_L interrupt will wake up the MCU from the STOP and WAIT mode whereas the Ring Detect, Carrier Detect and Data Ready interrupts will wake up the CPU from Wait mode. See Section 6.

4.3.4 TIMER Interrupt

The TIMER interrupt is generated by the multi-function Timer when a timer overflow or an input capture or a output compare has occurred as described in Section 8. The interrupt enable bit and flag for the Timer interrupt are located in the Timer Control and Status Registers TCR and TSR located at $0011 and $0012 respectively. The I-bit in the CCR must be clear in order for the Timer interrupt to 76543210 EXISR $001E READ KBIF7 KBIF6 KBIF5 KBIF4 KBIF3 IRQF2 IRQF1 IRQF0 WRITE RESET 00000000

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INTERRUPTS MOTOROLA REV 2.0 4-9 be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $FFF8 and $FFF9.

4.3.5 SPI Interrupt

The SPI interrupt is generated by serial peripheral interface as described in Section 9. The interrupt enable bits for the SPI interrupt is in the SPI Control Register (SPCR) at location $0020. The I-bit in the CCR must be clear in order for the SPI interrupt to be enabled. These interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $FFF6 and $FFF7.

4.3.6 CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer)

4.3.6.1 Core Timer Interrupt

The CTIMER interrupt is generated by the Core Timer when a core timer overflow, or real time interrupt has occurred as described in Section 8. The interrupt enable bits and flags for the Core Timer interrupts are located in the Core Timer Control and Status Register (CTCSR) located at $0008. The I-bit in the CCR must be clear in order for the CTIMER interrupt to be enabled.

4.3.6.2 Watch Timer Interrupt

The WTimer interrupt is generated by the Watch Timer when a 1 second timer overflow interrupt has occurred as described in Section 8. The interrupt enable bits and flags for the Watch Timer interrupt are located in the Watch Timer Control and Status Register (WTCSR) located at $0023. The I-bit in the CCR must be clear in order for the WTIMER interrupt to be enabled.

4.3.6.3 Interrupt Vector

The above two interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $FFF0 and $FFF1.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INTERRUPTS MC68HC05CL48 4-10 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 RESETS MOTOROLA REV 2.0 5-1 SECTION 5 RESETS The MCU can be reset in three ways:

• by the initial power-on reset function, (POR)
• by an active low input to the RESET pin, (RESET)
• by a COP watchdog timer reset, (COPR)

5.1 EXTERNAL RESET (RESET )

The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input can alter the operating mode of the MCU. The RESET pin can also be pulled to a low state by an internal pulldown that is activated by the internal COP Watchdog or Power-on resets. This RESET pin pulldown device will only be activated for one cycle of the internal clock, PH2, when a COP Watchdog reset occurs; or will remain activated as long as counting the power-on reset cycles or the low voltage is detected.

5.2 POWER-ON RESET (POR)

The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 488 internal processor bus clock cycles (PH2) after the oscillator becomes active. The RESET pin will be pulled down internally during these cycles. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this 488 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA RESETS MC68HC05CL48 5-2 REV 2.0

5.3 COMPUTER OPERATING PROPERLY RESET (COPR)

The internal COPR reset is generated automatically (if enabled) by a time-out of the COP Watchdog Timer. This time-out occurs if the counter in the COP Watchdog Timer is not reset (cleared) within a specific time by a program reset sequence. The COP Watchdog Timer can be enabled by setting bit 6 of the Option Register at $001F . Refer to Section 8 for more information on this time-out feature. The COP Watchdog reset will activate the internal pulldown device connected to the RESET pin for one cycle of the internal clock, PH2. The COP register shares the same address ($FFF0) with the MS byte of the Core Timer Interrupt Vector as shown below. Reading this location will return the MS byte of the Core Timer Interrupt Vector. Writing $00 to this location clears the COP watchdog timer. 76543210 COPR $FFF0 READ WRITE COPR P O R UUUUUUU0 U = UNAFFECTED

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LOW POWER MODES MOTOROLA REV 2.0 6-1 SECTION 6 LOW POWER MODES

6.1 LOW-POWER MODES

The MC68HC05CL48 has two low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP Watchdog Timer is enabled. The flow of the STOP and WAIT modes is shown in Figure 6-1.

6.1.1 STOP Instruction

Execution of the STOP instruction, places the MCU in its lowest power consumption mode. In the STOP Mode the internal oscillator is turned off, halting all internal processing, including the COP Watchdog Timer. When the CPU enters STOP Mode, the I-bit in the Condition Code Register will be cleared automatically. This enable the external hardware interrupt to wake up the MCU. All other registers and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP Mode only by a Caller ID (RT_L) interrupt, WTIMER interrupt, a hardware interrupt “IRQ, IRQ(n), KBI(n)” or an externally generated RESET. When exiting the STOP Mode the internal oscillator will resume after a 488 internal processor clock cycle oscillator stabilization delay.

6.1.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode, which consumes more power than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Other Internal clocks remain active, permitting interrupts to be generated from the functional blocks, or a reset to be generated from the COP Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT Mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can wake up the MCU. All other registers, memory, and input/output lines remain in their previous states.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LOW POWER MODES MC68HC05CL48 6-2 REV 2.0

6.2 DATA-RETENTION MODE

The contents of RAM and CPU registers are retained at supply voltage as low as 2.0 VDC. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. The RESET pin must be held low during data-retention mode. To put CPU into data retention mode with the lowest power:

• Clear OSC_ON bit in OPTION register.
• Run system with Oscillator clock.
• Execute STOP instruction to put CPU in STOP mode.
• Drive RESET pin to logical zero.
• Lower the VDD voltage. The RESET must remain low continuously during data retention mode. To take the CPU out of data retention mode:
• Return VDD to normal operating level.
• Return the RESET pin to logical one.

6.3 COP WATCHDOG TIMER CONSIDERATIONS

If the COP Watchdog Timer is selected by setting the enable bit, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will be executed as a WAIT instruction. It is because, if a STOP instruction could be executed, while the COP was enabled. The STOP instruction will cause the oscillator to halt and prevent the COP Watchdog Timer from timing out. Therefore, the STOP instruction will put the MCU into WAIT mode, instead of STOP mode, if COP is enabled. If the COP Watchdog Timer is selected, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP Watchdog should be disabled for a system that must have intentional uses of the WAIT Mode for periods longer than the COP time-out period.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LOW POWER MODES MOTOROLA REV 2.0 6-3 Figure 6-1. STOP/WAIT Flowchart STOP and Reset Start-up Delay Stop External Oscillator, Stop Internal Timer CLock, Stop Internal Processor Clock, Clear I-Bit in CCR External RESET? Y N External H/W Interrupt? Y N Restart External Oscillator, and Stabilization Delay End of Start-up Delay? N Y Restart Internal Processor Clock 2. Service Interrupt 1. Fetch Reset Vector or a. Stack b.Set I-Bit c.Vector to Interrupt Routine WAIT Timer Clock Active External Oscillator Active, and Internal Stop Internal Processor Clock, Clear I-Bit in CCR External RESET? Y N Internal COP Reset? Y N External H/W Interrupt? Y N Internal Interrupt? Y N Caller_id Interrupt? Y N Caller_ID (RT_L) Interrupt? Y N WTimer Interrupt? Y N

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LOW POWER MODES MC68HC05CL48 6-4 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INPUT/OUTPUT PORTS MOTOROLA REV 2.0 7-1 SECTION 7 INPUT/OUTPUT PORTS In single-chip mode there are 24 pins arranged as 3 8-bit I/O port. The I/O ports are programmable as either inputs or outputs under software control of the data direction registers. To avoid a glitch on the output pins, write data to the I/O Port Data Register before writing a one to the corresponding Data Direction Register.

7.1 PARALLEL PORTS

Port A and B and C are 8-bit bidirectional port. Each Port pin is controlled by the corresponding bits in a data direction register and a data register as shown in Figure 7-1. The functions of the I/O pins are summarized in Table 7-1. Figure 7-1. Port I/O Circuitry Table 7-1. Port I/O Pin Functions R/W DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in an output mode. The output data latch is read. Read/Write DDR Write Data Read Data Data Direction Register Data Register Bit I/O PinOUTPUT Internal HC05 Data Bus Reset (RST )

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INPUT/OUTPUT PORTS MC68HC05CL48 7-2 REV 2.0

7.2 PORT A

Port A is an 8-bit bidirectional port. The port A data register is at $0000 and the data direction register (DDRA) is at $0003. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. In addition to normal I/O port function, PTA0-PTA2 are also used as additional external interrupt inputs and PTA3-PTA7 are also associated with the KEYBOARD interrupt function. See Section 4.3.2 for detail description on External and Keyboard interrupts.

7.3 PORT B

Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDRB) is at $0004. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.

7.4 PORT C

Port C is an 8-bit bidirectional port which shares its pins with subsystems A-2-D, SPI and Timer under the control of the A-2-D status and control register ADCSR, the SPI control register SPCR and the Timer pin configuration register TIMCONF . The port C data register is at $0002, the data direction register (DDRC) is at $0005. Reset does not affect the data register, but clears the data direction, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Writing a ‘1’ to the SPE-bit of the SPI control register SPCR configures PTC[0:3] as dedicated SPI pins. Setting CONF6-bit and CONF7-bit of the Timer pin configuration register TIMCONF to ‘1’ configures PTC6 and PTC7 as Timer input capture pins respectively. PTC[4:5] will always be available as IO port pins even after the ADON-bit is set. When ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control register is set to select channel-2, PTC[4] becomes an A-2-D input pin. When ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control register is set to select channel-3, PTC[5] becomes an A-2-D input pin. Table 7-1. summarizes the PORT C function when used as sub-system pins. Table 7-2. PORT C I/O Configuration PORT C I/O Mode Sub-System Function PTC0 Input Output SCK: SPI slave clock-in (MSTR = ‘0’, SPE=1). SCK: SPI master clock-out (MSTR = ‘1’, SPE=1).

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INPUT/OUTPUT PORTS MOTOROLA REV 2.0 7-3 PTC1 Input Output MISO: SPI slave data out (MSTR=0, SPE=1) MISO: SPI master data in (MSTR=1, SPE=1) PTC2 Input Output MOSI: SPI slave data in (MSTR=0, SPE=1) MOSI: SPI master data out (MSTR=1, SPE=1) PTC3 Input SS: SPI slave select signal (SPE=1) Note: This pin is internally connected to VDD when (MSTR=1), this means that PTC3 can be used as a normal port pin. PTC4 Input AD2: A-to-D input (ADON=1 and Channel-2 selected) PTC5 Input AD3: A-to-D input (ADON=1 and Channel-3 selected) PTC6 Input TCAP1: Timer input capture1 (CONF6=1). PTC7 Input TCAP2: Timer input capture2 (CONG7=1). Table 7-2. PORT C I/O Configuration PORT C I/O Mode Sub-System Function

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INPUT/OUTPUT PORTS MC68HC05CL48 7-4 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-1 SECTION 8 TIMER The MC68HC05CL48 has three timers:

• 16-bit free-running timer
• 15-stage multi-functional (core) timer
• One second timer 8.1 16-BIT FREE-RUNNING TIMER The 16-bit free-running counter is driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. Refer to Figure 8-1 for a timer block diagram. Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. NOTE The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-2 REV 2.0 Figure 8-1. 16-Bit Free-running Timer Block Diagram MC68HC05 Internal Bus Interrupt Circuit Internal Timer Clock (NTF1) 8-bit Buffer Interrupt Logic TCRTSR High Byte Low Byte Output Compare Circuit 1 16-bit Free Running Counter Alternate Counter Register TCH ACHOC1H Overflow Detect Circuit Edge Detect Circuit1 Input Capture Register 1 OC2H Output Compare Circuit 2 Output Compare Register 2 Output Compare Register 1 TCAP1 OC2FOC1F IC2FTOF OC2IEOC1IE IC1IE IEDG1TOIE & OC2L& OC1L & TCL & ACL IC1H & IC1L Input Capture Register 2 IC2H & IC2L Edge Detect Circuit2 TCAP2 IC1F IC2IE IEDG2

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-3

8.1.1 Counter

The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.2 microseconds if the internal bus clock is 1.8MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $19-$1A (counter register) or $1B-$1C (counter alternate register). A read from only the least significant byte (LSB) of the free-running counter ($1A, $1C) receives the count value at the time of the read. If a read of the free-running 76543210 TCH $0019 READ TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 WRITE RESET 11111111 76543210 TCL $001A READ TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 WRITE Counter Reset RESET 11111100 76543210 ACH $001B READ AC15 AC14 AC13 AC12 AT11 AC10 AC9 AC8 WRITE RESET 11111111 76543210 ACL $001C READ AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 WRITE Counter Reset RESET 11111100

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-4 REV 2.0 counter or counter alternate register first addresses the most significant byte (MSB) ($19, $1B), the LSB ($1A, $1C) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($1A or $1C) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: a read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF . Figure 8-2. Timer State Diagram For Timer Overflow The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE). In some particular timing control applications it may be desirable to reset the 16- bit free running counter under software control. When the low byte of the counter ($1A or $1C) is written to, the counter is configured to its reset value ($FFFC). Internal Processor Clock Internal Timer Clocks T00 T01 T10 T11 Counter (16 bit) Timer Overflow Flag (TOF) $FFFE $FFFF $0000 $0001 NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by read of the Timer Status Register during the internal processor clock time followed by a read of the counter low register. $0002

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-5 The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of the flags and enable bits remain unaltered by this operation. If access has previously been made to the high byte of the free running counter ($19 or $1B), then the reset counter operation terminates the access sequence. Figure 8-3. Timer State Timing Diagram For Reset

8.1.2 Output Compare Registers

There are two output compare registers: output compare register 1 and output compare register 2. Output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations.

8.1.2.1 Output Compare Register 1

$0015 READ OC1:15 OC1:14 OC1:13 OC1:12 OC1:11 OC1:10 OC1:9 OC1:8 WRITE RESET UUUUUUUU Internal Processor Clock Internal Reset Internal Timer Clocks T00 T01 T10 T11 Counter (16bit) RESET (External or POR) $FFFC $FFFD $FFFE $FFFF NOTE: The Counter Register and Timer Control Register are the only ones affected by RESET.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-6 REV 2.0 The 16-bit output compare register 1 is made up of two 8-bit registers at locations $15 (MSB) and $16 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the corresponding output compare flag OC1F (bit 5 of timer status register $12) is set. The output compare register values should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit OC1IE (bit 5 of timer control register $11) is set. After a processor write cycle to the output compare register containing the MSB ($15), the output compare function is inhibited until the LSB ($16) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($16) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. Because the output compare flag OC1F and the output compare register 1 are undetermined at power on, and are not affected by external reset, care must be exercised when initializing the output compare function. The following procedure is recommended: 1. Write the high byte to the compare register 1 to inhibit further compares until the low byte is written. 2. Read the status register to arm the OC1F if it is already set. 3. Write the output compare register 1 low byte to enable the output compare 1 function with flag clear. The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read and the write to the corresponding output compare register. 76543210 OC1L $0016 READ OC1:7 OC1:6 OC1:5 OC1:4 OC1:3 OC1:2 OC1:1 OC1:0 WRITE RESET UUUUUUUU

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-7

8.1.2.2 Output Compare Register 2

The 16-bit output compare register 2 is made up of two 8-bit registers at locations $17 (MSB) and $18 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the corresponding output compare flag OC2F (bit 4 of timer status register $12) is set. The output compare register values should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit OC2IE (bit 4 of timer control register $11) is set. After a processor write cycle to the output compare register containing the MSB ($17), the output compare function is inhibited until the LSB ($18) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($18) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. Because the output compare flag OC2F and the output compare register 2 are undetermined at power on, and are not affected by external reset, care must be exercised when initializing the output compare function. A procedure as recommended for Compare Register 1 should be followed. 76543210 OC2H $0017 READ OC2:15 OC2:14 OC2:13 OC2:12 OC2:11 OC2:10 OC2:9 OC2:8 WRITE RESET UUUUUUUU 76543210 OC2L $0018 READ OC2:7 OC2:6 OC2:5 OC2:4 OC2:3 OC2:2 OC2:1 OC2:0 WRITE RESET UUUUUUUU

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-8 REV 2.0 Figure 8-4. Timer State Timing Diagram For Output Compare

8.1.3 Input Capture Registers

8.1.3.1 Input Capture Register 1

$0013 READ IC1:15 IC1:14 IC1:13 IC1:12 IC1:11 IC1:10 IC1:9 IC1:8 WRITE RESET UUUUUUUU Internal Processor Clock Internal Timer Clocks T00 T01 T10 T11 Counter (16 bit) Compare Register Latch $FFEB $FFEC $FFED $FFEE 1. The CPU writes to the Compare Register may take place at any time, but a compare $FFEF Compare Register CPU writes $FFED $FFED Output Compare Flag (OCF) 2. Internal compare takes place during timer state T01. 3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this only occurs at timer state T01. Thus, a 4-cycle different may exist between the write to the Compare Register and the actual compare. example).

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-9 Two 8-bit registers, which make up the 16-bit input capture register, these are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG1). Reset does not affect the contents of the input capture register.

• IEDG1 = 0: Capture on negative edge
• IEDG1 = 1: Capture on positive edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI1E (bit 7 of the timer control register $11) is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC1F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($13) MSB, the counter transfer is inhibited until the LSB ($14) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($14) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 76543210 IC1L $0014 READ IC1:7 IC1:6 IC1:5 IC1:4 IC1:3 IC1:2 IC1:1 IC1:0 WRITE RESET UUUUUUUU

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-10 REV 2.0

8.1.3.2 Input Capture Register 2

Two 8-bit registers, which make up the 16-bit input capture register, these are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG2). Reset does not affect the contents of the input capture register.

• IEDG2 = 0: Capture on negative edge
• IEDG2 = 1: Capture on positive edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI2E (bit 6 of the timer control register $11) is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC2F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($0F) MSB, the counter transfer is inhibited until the LSB ($10) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($10) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 76543210 IC2H $000F READ IC2:15 IC2:14 IC2:13 IC2:12 IC2:11 IC2:10 IC2:9 IC2:8 WRITE RESET UUUUUUUU 76543210 IC2L $0010 READ IC2:7 IC2:6 IC2:5 IC2:4 IC2:3 IC2:2 IC2:1 IC2:0 WRITE RESET UUUUUUUU

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-11 Figure 8-5. Timer State Timing Diagram For Input Capture

8.1.4 Timer Control Register (TCR)

The timer control registers TCR is a read/write register. Five bits control interrupts associated with the timer status register flags IC1F , IC2F , OC1F , OC2F and TOF . The other two bits control which edge is significant to the input capture edge detector (i.e., negative or positive). The timer control register and the free running counter are the only sections of the timer affected by reset. The timer control registers are illustrated below by a definition of each bit. 76543210 TCR $0011 READ IC1IE IC2IE OC1IE OC2IE TOIE IEDG2 IEDG1 WRITE RESET 00000X U U U = UNAFFECTED Internal Processor Clock Internal Timer Clocks T00 T01 T10 T11 Counter (16 bit)$FFEB $FFEC $FFED $FFEE $FFEF Input Edge note Input Capture Latch Input Capture Flag (ICF) NOTE: If the input edge occurs in the shaded area from one timer state T10 to the other timer state T10 the Input Capture Flag is set during the next state T11.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-12 REV 2.0 IC1IE - Input Capture 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled IC2IE - Input Capture 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OC1IE - Output Compare 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OC2IE - Output Compare 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE - Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled IEDG2 - Input Edge 2 Value of the input edge determines which level transition on TCAP2 pin will trigger a free running counter transfer to the input capture register. Reset does not affect the IEDG2 bit. 1 = positive edge 0 = negative edge IEDG1 - Input Edge Value of the input edge determines which level transition on TCAP1 pin will trigger a free running counter transfer to the input capture register. Reset does not affect the IEDG1 bit. 1 = positive edge 0 = negative edge

8.1.5 Timer Status Register (TSR)

The timer status register is a read-only register and is illustrated below followed by a definition of each bit. Refer to timing diagrams shown in Figure 8-3, Figure 8-2 and Figure 8-4 for timing relationship to the timer status register bits. 76543210 TSR $0012 READ IC1F IC2F OC1F OC2F TOF WRITE RESET UUUUUUU0 U = UNAFFECTED

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-13 IC1F - Input Capture Flag 1 = Flag set when a selected polarity edge has been sensed by the input capture edge detector. 0 = Flag cleared by reading the timer status register (with IC1F set) followed by accessing the low byte ($14) of the input capture register. IC2F - Input Capture Flag 1 = Flag set when a selected polarity edge has been sensed by the input capture edge detector. 0 = Flag cleared by reading the timer status register (with IC2F set) followed by accessing the low byte ($10) of the input capture register. OC1F - Output Compare 1 Flag 1 = Flag set when the output compare register 1 contents matches the contents of the free running counter. 0 = Flag cleared by reading the timer status register (with OC1F set) and then accessing the low byte ($16) of the output compare 1 register. OC2F - Output Compare 2 Flag 1 = Flag set when the output compare register 2 contents matches the contents of the free running counter. 0 = Flag cleared by reading the timer status register (with OC2F set) and then accessing the low byte ($18) of the output compare 1 register. TOF - Timer OVerflow Flag 1 = Flag set by transition of the free running counter from $FFFF to $0000. 0 = Flag cleared by reading the timer status register (with TOF set) followed by an access of the free running counter least significant byte ($1A). Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free- running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set, and 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-14 REV 2.0 The counter alternate register at address $1B and $1C contains the same value as the free-running counter (at address $19 and $1A); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register.

8.1.6 Timer Pin Configuration Register (TIMCONF)

The timer pin configuration register is a read/write register, this is used to control PTC[6:7] pin function. CONF7- Pin configuration 7 1 = Configures PTC7 as timer input capture pin. 0 = PTC7 used as normal I/O port pin. CONF6- Pin configuration 6 1 = Configures PTC6 as timer input capture pin. 0 = PTC6 used as normal I/O port pin.

8.1.7 Operation During Low Power Mode

During the wait and stop modes, the timer stops and holds at its current state, retaining all data, and resumes operation from this point when external interrupt (IRQ), or internal interrupt is received.

8.2 CORE TIMER

The MC68HC05CL48 Core Timer (or Ctimer) for is a 15-stage multi-functional ripple counter. The features include Timer Over Flow, Power-On Reset (POR), Real Time Interrupt, and COP Watchdog Timer. As seen in Figure 8-6, the Timer is driven by the internal bus clock divided by four with a fixed prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Ctimer Counter Register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of E/1024. One additional stages produce the POR function at E/2064. The Timer Counter Bypass circuitry (available only in Test Mode) is at this point in the 76543210 TIMCONF $0006 READ CONF7 CONF6 WRITE RESET 0 0 UUUUU0 U = UNAFFECTED

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-15 timer chain. This circuit is followed by two more stages, with the resulting clock (E/ 16384) driving the Real Time Interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided by eight to drive the optional COP Watchdog Timer circuit. The RTI rate selector bits, and the RTI and CTOF enable bits and flags are located in the Ctimer Control and Status Register(CTCSR) at location $08. Figure 8-6. Core Timer Block Diagram COP Clear Internal Bus $09 CTCR 7-bit counter Interrupt Circuit $08 CTCSR RTI Select Circuit Overflow Circuit Detect COP Watchdog Resetable Timer(‚8) To Interrupt Logic fop fop/22 fop/210 POR TCBP TCSR TCR Internal Processor Clock RTIF CTimer Control & Status Register Core Timer Counter Register (TCR) CTOFE -RTIECTOF RT1- RT0 To Reset Logic

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-16 REV 2.0

8.2.1 Computer Operating Properly (COP) Watchdog reset

The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP time-out is done by writing a “0” to bit 0 of address $FFF0. This location is shared with User ROM byte. And reading this location will return the User ROM data. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared. If the COP (Computer Operating Properly) Watchdog Timer circuit times out, an internal reset is generated and the reset vector is fetched. This function is software selectable by setting the COP bit in the Option Register. The COP bit is set after reset, i.e. the COP function is defaulted. The COP function can be disable by writing a ‘0’ to this bit. NOTE COP is located at bit 6 of the Option Register at $001F , which can only be written once after reset.

8.2.2 Ctimer Control and Status Register (CTCSR)

The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. CTOF - Core Timer Over Flow This is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. 1 = No effect 0 = Clearing the TOF RTIF - Real Time Interrupt Flag The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The clock frequency that drives the RTI circuit is E/2 13 with three additional divider stages. This flag is a clearable, read-only status bit and is set 76543210 CTCSR $0008 READ CTOF RTIF CTOFE RTIE RT1 RT0 WRITE RESET 00000011

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-17 when the output of the chosen (1 of 4 selection) stage goes active. 1 = No effect 0 = Clearing the RTIF CTOFE - Core Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the TOF bit is set, provided the I bit in CCR is cleared. 1 = Interrupt enable 0 = Interrupt disable RTIE - Real Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set, provided the I bit in the CCR is cleared. 1 = Interrupt enable 0 = Interrupt disable RT1:RT0 - Rate Select These two bits select one of four taps from the Real Time Interrupt circuit. The settings for RTI is listed in Table 8-1. Reset sets these RT0 and RT1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. NOTE Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps.

8.2.3 Ctimer Counter Register (CTCR)

The Core Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-18 REV 2.0 The power-on cycle clears the entire counter chain and begins clocking the counter. After 2016 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted any time during operation (other than POR), the counter chain will be cleared.

8.2.4 Operation During Low Power Mode

The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt or an external RESET, the internal oscillator will resume, followed by 2016 cycles internal processor stabilization delay. The timer is then cleared and operation resumes. The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. 76543210 CTCR $0009 READ CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 WRITE RESET 00000000 Table 8-1. RTI and COP Rates at 1.8MHz Bus Frequency BUS FREQUENCY = 1.8 MHz RT1:RT0 Div. Ratio RTI Rate COP Rate (RTIx7) 00 214 9.1 ms 63.7 ms 01 215 18.2ms 127.4 ms 10 216 36.4 ms 254.8 ms 11 217 72.8 ms 509.6 ms

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 TIMER MOTOROLA REV 2.0 8-19

8.3 ONE SECOND WATCH TIMER

The 1 second Watch Timer is a 15-bit free running counter which runs off the 32kHz external clock directly and is therefore not affected by Stop Mode or Wait Mode. The Watch Timer is used to generate interrupts at 1 second interval to wake up the CPU when the I-bit in the CCR is cleared. See Figure 8-7. The Watch Timer overflow flag WTOF is set when the a transition from $7FFF to $0000 occurs and will cause an interrupt if the WTOIE-bit of the Watch Timer control and status register (WTCSR $0023) is set to ‘1’. This flag is latched and should be cleared by the Watch Timer interrupt service routine to prevent unwanted interrupts. Writing a ‘0’ to the WTOF-bit or reset clears the WTOF-bit. Power on or external reset has no effect on the free running counter and therefore the counter state is unknown after reset. However, the Watch Timer can be reset to a known state by writing a ‘1’ to the WTR-bit in the Watch Timer control and status register. The WTOF flag is prevented from being set during software reset. Reading the WTR-bit will always return a ‘0’. The Watch Timer can be disabled by writing a ‘1’ to the WTOFF-bit of the Watch Timer control and status register, the value of the Watch Timer is retained during the off period. Table 8-2. RTI and COP Rates 17.5kHz Bus Frequency BUS FREQUENCY = 17.5 kHz RT1:RT0 Div. Ratio RTI Rate COP Rate (RTIx7) 00 214 0.94 s 6.58 s 01 215 1.88 s 13.16 s 10 216 3.76 s 26.32 s 11 217 7.52 s 52.64 s

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-20 REV 2.0 Figure 8-7. ONE Second Watch Timer

8.3.1 Watch Timer Control & Status Register (WTCSR)

1 = Disable Watch Timer 0 = Enable Watch Timer WTR Writing a ‘1’ to this bit will generate a reset pulse to reset the Watch Timer. Reading this bit will always return a ‘0’. WTOIE 1 = Enable 1 second interrupt. 0 = Disable 1 second interrupt. WTOF 1 = Flag set by transition of the 15-bit free running counter from $7FFF to $0000 0 = Flag cleared by writing a 0 to the WTOF bit. 76543210 WTCSR $0023 READ WTOFF WTOIE WTOF WRITE WTR RESET ----0 0 0 0 U = UNAFFECTED 15-bit Free Running Counter 32kHz External Clock WTOIEWRTWTOFF WTOF RESETOFF 1 second overflow WTimer Interrupt

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 SERIAL PERIPHERAL INTERFACE MOTOROLA REV 2.0 9-1 SECTION 9 SERIAL PERIPHERAL INTERFACE The term “serial peripheral” refers to the fact that this interface requires separate wires (signals) for data and clock. In this format, data does not contain an explicit clock. The SPI scheme may be used to interconnect microcomputers located at a short distance (usually within a single “black box” or on the same PC card). This may comprise a system of one microcomputer and several slaves or may be a system of microcomputers, each having the capability of either master or slave. A practical system may include: 1) MISO master in slave out 2) MOSI master out slave in 3) SCK serial clock 4) SS (n) slave select(s)

9.1 SIGNAL DESCRIPTION

9.1.1 MISO Master In Slave Out

9.1.1.1 Slave Mode

MISO is the signal which is used in Slave Mode to present data from a Slave device to the bus. The MISO pin will be placed in the hi-Z state whenever a Slave device is “not” selected (SS=1) by the bus master. Figure 9-1 shows the clock (SCK) and data relationship. Four possible timing relationships may be chosen by use of the control bits (CPOL) and (CPHA). The Slave device and a Master device must be programmed to be in similar timing modes for proper data transfer.

9.1.1.2 Master Mode

In the master mode (control bit MSTR=1), the function of MOSI and MISO are inverted within the device. Therefore, the MISO pin becomes the data input pin for a device which is in the master mode. (Also, the function of SCK switches from being an input for system clock to one of outputting the system clock.)

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA SERIAL PERIPHERAL INTERFACE MC68HC05CL48 9-2 REV 2.0

9.1.2 MOSI Serial Data In (Input)

9.1.2.1 Slave Mode

MOSI is the signal used to receive data from some Master device. Figure 9-1 shows the serial clock and data timing relationship. It should be noted that when a Master device transmits data to a second device via the MOSI line, the slave device (if it has the capability) will respond by sending data into the MISO pin of the master device. This implies full duplex transmission with both data-out and data-in synchronized to the same clock signal which is provided by the master. Moreover, the SAME shift register is used for data out and data in. Thus, the byte transmitted is replaced by the byte received, removing the need for separate status bits for XMIT EMPTY and REC FULL. A single status bit, SPIF , is used to signify IO operation complete.

9.1.2.2 Master Mode

As noted above, the function of MOSI and MISO are inverted in the master mode. The MOSI pin becomes the data output pin when the device is in the master mode. When a transfer of data is not taking place with a Slave device the Master drives the MOSI line high. The Master always allows the data onto the MOSI pin a half-cycle before the clock edge (SCK) needed for the Slave to latch the data internally.

9.1.3 SCK Serial Clock (In/Out)

9.1.3.1 Slave Mode

The serial clock is used to move data both in and out of the device through its MOSI and MISO pins. The Master and Slave device are capable of exchanging a byte of information during a sequence of eight clock pulses if wired to do so. In the slave mode, the SCK pin becomes an input for the external clock being sent from the Master device. In this case SCK is asynchronous to the Slave device’s phase 1-2 clocks and read/write control, therefore synchronization must take place prior to transmission and after reception. This must be done on the byte level. The type of clock and its’ relationship with the data is controlled by bits CPOL and CPHA. Reference Figure 9-1. The clock rate control bits SPR1 and SPR0 have no function while the part is in the Slave mode.

9.1.3.2 Master Mode

In this mode, the clock is generated within the Master device by a circuit driven

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 SERIAL PERIPHERAL INTERFACE MOTOROLA REV 2.0 9-3 from the bus clock. The clock rate is selected by bits (SPR1,SPR0) in the control register. The SCK pin on the Master device becomes a fixed output providing the system clock to an enabled Slave or Slaves. The clock is used by the Master to latch incoming Slave data on the MISO pin and shift out data to the Slave device on the MOSI pin. The Master and Slave must be operated in the same timing mode. The type of clock and its’ relationship with the data is controlled by bits CPOL and CPHA. Reference Figure 9-1. 9.1.4 S S SLAVE SELECT (INPUT)

9.1.4.1 Slave Mode

The slave select (SS input) is generated by the master (parallel port may be used) and used to “enable one” of several slaves to accept and/or return data or “enable several” slaves to accept data. To insure a data byte transfer, the SS signal must be low prior to occurrence of SCK and must not become high until after the 8th (last) SCK cycle. Figure 9-1 shows the clock (SCK) and data relationship. Depending on the state of the CPHA control bit, the SS pin pulled low: (1) allows the first bit of data onto the MISO system line for transfer and (2) prevents the Slave from reading or writing the data register. A further description of the affect of the (SS) pin and (CPHA) control bit on the i/o data register is given in the description of the (WCOL) status flag. The (WCOL) flag warns the Slave if it has had a conflict between a transmission and a write of the data register. A high level on SS forces MISO to the hi-Z state. Also, SCK and MOSI are ignored by the disabled slave.

9.1.4.2 Master Mode

In this mode, Slave Select (SS) input is monitored to assure that it stays false (high). If Slave Select becomes true, the device immediately exits the master mode and becomes a slave (MSTR=0). Also, control bit (SPE) is forced to a zero causing all SPI system pins to be inputs. An interrupt flag (MODF) is set warning the device that the above events have occurred. The significance of this is that a collision has occurred; that is, two devices have both become masters. This is normally the result of software error, although some systems may allow the default master to “knock all other masters off the bus” if an erroneous bus state is detected. This is, of course, a catastrophic event and it is the responsibility of the default master to completely “clean up” the system.

9.2 SPI REGISTERS

The register addresses only show the low order address bits i.e ABL(1:0). The registers can be placed anywhere in the device memory map by generating an appropriate ‘M odule Select’ signal in the map logic.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA SERIAL PERIPHERAL INTERFACE MC68HC05CL48 9-4 REV 2.0

9.2.1 SPCR SPI Control Register

When this bit is set to a one a hardware interrupt sequence is requested each time the SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I-bit in the CC-Register is one. SPE SPI System Enable Setting the SPE-bit to ‘1’ will enable the SPI function and automatically configure PTC[3:0] as dedicated SPI pins. MSTR Master/Slave Mode Select 0 = Slave mode 1 = Master mode CPOL Clock Polarity CPHA Clock Phase These two bits are used to specify the clock format to be used in SPI operations. Please refer to Figure 9-1. SPR1, SPR0 SPI Clock (SCK) Rate Select Bits These bits are used to specify the SPI clock rate. 76543210 SPCR $0020 READ SPIE SPE - MSTR CPOL CPHA SPR1 SPR0 WRITE RESET 00-001U U Table 9-1. SPI Clock Rates SPR1 SPR0 E Clock divided-by Frequency Eclk = 1.8 MHz (baud rate) 0 0 2 0.9 MHz 0 1 4 450 kHz 1 0 16 112.5 kHz 1 1 32 56.25 kHz

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 SERIAL PERIPHERAL INTERFACE MOTOROLA REV 2.0 9-5 Figure 9-1. SPI Clock/Data Relationships begin endTransfer SCK Sample(I) Change(O) Sel SS MSB LSB CPOL:CPOA = 0:0 begin end MSB LSB Transfer SCK Sample(I) Change(O) Sel SS CPOL:CPOA = 1:1 Transfer SCK Sample(I) Change(O) Sel SS Transfer SCK Sample(I) Change(O) Sel SS MSB LSB begin end MSB LSB CPOL:CPOA = 1:0 CPOL:CPOA = 0:1 begin end

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA SERIAL PERIPHERAL INTERFACE MC68HC05CL48 9-6 REV 2.0

9.2.2 SPSR SPI Status Register

SPIF SPI Interrupt Request SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPSR register (with SPIF set) followed by an access (read or write) to the SPI Data Register. WCOL Write Collision Status Flag This error status flag is used to indicate that a serial transfer was in progress when the MCU tried to write new data into the SPDR data register. The MCU write is disabled to avoid writing over the data being transmitted. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. This flag is automatically cleared by a read of the SPSR (with WCOL set) followed by an access (read or write) to the SPDR register. MODFSPI Mode Error Interrupt Status Flag This bit is set automatically by SPI hardware if the MSTR control bit is set to one and the Slave Select input pin becomes zero. This condition is not permitted in normal operation. This flag is automatically cleared by a read of the SPSR (with MODF set) followed by a write to the SPCR register.

9.2.3 SPDR SPI Data Register

This 8-bit register is both the input and output register for SPI data. In the SPI system the 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO wires to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master so the data is effectively 76543210 SPSR $0021 READ SPIF WCOL 0 MODF 0000 WRITE RESET 00000000 76543210 SPDR $0022 READ SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 WRITE RESET UUUUUUUU

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 SERIAL PERIPHERAL INTERFACE MOTOROLA REV 2.0 9-7 exchanged between the master and the slave. Note that some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. When writing the SPDR, the data is written directly into the shift register and always shifted out MSB first. When reading the SPDR, a Read Data Buffer is actually accessed. This buffer contains the last data byte received by the SPI, and is updated during the cycle that SPIF is set (reception complete).

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA SERIAL PERIPHERAL INTERFACE MC68HC05CL48 9-8 REV 2.0

June 6, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 ANALOG TO DIGITAL CONVERTER MOTOROLA REV 2.0 10-1 SECTION 10 ANALOG TO DIGITAL CONVERTER The MC68HC05CL48 includes a 8-channel, 8-bit, multiplexed input, successive approximation A/D converter, with four of the input channels available on external pins and another four internal channels are used for calibration purpose.

10.1 ANALOG SECTION

10.1.1 Ratiometric Conversion

The A/D is ratiometric, with two dedicated pins supplying the reference voltages RH and VRL). An input voltage equal to VRH converts to $FF (full scale) and an input voltage equal to VRL converts to $00. An input voltage greater than VRH will convert to $FF with no overflow indication. For ratiometric conversions, the source of each analog input should use V RH as the supply voltage and be referenced to VRL .

10.1.2 VRH and VRL

VRH and VRL are generated internally on chip to reduce pin counts.

10.1.3 Accuracy And Precision

The 8-bit conversions shall be accurate to within – 11/2 LSB including quantization when averaged over four readings.

10.2 CONVERSION PROCESS

The A/D reference inputs are applied to a precision internal digital-to-analog converter. Control logic drives this D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. The conversion process is monotonic and has no missing codes.

GENERAL RELEASE SPECIFICATION June 6, 1997 MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC05CL48 10-2 REV 2.0

10.3 DIGITAL SECTION

10.3.1 Conversion Time

Each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 MHz.

10.3.2 Multi-Channel Operation

In User Mode a multiplexer allows the single A/D converter to select one of eight analog signals, two of which are VRH and VRL . The ATD3:0 are input signals to the multiplexer.

10.4 A/D STATUS AND CONTROL REGISTER (ADCSR)

The following paragraphs describe the function of the A/D Status and Control Register.

10.4.1 COCO - Conversions Complete

This read-only status bit is set when a conversion is completed, indicating that the A/D Data Register contains valid results. This bit is cleared whenever the A/D Status and Control Register is written and a new conversion automatically started, or whenever the A/D Data Register is read. Once a conversion has been started by writing to the A/D Status and Control Register, conversions of the selected channel will continue every 32 cycles until the A/D Status and Control Register is written again. In this continuous conversion mode the A/D Data Register will be filled with new data, and the COCO bit set, every 32 cycles. Data from the previous conversion will be overwritten regardless of the state of the COCO bit prior to writing.

10.4.2 ADRC - A/D RC Oscillator Control

When the RC oscillator is selected (ADRC = 1) to be the A/D clock source, it requires a time t ADRC to stabilize. Results can be inaccurate during this time. If the CPU clock is running below 1 Mhz, the RC oscillator must be used. When ADRC =0, the A/D uses the CPU clock. 76543210 ADSCR $0024 READ COCO ADRC ADON CH2 CH1 CH0 WRITE RESET UUUUUUUU

June 6, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 ANALOG TO DIGITAL CONVERTER MOTOROLA REV 2.0 10-3

10.4.3 ADON - A/D On

When the A/D is turned on (ADON = 1), it requires a time tADON for the current sources to stabilize, and results can be inaccurate during this time. This bit turns on the charge pump. If the ADRC is set, clearing this bit disables the RC oscillator to save power.

10.4.4 CH2:CH0 - Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field which is used to select one of eight A/D channels. Channels 0-3 correspond to the analog input pins: ATD(3:0) in the MCU. Channels 4-7 are used for internal reference points. The following table shows the signals selected by the channel select field.

10.5 A/D DATA REGISTER (ADDR)

One 8-bit result register is provided. This register is updated each time COCO is set

10.6 A/D DURING WAIT MODE

The A/D continues normal operation during WAIT mode. To decrease power consumption during WAIT, it is recommended that both the ADON and ADRC bits in the A/D Status and Control Register be cleared if the A/D converter is not being used. If the A/D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit be cleared. CHANNEL SIGNAL

0 ATD0 pin

1 ATD1 pin

2 ATD2/PTC[4] pin

3 ATD3/PTC[5] pin

6( V RH - VRL )/4 7( V RH - VRL )/2 Table 10-1. A/D Channel Assignments 76543210 ADDR $0025 READ ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 WRITE RESET UUUUUUUU

GENERAL RELEASE SPECIFICATION June 6, 1997 MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC05CL48 10-4 REV 2.0

10.7 A/D DURING STOP MODE

In STOP mode the comparator and charge pump are turned off and the A/D ceases to function. Any pending conversion is aborted. When the clocks begin oscillation upon leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize enough to provide conversions to the specified accuracy. The delays built into the MC68HC05 when coming out of STOP mode are sufficient for this purpose, therefore no explicit delays need to be built into the software.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-1 SECTION 11 CALLER-ID The Caller ID module demodulates the Bell 202 and CCITT V.23 1200 baud FSK asynchronous data. This module consists of four major building blocks - FSK demodulator, Carrier Detect, Ring Detect and the Power Management circuit. The block diagram of this module is shown in Figure 11-1. Figure 11-1. Caller ID Block Diagram Tip Ring + Ring 202 Demod Detect Circuit BPF Valid Data Detect Power Management Carrier Detect Circuit Carrier Detect Interface Ring Detect Interface Demod Data Control/Status Register 1 Control/Status Register 2 Serial Data Select Interrupt Circuit MCU Data Bus SDSL CPU Interrupt Ring Det 1 Ring Det 2 Ring Time VAG Power CTL from CPU Control/Status Register 3

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-2 REV 2.0

11.1 FSK DEMODULATOR

The recovered signal consists of both the channel seizure information and the message words. The original serial raw data is made available via the MCU registers. See Section 11.7.2.

11.2 CARRIER DETECTOR

The Carrier Detect block will validate the carrier signal from the filter section. The asynchronous carrier signal is considered valid if present for a minimum of 25ms. A carrier dropout is confirmed if it is silent for more than 8ms. The carrier detect signal will remain low until a dropout condition is detected. The carrier detect output is available in a read-only register (CD ) in Control/Status Register 2 (CLCSR2). It can also be overwritten by writing to CDO (Carrier Detect Override) in the Control/Status Register 1 (CLCSR1) when enabled by writing a ‘1’ to CDOE (Carrier Detect Override Enable) in the CLCSR3 register. A valid carrier can also produce an interrupt to the CPU when enabled by the CDIE bit in CLCSR1. See Section 11.7.1 and Section 11.7.2 Figure 11-2. Carrier Detect Interface

11.3 RT_L INTERRUPT

Figure 11-3 shows that the RT_L pin connected to a ring time circuit. When RDI1 is ‘low’, RT_L is pulled high by the external pull-up resistor. When RDI1 rises above 1.0 volt, RT_L will be pulled low by the open-drain NMOS transistor and an interrupt will be generated. Note: RT_L interrupt is permanently disabled in the current design and can only be enabled by a Metal Mask Option. Carrier Detect CDO CDOE CD DB CDIE CDIF Read Interrupt

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-3 Figure 11-3. RT_L Interrupt

11.4 RING DETECTOR

The ring detect circuit validates the input ring signal (RD2) and the ring detect output is available in a read-only register (RD) in Control/Status Register 2 (CLCSR2). It can also be overwritten by writing to RDO (Ring Detect Override) in the Control/Status Register 1(CLCSR1) when enabled by writing a ‘1’ to RDOE (Ring Detect Override Enable) in the CLCSR3 register. A valid ring signal can also produce an interrupt to the CPU when enabled by the RDIE bit in CLCSR1. See Figure 11-4. Ring Detect Interface VDD External Pull-up RT_L Interrupt External Cap 0.02mF typical 270kW typical RDI1 RT_L Ring Detect RDO RDOE RD DB RDIE RDIF Read Interrupt

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-4 REV 2.0

11.5 POWER MANAGEMENT

If the Ring Detect module is used, it should be enabled by setting the RDPW bit before executing the STOP instruction. When the RT signal is below the threshold (see Figure 11-9) the oscillator circuit is forced on and the Ring Signal is validated. If the RT rises above the threshold before the Ring Signal is validated the oscillator will stop and the MCU will stay in the STOP mode. However, if a valid ring is detected an interrupt is generated provided the Ring Detect Interrupt Enable bit (RDIE) is set. The interrupt will wake the MCU from the STOP mode and the clocks to all enabled modules will start. At this time if the CPU is not required the WAIT mode can be entered. If the Carrier Detect module is enabled before entering the wait mode by CDPW bit, it will start processing the incoming data. When a valid carrier is detected an interrupt is generated if enabled by the CDIE bit. The interrupt will take the CPU out of the WAIT mode. Figure 11-5. Power Up Sequence from STOP Mode CPU STOP MODE RDPW? POWER ON RDIE? RD INTERRUPT/ YE S YE S CPU WAIT MODE CDPW? POWER ON CDIE? CD INTERRUPT YE S YE S WAKE UP CPU VALID YE S NO NO RING DETECT START PLL CLOCK NO NO NO RT? CARRIER DETECT

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-5 Figure 11-6. Power Up Sequence from WAIT Mode

11.6 DATA INTERFACE

The demodulated data from this module is available in bit-serial and 8-bit format. The serial data can be read from CIDSD (bit 2) of the CLCSR2 register and the 8- bit data is available from the Caller_ID data register CDDR. This data includes the alternate 0 and 1 pattern, 150 ms marking which precedes data. At all other times the demodulator output bit is high. The Caller_ID data ready flag CDRF bit-2 of CLCSR3 will be set to indicate that the 8-bit data is ready to be read. The data ready flag will generate an CPU interrupt if the data ready interrupt enable DRIE bit-3 of CLCSR3 is set and the I- bit of the CCR is cleared. The Caller_ID data register CDDR acts as data buffer for the serial to parallel data conversion register and should be read by the CPU within 8.3msec after receiving the interrupt. Failure to do so will result data lost. Reading the Caller_ID data register CDDR clears the Caller_ID data ready flag. Figure 11-9 shows the timing diagram for the serial to parallel data conversion. CPU WAIT MODE CDPW? POWER ON CDIE? CD INTERRUPT YE S YE S WAKE UP CPU NO NO CARRIER DETECT

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-6 REV 2.0 Figure 11-7. 8-bit Caller ID Data Timing Diagram

11.7 CALLER-ID REGISTERS

11.7.1 Control/Status Register1 (CLCSR1)

CDO, BIT0 Carrier Detect Override, when enabled by the CDOE bit in the CLCSR3 register, the carrier detect can be forced by writing a zero to this bit. On reset this bit is set to one. RDO, BIT1 Ring Detect Override, when enabled by RDOE in the CLCSR3 register, the ring detect can be forced by writing a zero to this bit. On reset this bit is set to one. CDIE, Bit4 (Carrier Detect Interrupt Enable) When set enables the carrier detect interrupt to be generated when a carrier is detected or forced by writing to CDO. 76543210 CLCSR1 $000A READ RDIF RDIE CDIF CDIE RDO CDO WRITE 0 0 RESET 0000U U11 Stop-bit = ‘1’ 8-bit word 8-bit word 8-bit word Bit-Serial Cooked Data Start-bit Stop-bit Stop-bitStart-bit Start-bit Stop-bit CDRF RDRF Cleared by CPU reading CDDR RDRF Cleared by CPU reading CDDR Mark-bits (0-10 bits) Mark-bits (0-10 bits) Mark-bit = ‘1’ Start-bit = ‘0’

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-7 CDIF , BIT5 (Carrier Detect Interrupt Flag) Provided the carrier detect interrupt is enabled by setting the CDIE, this bit is set when the carrier is detected. When this flag is one an interrupt is generated. This bit shares the interrupt vector address with Ring Detect interrupt. The CDIF bit must be cleared by writing a zero. RDIE, Bit6 (Ring Detect Interrupt Enable) When set enables the ring detect interrupt to be generated when a ring is detected or forced by writing to RDO. RDIF , BIT7 (Ring Detect Interrupt Flag) Provided the ring detect interrupt is enabled by setting the RDIE, this bit is set when the ring is detected. When this flag is one an interrupt is generated. This bit shares the interrupt vector address with Carrier Detect interrupt. The RDIF bit must be cleared by writing a zero.

11.7.2 Control/Status Register 2 (CLCSR2)

, Bit0 (Carrier Detect) This read only bit returns the value of the Carrier Detect signal which goes low when a valid carrier is detected and remains low while the carrier remains valid. RD , Bit1 (Ring Detect) This read only bit returns the value of the Ring Detect signal which goes low when a valid ringing signal is detected and remains low as long as the ringing signal remains valid. CIDSD, Bit2 (Caller ID Serial Data) This read only bit returns the value of the Caller ID Serial Data (output of the on chip demodulator) whenever the CD is low. This data includes the alternate 0 and 1 pattern, 150 ms marking which precedes the data. At all other times the demodulator output is high. CDPW, Bit5 (Carrier Detect Power Up) This bit when set is used to enable carrier detection. An interrupt will be generated when a valid carrier is detected and if the CDIE bit in the CLCSR1 register is set. 76543210 CLCSR2 $000B READ RDPW CDPW CIDSD RD CD WRITE RESET U 0 0 U U U 1 1 U = UNAFFECTED

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-8 REV 2.0 RDPW, Bit6 (Ring Detect Power Up) This bit when set is used to enable ring detection. An interrupt will be generated when a valid ring is detected and if the RDIE bit in the CLCSR1 register is set.

11.7.3 Control/Status Register 3 (CLCSR3)

CDOE, Bit-0 Carrier Detect Override Enable, when set this bit disables the carrier detect module output and allows the user to force the carrier detect signal by writing a zero to CDO, bit 0 in the CLCSR1 register. RDOE, Bit-1 Ring Detect Override Enable, when set this bit disables the ring detect module output and allows the user to force the ring detect signal by writing a zero to RDO, bit 1 in the CLCSR1 register. CDRF , Bit-2 Caller_ID data ready flag. This is set to ‘1’ when the 8-bit data is ready to be read. Reading CDDR ($000E) clears this bit. DRIE, Bit-3 (Data Ready Interrupt Enable) 1 = Enable CDRF to cause an interrupt. 0 = Disable CDRF from generating an interrupt. CDRE, Bit-4 (Caller_ID Receiver Enable) 1 = Enable Caller_ID 8-bit data receiver. 0 = Disable Caller_ID 8-bit data receiver. SDSL, Bit-7 (Serial Data Select) 0 = Select cooked data to be routed to the Caller ID parallel data receiver. 1 = Select raw data to be routed to the Caller ID parallel data receiver. 76543210 CLCSR3 $000C READ SDSL CDRE DRIE CDRF RDOE CDOE WRITE RESET 0 U U U 0000 U = UNAFFECTED

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-9

11.7.4 Caller_ID Data Register (CDDR)

CDDR[7:0] is the Caller ID data in byte format.

11.8 DESIGN PARAMETERS

The data signalling interface conforms to the recommended operating ranges of the physical layer test parameters for TYPE 1 CPE as described in Bellcore Publication SR-NWT -003004. 76543210 CDDR $000E READ CDD7 CDD6 CDD5 CDD4 CDD3 CDD2 CDD1 CDD0 WRITE RESET UUUU 0000 U = UNAFFECTED Table 11-1. Typical Input parameter Parameters Operating Range Units Mark Frequency 1188 ~ 1212 Hz Space Frequency 2178 ~ 2222 Hz Mark Level (600 ohm) -12 ~ -32 dBm Space Level (600 ohm) -12 ~ -36 dBm Carrier Frequency 1700 Hz Twist Immunity (600 ohm) +/- 10 dBm Baud Rate 1188 ~ 1212 baud Ringing Frequency 10 to 55 Hz Noise Immunity (Signal to Noise Ratio) -20 (for noise below 200 and above 3200 Hz) 25 (for noise between 200 and

3200 Hz)

Channel Seizure Delay 250 ~ 3600 ms Input Impedance 500 k W Immunity to CS and MS 10 ms

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-10 REV 2.0 The transmission level from the terminating C.O will be -13.5 dBm +/- 1.0. The expected worst case attenuation through the loop is expected to be -20dB. The receiver therefore, should have a sensitivity of approximately -34.5 dB to handle the worst case installations. Table 11-2. Critical Design Characteristic Characteristics Typ Unit Input Tip/Ring Sensitivity (600 ohm) -40 dBm Ring/Tip Common Mode Rejection Ratio 60 dB Bandpass Filter (BPF) Frequency Response (relative to 1700 Hz @ 0 dB) 60 Hz 1000 Hz 2400 Hz >=3300 Hz -58 -34 dB Carrier Detect Sensitivity (600 ohm) -40 (-48 min) dBm Ring Detect Threshold (RDI2) 0.39*Vdd – 0.1volt Volts RDI Threshold to keep RT_L=’1’ < 1.0 Volts Table 11-3. Switching Characteristics (VDD= 5V; TA=25 C) Description Symbol Min Typ Max Unit PLL Clock Start-up Time t DOSC - - 10 ms Carrier Detect Acquisition t DAQ -1 4 2 5m s End of Carrier Detect t DCH 8--m s

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 CALLER-ID MOTOROLA REV 2.0 11-11

11.9 MESSAGE FORMAT

Figure 11-8. Single Message Format Figure 11-9. CLID Timing Diagram 0101 1 DATA

2 Sec 4 Sec 2 Sec

.5 Sec .5 Sec Channel Seizure Mark Message Message Message Chk sum Signal Type Word Length Word Word(s) Word Mark bits (0-10) 0101 1 DATA .5 Sec .5 SecData Word Ring Input Ring Detect Ring Detect Interrupt Flag Flag cleared by SW Carrier Detect Carrier Detect Interrupt Flag Flag cleared by SW Demodulated Serial Data Ring Time

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA CALLER-ID MC68HC05CL48 11-12 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LCD DRIVER MOTOROLA REV 2.0 12-1 SECTION 12 LCD DRIVER The LCD driver module supports a 45 frontplanes by 16 backplanes or a 53 frontplanes by 8 backplanes display. This allows a maximum of 720 LCD segments to be driven. Each segment is controlled by a corresponding bit in the LCD RAM. On reset or on power-up, the drivers are disabled via a Display on (DISON) bit in the LCD Control (LCDCTR) register. Figure 12-1 shows a block diagram of the LCD subsystem. Figure 12-1. LCD Driver Block Diagram Internal signals BP[0:7] Display RAM LCD data latch FP[0:44] Internal Data bus Internal Address bus Voltage Generator 45X16 Segment driver BP[8:15]/ FP[45:52] VLCD Control Logic Backplane Driver

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LCD DRIVER MC68HC05CL48 12-2 REV 2.0 12.1 LCD RAM. The data to be displayed by the LCD is written to a 90 byte display RAM located at locations $0930 thru $095C and $0A30 thru $0A5C in the memory map. The bits are organized according to Table 12-1 and Table 12-2, with a 1 stored in a given location resulting in the corresponding display segment being activated. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. When the display is disabled, the LCD RAM can be used as on-chip RAM. Table 12-1. LCD RAM Organization ADDR DATA 0 1 234567 $0930 FP0-BP0 FP0-BP1 FP0-BP2 FP0-BP3 FP0-BP4 FP0-BP5 FP0-BP6 FP0-BP7 $0931 FP1-BP0 FP1-BP1 FP1-BP2 FP1-BP3 FP1-BP4 FP1-BP5 FP1-BP6 FP1-BP7 $0932 FP2-BP0 FP2-BP1 FP2-BP2 FP2-BP3 FP2-BP4 FP2-BP5 FP2-BP6 FP2-BP7 $095A FP42-BP0 FP42-BP1 FP42-BP2 FP42-BP3 FP42-BP4 FP42-BP5 FP42-BP6 FP42-BP7 $095B FP43-BP0 FP43-BP1 FP43-BP2 FP43-BP3 FP43-BP4 FP43-BP5 FP43-BP6 FP43-BP7 $095C FP44-BP0 FP44-BP1 FP44-BP2 FP44-BP3 FP44-BP4 FP44-BP5 FP44-BP6 FP44-BP7

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LCD DRIVER MOTOROLA REV 2.0 12-3 Table 12-2. LCD RAM Organization ADDR DATA 0 1 234567 $0A30 FP0-BP8 FP0-BP9 FP0-BP10 FP0-BP11 FP0-BP12 FP0-BP13 FP0-BP14 FP0-BP15 FP45-BP0 FP45-BP1 FP45-BP2 FP45-BP3 FP45-BP4 FP45-BP5 FP45-BP6 FP45-BP7 $0A31 FP1-BP8 FP1-BP9 FP1-BP10 FP1-BP11 FP1-BP12 FP1-BP13 FP1-BP14 FP1-BP15 FP46-BP0 FP46-BP1 FP46-BP2 FP46-BP3 FP46-BP4 FP46-BP5 FP46-BP6 FP46-BP7 $0A32 FP2-BP8 FP2-BP9 FP2-BP10 FP2-BP11 FP2-BP12 FP2-BP13 FP2-BP14 FP2-BP15 FP47-BP0 FP47-BP1 FP47-BP2 FP47-BP3 FP47-BP4 FP47-BP5 FP47-BP6 FP47-BP7 $0A33 FP3-BP8 FP3-BP9 FP3-BP10 FP3-BP11 FP3-BP12 FP3-BP13 FP3-BP14 FP3-BP15 FP48-BP0 FP48-BP1 FP48-BP2 FP48-BP3 FP48-BP4 FP48-BP5 FP48-BP6 FP48-BP7 $0A34 FP4-BP8 FP4-BP9 FP4-BP10 FP4-BP11 FP4-BP12 FP4-BP13 FP4-BP14 FP4-BP15 FP49-BP0 FP49-BP1 FP49-BP2 FP49-BP3 FP49-BP4 FP49-BP5 FP49-BP6 FP49-BP7 $0A35 FP5-BP8 FP5-BP9 FP5-BP10 FP5-BP11 FP5-BP12 FP5-BP13 FP5-BP14 FP5-BP15 FP50-BP0 FP50-BP1 FP50-BP2 FP50-BP3 FP50-BP4 FP50-BP5 FP50-BP6 FP50-BP7 $0A36 FP6-BP8 FP6-BP9 FP6-BP10 FP6-BP11 FP6-BP12 FP6-BP13 FP6-BP14 FP6-BP15 FP51-BP0 FP51-BP1 FP51-BP2 FP51-BP3 FP51-BP4 FP51-BP5 FP51-BP6 FP51-BP7 $0A37 FP7-BP8 FP7-BP9 FP7-BP10 FP7-BP11 FP7-BP12 FP7-BP13 FP7-BP14 FP7-BP15 FP52-BP0 FP52-BP1 FP52-BP2 FP52-BP3 FP52-BP4 FP52-BP5 FP52-BP6 FP52-BP7 $0A38 FP8-BP8 FP8-BP9 FP8-BP10 FP8-BP11 FP8-BP12 FP8-BP13 FP8-BP14 FP8-BP15 $0A39 FP9-BP8 FP9-BP9 FP9-BP10 FP9-BP11 FP9-BP12 FP9-BP13 FP9-BP14 FP9-BP15 $0A5A FP42-BP8 FP42-BP9 FP42-BP10 FP42-BP11 FP42-BP12 FP42-BP13 FP42-BP14 FP42-BP15 $0A5B FP43-BP8 FP43-BP9 FP43-BP10 FP43-BP11 FP43-BP12 FP43-BP13 FP43-BP14 FP43-BP15 $0A5C FP44-BP8 FP44-BP9 FP44-BP10 FP44-BP11 FP44-BP12 FP44-BP13 FP44-BP14 FP44-BP15

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LCD DRIVER MC68HC05CL48 12-4 REV 2.0

12.2 LCD OPERATION

Figure 12-2 shows the backplane waveforms and some examples of frontplane waveforms which are dependent on the LCD segments to be driven as defined in the LCD RAM. Each “on” segment must have a differential driving voltage (BP-FP) applied to it once in each frame; the LCD driver module hardware uses the data in the LCD RAM to construct the frontplane waveform to meet this criterion. The backplane waveforms are continuous and repetitive (every 2 frames); they are fixed and not affected by the data in the LCD RAM. During WAIT mode the LCD drivers function as normal and will keep the display active if the DISON bit (bit0 of $07) is set. The LCD drivers can be configured to operate with either 16 backplanes or 8 backplanes under software control. The bias ratio can be set 1:4 or 1/5 under software control for both a 8 and 16 backplane LCD. The voltage levels required are generated internally by a resistive divider between VLCD and VSS.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LCD DRIVER MOTOROLA REV 2.0 12-5 Figure 12-2. LCD 5:1 bias waveforms Frame One Vlcd BP0 BP1 BP2 BP7 FP X FP Y FP Z Vlcd Vlcd Vlcd Vlcd Vlcd Vlcd

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LCD DRIVER MC68HC05CL48 12-6 REV 2.0 Figure 12-3. LCD 4:1 bias waveforms Frame One Vlcd BP0 BP1 BP2 BP7 FP X FP Y FP Z Vlcd Vlcd Vlcd Vlcd Vlcd Vlcd

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LCD DRIVER MOTOROLA REV 2.0 12-7

12.3 LCD VOLTAGE GENERATION

Figure 12-4 shows the resistive divider chain network that is used to produce the various LCD waveforms outlined in the previous section. The LCD system can be disabled by setting the DISON bit to 0. The voltage levels of the LCD driver waveforms and hence the contrast of the LCD can be altered by selecting appropriate resistors by setting the corresponding values to the CC0 to CC3 bits in the LCDCTR register. Figure 12-4. Voltage Generator DISON RL4 RL3 RL2 VLCD CC1 CC2 CC3 RC1 RC2 RC3 RL5 RL1 External Caps BIAS5 CC0 RC0

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LCD DRIVER MC68HC05CL48 12-8 REV 2.0

12.4 LCD CONTROL REGISTER (LCDCR)

1 = The Display is on when this bit is ’1’ and 0 = off when this bit is ’0’. Setting this bit to ’0’ also disconnects the voltage generator resistor chain from VSS, thus reducing power. BIAS5 - Bits 2 1 = Select 5:1 bias voltage levels. 0 = Select 4:1 bias voltage levels. MX8 - bit 3 1 = the system operates with 53 frontplanes and 8 backplanes, 0 = the system operates with 45 frontplanes and 16 backplanes. CC0 - CC3 - bits 4,5,6,7 These bits can be used to select the values of the contrast control resistors. 1 = the corresponding resistor will be shorted. On reset these bits are set to 1. Table 12-3. LCD Voltage Characteristic VLCD=5.0volts 4:1 bias Voltage (volts) Typical Values 5:1 bias Voltage (volts)] Typical Values V5 5.0 5.0 V4 3.75 4.0 V3 2.5 3.0 V2 2.5 2.0 V1 1.25 1.0 V0 0.0 0.0 76543210 LCDCR $0007 READ CC3 CC2 CC1 CC0 MX8 BIAS5 DISON WRITE RESET 111100-0 U = UNAFFECTED

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LCD DRIVER MOTOROLA REV 2.0 12-9

12.5 ELECTRICAL REQUIREMENTS

The contrast network will be monotonic under the normal operating conditions. Note: Both ladder resistors and the contrast resistors are implemented using poly resistor to minimize process and temperature variation.

12.5.1 DC Requirements

The DC voltage between Front-plane to Back-plane will be less than 50mV, average over one frame. For VLCD = 3 to 5 volts and temperature range of –10°C to 70°C . Table 12-4. Ladder Voltage Values VLCD=5.0 volts 4:1 Bias V5-V4 1.25 – 4% V4-V3 1.25 – 4% V3-V2 0 – 4% V2-V1 1.25 – 4% V1-V0 1.25 – 4% Table 12-5. Contrast Resistor Values Resistor Resistor Values (ohm) +/- 25% RC0 10k RC1 20k RC2 40k RC3 80k R1 100k R2 100k R3 100k R4 100k R5 100k

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA LCD DRIVER MC68HC05CL48 12-10 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 PHASE-LOCKED LOOP MOTOROLA REV 2.0 13-1 SECTION 13 PHASE-LOCKED LOOP System clock can be obtained either from the external 32kHz oscillator or from the PLL. During power on or external reset, the system is defaulted to use the 32 kHz clock from the external oscillator. This is to prevent the system from using otherwise, an unstable clock from the PLL during reset. To use the PLL clock after power on or external reset, the PON-bit should be set ‘1’ first to switch the PLL on, a minimum of 10msec should then be allowed for the PLL clock to stabilize before setting the PCLK-bit to ‘1’ to switch to use the PLL clock. Power on or external reset clears the PCLK-bit. Four clocks at different frequencies are available to the system from the PLL using the frequency select bits FREQ0 and FREQ1 of the PCSR, see Table 13-1. The PLL can be powered down to save power by setting the PON-bit to ‘0’. When the PLL is powered up after it has been powered down, again the system should allow a minimum of 10msec before switching onto the PLL clock. The PLL when it is powered up, will also provide the 1.8MHz clock for the Caller ID module. Before switching the PLL off, the PCLK-bit must be cleared thus selecting the 32kHz crystal clock as the system clock. A minimum of 2*OSC cycles should be allowed for the system to switch from the PLL clock to the oscillator clock. Table 13-1. System Clock Frequency Selection FREQ1 FREQ0 System Clock 0 0 3.6MHz 0 1 1.8MHz 1 0 900kHz 1 1 450kHz

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA PHASE-LOCKED LOOP MC68HC05CL48 13-2 REV 2.0

13.1 PLL CONTROL AND STATUS REGISTER (PCSR $000D)

PON - PLL power on/off bit. 1 = PLL is switched on. 0 = PLL is switched off. PCLK - PLL Clock select bit. 1 = Use PLL clock. 0 = Use external clock. FREQ1 - Frequency select bit 1. FREQ0 - Frequency select bit 0.

13.2 PLL OPERATIONS

The PLL consists of an on chip VCO, a phase comparator and a divider. A filter is required to filter the phase comparator output to provide a DC signal to control the VCO frequency Figure 13-1.

13.3 PLL LOCK TIME

The PLL will lock in less than 10msec after the PON-bit is set. The PCLK should not be set before the PLL is locked.

13.4 PLL CLOCK FREQUENCY

When the PLL is in lock, the VCO output frequency is given by: The VCO output frequency is further divided by a frequency divider circuit to give three other frequencies as shown in Figure 13-1. 7 6 5 4 3 2 1 0 PCSR $000D READ PON PCLK FREQ1 FREQ0 WRITE RESET 0 0 X X X 0 0 X Fvco = 114 * Fosc where Fosc = oscillator frequency Example: Fosc = 32.768kHz, Fvco = 3.604MHz.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA PHASE-LOCKED LOOP MC68HC05CL48 13-4 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-1 SECTION 14 INSTRUCTION SET This section describes the addressing modes and instruction types.

14.1 ADDRESSING MODES

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, No Offset
• Indexed, 8-Bit Offset
• Indexed, 16-Bit Offset
• Relative

14.1.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inher- ent instructions require no memory address and are one byte long.

14.1.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

14.1.3 Direct

Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-2 REV 2.0

14.1.4 Extended

Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.

14.1.5 Indexed, No Offset

Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU auto- matically uses $00 as the high byte, so these instructions can address locations $0000–$00FF . Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

14.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory loca- tions and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte fol- lowing the opcode.

14.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-3

14.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte follow- ing the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s com- plement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

14.1.9 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-4 REV 2.0 14.1.10Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accu- mulator or the index register. The CPU finds the other operand in memory. Table 14-1 lists the register/memory instructions. Table 14-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-5 14.1.11Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 14-2 lists the read-modify-write instructions. 14.1.12Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any read- able bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested Table 14-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left ASL Arithmetic Shift Right ASR Clear Bit in Memory BCLR Set Bit in Memory BSET Clear CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-6 REV 2.0 and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 14-3 lists the jump and branch instructions. Table 14-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-7 14.1.13Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 14-4 lists these instructions. 14.1.14Control Instructions These register reference instructions control CPU operation during program exe- cution. Control instructions, listed in Table 14-5, use inherent addressing. Table 14-4. Bit Manipulation Instructions Instruction Mnemonic Clear Bit BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Set Bit BSET Table 14-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and Enable IRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-8 REV 2.0 14.1.15Instruction Set Summary Table 14-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 14-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ‹ (A) + (M) + (C) à — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ‹ (A) + (M) à — ààà IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X Logical AND A ‹ (A) Ù (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left (Same as LSL) —— ààà DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ààà DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ‹ 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ‹ (PC) + 2 + rel ? Z = 1 ————— R E L 2 7 r r 3 BHCC rel Branch if Half-Carry Bit Clear PC ‹ (PC) + 2 + rel ? H = 0 ————— R E L 2 8 r r 3 C b0b7 b0b7 C

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-9 BHCS rel Branch if Half-Carry Bit Set PC ‹ (PC) + 2 + rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ‹ (PC) + 2 + rel ? C Ú Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch if IRQ Pin High PC ‹ (PC) + 2 + rel ? IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ‹ (PC) + 2 + rel ? IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte (A) Ù (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff p BLO rel Branch if Lower (Same as BCS) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch if Lower or Same PC ‹ (PC) + 2 + rel ? C Ú Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ‹ (PC) + 2 + rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ‹ (PC) + 2 + rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ‹ (PC) + 2 + rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ‹ (PC) + 2 + rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ‹ (PC) + 2 + rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ‹ (PC) + 2 + rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if bit n clear PC ‹ (PC) + 2 + rel ? M n = 0 ———— à DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRSET n opr relBranch if Bit n Set PC ‹ (PC) + 2 + rel ? M n = 1 ———— à DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ‹ (PC) + 2 + rel ? 1 = 0 ————— R E L 2 1 r r 3 Table 14-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-10 REV 2.0 BSET n opr Set Bit n Mn ‹ 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ‹ (PC) + 2; push (PCL) SP ‹ (SP) – 1; push (PCH) SP ‹ (SP) – 1 PC ‹ (PC) + rel CLC Clear Carry Bit C ‹ 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ‹ 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ‹ $00 A ‹ $00 X ‹ $00 M ‹ $00 M ‹ $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte (A) – (M) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) —— àà 1 DIR INH INH IX1 IX dd ff CPX # opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte (X) – (M) — — àà 1 IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ‹ (M) – 1 A ‹ (A) – 1 X ‹ (X) – 1 M ‹ (M) – 1 M ‹ (M) – 1 —— àà — DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 14-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC M A X M M

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-11 INC opr INCA INCX INC opr,X INC ,X Increment Byte M ‹ (M) + 1 A ‹ (A) + 1 X ‹ (X) + 1 M ‹ (M) + 1 M ‹ (M) + 1 —— àà — DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ‹ Jump Address ————— DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ‹ (PC) + n (n = 1, 2, or 3) Push (PCL); SP ‹ (SP) – 1 Push (PCH); SP ‹ (SP) – 1 PC ‹ Conditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA # opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ‹ (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX # opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ‹ (M) — — àà — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left (Same as ASL) —— ààà DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 àà DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ‹ (X) · (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) —— ààà DIR INH INH IX1 IX ii ff NOP No Operation ————— I N H 9 D 2 Table 14-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-12 REV 2.0 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory A ‹ (A) Ú (M) — — àà — IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit —— ààà DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit —— ààà DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ‹ $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ‹ (SP) + 1; Pull (CCR) SP ‹ (SP) + 1; Pull (A) SP ‹ (SP) + 1; Pull (X) SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL) ààààà INH 80 6 RTS Return from Subroutine SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL) INH SBC # opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator A ‹ (A) – (M) – (C) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ‹ 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ‹ 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory M ‹ (A) — — àà — DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ‹ (X) — — àà — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff Table 14-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7 C

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INSTRUCTION SET MOTOROLA REV 2.0 14-13 SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator A ‹ (A) – (M) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ‹ (PC) + 1; Push (PCL) SP ‹ (SP) – 1; Push (PCH) SP ‹ (SP) – 1; Push (X) SP ‹ (SP) – 1; Push (A) SP ‹ (SP) – 1; Push (CCR) SP ‹ (SP) – 1; I ‹ 1 PCH ‹ Interrupt Vector High Byte PCL ‹ Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 ————— DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts — à — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask Ù Logical AND ii Immediate operand byte Ú Logical OR IMM Immediate addressing mode ¯ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ‹ Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag × Set or cleared n Any bit — Not affected Table 14-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC

MOTOROLAINSTRUCTION SETMC68HC05CL48 14-14REV 2.0 Table 14-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX 0123456789AB C D EF BRSET0

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 ELECTRICAL SPECIFICATIONS MOTOROLA REV 2.0 15-1 SECTION 15 ELECTRICAL SPECIFICATIONS

15.1 MAXIMUM RATINGS

(Voltages referenced to VSS ) NOTE Maximum current drain per pin is for one pin at a time, limited by an external resistor. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that V IN and VOUT be constrained to the range VSS £ (VIN or VOUT ) £ VDD . Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either V SS or VDD ).

15.2 THERMAL CHARACTERISTICS

Supply Voltage V DD –0.3 to +7.0 V LCD Supply Voltage V LCD VDD to +6.0 V Input Voltage V IN VSS – 0.3 to VDD + 0.3 V Self-Check Mode (IRQ/IRQ Pin only) V IN VSS – 0.3 to 2xVDD +0.3 V Current Drain per pin excluding VDD and VSS I2 5 m A Operating Temperature Range T A –10 to 70 °C Storage Temperature Range T STG –65 to 150 °C Rating Symbol Value Unit Thermal resistance (Plastic) qJA 60 °C/W

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05CL48 15-2 REV 2.0

15.3 DC ELECTRICAL CHARACTERISTICS

(VDD = 3.3 VDC –10%, VSS = 0 VDC , TA =–10°C to +70 °C, unless otherwise noted) Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25°C only. (3) Wait IDD : Only timer system active. (4) Run (Operating) IDD , Wait IDD : Measured with all inputs 0.2 V from rail; no D.C. loads, less than 50pF on all outputs, CL = 20 pF on OSC2. (5) Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V. (6) Stop IDD measured with OSC1 = VSS . (7) Wait IDD is affected linearly by the OSC2 capacitance. CHARACTERISTICS Symbol Min Typ Max Unit Output Voltage ILOAD = –10mA ILOAD = 10mA VOL VOH VDD –0.1 0.1 V V Output High Voltage ILOAD = 0.8mA PTA0-7,PTB0-7, PTC0-7 VOH VDD –0.8 — — V Output Low Voltage ILOAD = 1.6mA PTA0-7, PTB0-7,PTC0-7 VOL — — 0.4 V Input High Voltage PTA0-7,PTB0-7,PTC0-7,RESET, IRQ, OSC1, V IH 0.8xVDD —V DD V Input Low Voltage PTA0-7, PTB0-7, PTC0-7,RESET, IRQ, OSC1, TCAP1,TCAP2 VIL VSS — 0.2xV DD V Output Sink Current (from 5V) PTA0-7,PTB0-7, PTC0-7 I SINK — — 3.0 mA Output Source Current (into 2.5V) PTA0-7,PTB0-7, PTC0-7 I SINK — 3.0 — mA I/O Ports High-Z leakage PTA0-7,PTB0-7,PTC0-7 Measured with input at (V DD - 0.1) volts and (VSS + 0.1) volts. IOZ —— –100 nA Input Current RESET , IRQ, IRQ0, IRQ1, IRQ2, OSC1, TCAP1 TCAP2 IOZ —— –10 mA Capacitance All input or output. C IN C OUT —— pF pF

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 ELECTRICAL SPECIFICATIONS MOTOROLA REV 2.0 15-3

15.4 POWER DISSIPATION

(VDD = 3.3Vdc, VSS = 0 Vdc, TA =–10°C to +70 °C, unless otherwise noted) Mode Conditions Symbol Max (HC705CL48) Max (HC05CL48) Unit RUNNING (a) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active LCD = active ATD = active SPI = active CLID = active I DD 6.34 6.5 mA RUNNING (b) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active LCD = active I DD 3.82 2.8 mA RUNNING (c) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active ATD = active LCD = active I DD 4.13 3.0 mA WAIT (d) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active ATD = active LCD = active I DD 2.67 1.0 mA RUNNING (e) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active ATD = active CLID = active LCD = active I DD 6.36 6.5 mA WAIT (f) System Clock = 3.6MHz PLL = active Core Timer = active WTimer = active ATD = active CLID = active LCD = active I DD 4.90 2.5 mA STOP (g) System Clock = 32kHz LCD = active WTimer = active IDD 80 80 mA STOP (h) No Oscillator All modules switched off. IDD 77 mA

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05CL48 15-4 REV 2.0 Note: The above IDD measurements include the 32kHz oscillator IDD configured as in Figure 1-4 (a) except for case (h) and (i).

15.5 CONTROL TIMING

(VDD = 3.3 VDC –10%, VSS = 0 VDC , TA = –10°C to +70°C, unless otherwise noted) Notes: (1) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC .

15.6 ESD PROTECTION

All pads are designed to withstand 2kV of ESD. Data Retention (i) VDD =2.0, RESETB = “0” No Oscillator IDD 55 mA Start Up (j) VDD = 0 to 3V, RESETB = “0” I DD 3.0 3.0 mA CHARACTERISTIC Symbol Min Max Unit Frequency of operation Crystal option External clock f OSC fIN 32.768 32.768 kHz MHz Internal operating frequency Crystal option External clock f OP fOP 0.016384 1.802 MHz MHz Cycle time t CYC 61035 555 ns Crystal Oscillator Start-up time. (Refer to Figure 1-4 (a)) “From supply=Vdd to the end of POR cycles.” tOXOV —3 s Crystal Oscillator Start-up Voltage t OXOV 2.7 5.0 Volts Crystal Oscillator Small Signal Voltage Gain A V 10 25 Stop recovery Start-up time (crystal oscillator + POR cycles) tILCH —7 0 m s PLL lock time (after asserting PON-bit) t PLL —1 0 m s RESET pulse width t RL 1.5 I OUT tCYC Interrupt pulse width (Edge triggered) t ILIH 119 I IN ns Interrupt pulse period t ILIL See note1 — t CYC OSC1 Pulse Width t 270 280 ns Mode Conditions Symbol Max (HC705CL48) Max (HC05CL48) Unit

June 10, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MECHANICAL SPECIFICATIONS MOTOROLA REV 2.0 16-1 SECTION 16 MECHANICAL SPECIFICATIONS This section outlines the mechanical dimensions of the 112-pin TQFP and 100-pin TQFP packages.

GENERAL RELEASE SPECIFICATION June 10, 1997 MOTOROLA MECHANICAL SPECIFICATIONS MC68HC05CL48 16-2 REV 2.0 16.1 112-PIN THIN-QUAD-FLAT-PACKAGE (CASE 987-01) Figure 16-1. 112-Pin TQFP Mechanical Dimensions ÇÇÇ Ç Ç Ç ÇÇÇ ÉÉÉ É É É ÉÉÉ DIM A MIN MAX

20.000 BSC

A1 10.000 BSC B 20.000 BSC B1 10.000 BSC C ––– 1.600 C1 0.050 0.150 C2 1.350 1.450 D 0.270 0.370 E 0.450 0.750 F 0.270 0.330 G 0.650 BSC J 0.090 0.170 K 0.500 REF P 0.325 BSC R1 0.100 0.200 R2 0.100 0.200 S 22.000 BSC S1 11.000 BSC V 22.000 BSC V1 11.000 BSC Y 0.250 REF Z 1.000 REF AA 0.090 0.160 /C0113 /C0113 /C0113 /C0113 NOTES: 1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. VIEW Y L–M0.20 NT4X 4X 28 TIPS PIN 1 IDENT 112 85 28 57 29 56 B V V1B1 A S VIEW AB 0.10 C /C0113 2/C01130.050 SEATING PLANE GAGE PLANE 1/C0113 /C0113 VIEW AB (Z) (Y) E (K) R1 0.25 VIEW Y P G108X SECTION J1–J1 BASE ROTATED 90 COUNTERCLOCKWISE/C0095 METAL J AA F D L–MM0.13 N T CL L–M0.20 NT L N M T T 112X X X=L, M OR N R R

June 10, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MECHANICAL SPECIFICATIONS MOTOROLA REV 2.0 16-3 16.2 100-PIN THIN-QUAD-FLAT-PACKAGE (CASE 983-02) Figure 16-2. 100-Pin TQFP Mechanical Dimensions DIM A MIN MAX

14.00 BSC

A1 7.00 BSC B 14.00 BSC B1 7.00 BSC C 1.70 C1 0.05 0.20 C2 1.30 1.50 D 0.10 0.30 E 0.45 0.75 F 0.15 0.23 G 0.50 BSC J 0.07 0.20 K 0.50 REF R1 0.08 0.20 S 16.00 BSC S1 8.00 BSC U 0.09 0.16 V 16.00 BSC V1 8.00 BSC W 0.20 REF Z 1.00 REF 0 7

12 REF

NOTES: 1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07. VIEW Y 4X 25 TIPS 100 76 26 50 VIEW AA C N0.2 T L –M 0.08 T (K) (Z) (W) GAGE PLANE VIEW AA VIEW Y AB PLATING UJ D F ROTATED 90 CLOCKWISE BASE METAL SECTION AB –AB 0.05 E 0.25 CL L–MM0.08 N T 34X 1 2X R R1 X = L, M OR N G A S B1 V1 B V ––– ––– N0.2 T L –M M N T SEATING 24X 100X PLANE X AB L

GENERAL RELEASE SPECIFICATION June 10, 1997 MOTOROLA MECHANICAL SPECIFICATIONS MC68HC05CL48 16-4 REV 2.0

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 A-1 APPENDIX A MC68HC705CL48 This appendix describes the differences between the MC68HC705CL48 and MC68HC05CL48. This part is for user system evaluation and debugging only, and is not recommended for mass production. A.1 INTRODUCTION The MC68HC705CL48 is an EPROM version of the MC68HC05CL48, and is available for user system evaluation and debugging only. The MC68HC705CL48 is functionally identical to the MC68HC05CL48 with the exception of the 47.5k- byte user ROM replaced by 47.5k-byte user EPROM and, the self-check routine is replaced by a bootstrap routine. A.2 MEMORY The MC68HC705CL48 memory map is shown in Figure A-1. A.3 BOOTLOADER MODE Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is at VTST and the PTB7 pin is at logic one. The Bootloader program and vectors are masked in the ROM area from $FE00 to $FFEF . This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass. The user code must be a one-to-one correspondence with the internal EPROM addresses.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 A-2 REV 2.0 Figure A-1. MC68HC705CL48 Memory Map Ctimer/WTimer $FFF0 $FFF1 IRQn/KBI $FFF2 $FFF3 Caller_ID $FFF4 $FFF5 SWI $FFFC $FFFD SPI $FFF6 $FFF7 Timer $FFF8 $FFF9 IRQ $FFFA $FFFB Reset $FFFE $FFFF I/O Register $0000 $002F RAM $00FF Not Used $0030 Stack $082F $3FFF EPROM 47.5k Bytes $4000 Bootstrap ROM $FFEF Bootstrap Vectors $FE00 User Vectors $FFF0 $FFFF $FFE0 $FFDF $00C0 Port A Data Register $00 Port B Data Register $01 $02 Port A Direction Register $03 Timer Pin Configuration Register $04 $05 $06 $07 Core Timer Control/Status Register$08 Core Timer Register $09 $0A $0B $0C $0D Caller ID Data Register $0E $0F $10 $11 Timer Status Register $12 $13Input Capture High Register 1 $14Input Capture Low Register 1 $15Output Compare High Register 1 $16Output Compare Low Register 1 $17 Counter High Register $18 Counter Low Register $19 Alternate Counter High Register $1A Alternate Counter Low Register $1B External Interrupt Control Register $1C External Interrupt Status Register $1D $1E Option Register $1F Not Used $095C Input Capture Low Register 2 Timer Control Register Output Compare Low Register 2 Output Compare High Register 2 Input Capture High Register 2 Caller ID Control/Status Register 2 Caller ID Control/Status Register 1 LCD Control Register Caller ID Control/Status Register 3 PLL Status/Data Register $FDFF $20 $21 $22 $23 $24 $25 $26 $2F $27 SPI Control Register SPI Status Register SPI Data Register Port C Data Register Port B Direction Register Port C Direction Register Watch Timer Control & Status Register A/D Control and Status Register A/D Data Register EPROM Program Control Register Reserved $0930 $0830 $0100 LCD RAM $0A5D $0A5C $0A30 Not Used $092F $095D $0A2F

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 A-3 A.4 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Register located at address $26. Please contact Motorola for programming board availability. A.4.1 EPROM Program Control Register (EPCR $26) This register is provided for programming the on-chip EPROM in the MC68HC705CL48. ELAT—EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit should not be set when no programming voltage is applied to the V pp pin. PGM—EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array. 1 = Programming power is switched ON to EPROM array. If ELAT „ 1, then PGM = 0. A.4.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time t PGMR 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes. EPCR $0026 bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 Read RESERVED ELAT PGM Write Reset 00000000

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 A-4 REV 2.0 CAUTION It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. Figure A-2 shows the flow required to successfully program the EPROM. Figure A-2. EPROM Programming Sequence START ELAT=1 Write EPROM byte EPGM=1 Wait 1ms EPGM=0 ELAT=0 Write additional byte? Y N END

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 B-1 APPENDIX B MC68HC05CL16 This appendix describes the differences between the MC68HC05CL16 and MC68HC05CL48. The entire MC68HC05CL48 data sheet applies to the MC68HC05CL16, with exceptions outlined in this appendix. B.1 INTRODUCTION The MC68HC05CL16 is functionally identical to the MC68HC05CL48, except the following: Figure B-1 shows a block diagram of the MC68HC05CL16. B.2 SIGNAL DESCRIPTION The LCD driver voltages from the resistor ladder, V0, V1, V2, V3, and V4 on the MC68HC05CL48 are not available on the MC68HC05CL16. B.3 MEMORY The MC68HC05CL16 has 16k-bytes of user ROM. The MC68HC05CL16 memory map is shown in Figure B-2. Table B-1. MC68HC05CL16 and MC68HC05CL48 Differences MC68HC05CL16 MC68HC05CL48 16k-bytes user ROM 47.5k-bytes user ROM — LCD driver output voltages: V0, V1, V2, V3, V4 100-pin TQFP 112-pin TQFP

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 B-2 REV 2.0 Figure B-1. MC68HC05CL16 Block Diagram 0 000000011 CPU CONTROL ARITHMETIC/LOGIC UNIT ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER M68HC05 MCU RESET CONDITION CODE REGISTER 111HI N C Z DATA DIRECTION REGISTER A PORT A PTA7/KB7 PTA6/KB6 PTA5/KB5 PTA4/KB4 PTA3/KB3 PTA2/IRQ2 PTA1/IRQ1 PTA0/IRQ0 COP INTERNAL OSCILLATOR DIVIDE BY TWO IRQ/VPP VDD VSS OSC1 OSC2 USER RAM — 2k BYTES RESET DATA DIRECTION REGISTER B PORT B PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 USER ROM — 16k BYTES TIMER TCAP2 TCAP1 WATCHDOG CPU CLOCK POWER INTERNAL CLOCK SPI PLL XFC CALLER ID RT_L RD1 RD2 A/D AD0 AD1 SS SCK MISO MOSI LCD DRIVER FP[44:0] BP[15:0] VLCD DATA DIRECTION REGISTER C PORT C PTC7/TCAP2 PTC6/TCAP1 PTC5/AD3 PTC4/AD2 PTC3/ SS PTC2/MOSI PTC1/MISO PTC0/SCK CONFIGURATION REGISTER C AD2 AD3 FSK– FSK+ WTIMER

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 B-3 Figure B-2. MC68HC05CL16 Memory Map Ctimer/WTimer $FFF0 $FFF1 IRQn/KBI $FFF2 $FFF3 Caller_ID $FFF4 $FFF5 SWI $FFFC $FFFD SPI $FFF6 $FFF7 Timer $FFF8 $FFF9 IRQ $FFFA $FFFB Reset $FFFE $FFFF I/O Register $0000 $002F RAM $00FF Not Used $0030 Stack $082F ROM 16k Bytes Self-check ROM $FFEF Self-check Vectors $FE00 User Vectors $FFF0 $FFFF $FFE0 $FFDF $00C0 Port A Data Register $00 Port B Data Register $01 $02 Port A Direction Register $03 Timer Pin Configuration Register $04 $05 $06 $07 Core Timer Control/Status Register$08 Core Timer Register $09 $0A $0B $0C $0D Caller ID Data Register $0E $0F $10 $11 Timer Status Register $12 $13Input Capture High Register 1 $14Input Capture Low Register 1 $15Output Compare High Register 1 $16Output Compare Low Register 1 $17 Counter High Register $18 Counter Low Register $19 Alternate Counter High Register $1A Alternate Counter Low Register $1B External Interrupt Control Register $1C External Interrupt Status Register $1D $1E Option Register $1F Not Used $095C Input Capture Low Register 2 Timer Control Register Output Compare Low Register 2 Output Compare High Register 2 Input Capture High Register 2 Caller ID Control/Status Register 2 Caller ID Control/Status Register 1 LCD Control Register Caller ID Control/Status Register 3 PLL Status/Data Register $FDFF $20 $21 $22 $23 $24 $25 $26 $2F $27 SPI Control Register SPI Status Register SPI Data Register Port C Data Register Port B Direction Register Port C Direction Register Watch Timer Control & Status Register A/D Control and Status Register A/D Data Register Reserved for EPROM (EPCR) Reserved $0930 $0830 $0100 LCD RAM $0A5D $0A5C $0A30 Not Used $092F $095D $0A2F $BE00 $BDFF

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 B-4 REV 2.0 B.4 PIN ASSIGNMENT The MC68HC05CL16 pin assignment for the 100-pin TQFP package is shown in Figure B-3. Figure B-3. MC68HC05CL16 Pin Assignment BP6 BP7 BP9/FP51 PTC7/TCAP2 PTB7 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 VDD VSS AD1 AD0 FSK+ FSK– RT_L PTB6 FP43 FP42 FP40 FP39 FP38 FP37 FP36 FP35 FP34 FP33 FP32 FP31 FP30 FP29 FP28 FP41 FP18 FP17 FP15 FP14 FP13 FP12 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP16 FP44 BP15/FP45 BP13/FP47 BP12/FP48 BP11/FP49 BP10/FP50 BP8/FP52 BP5 BP4 BP3 BP2 BP1 BP14/FP46 FP11 100 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 PTC1/MISO PTC0/SCK BP0 VLCD PTC2/MOSI PTC3/SS PTC4AD2 PTC5/AD3 PTC6/TCAP1 FP2 FP1 PTA0/IRQ0B PTA1/IRQ1B PTA2/IRQ2 PTA3/KBI3 PTA5/KBI5 FP0 PTA4/KBI4 RD1 RD2 OSC1 RESET XFC IRQ /VPP* PTA7/KBI7 PTA6/KBI6 OSC2 MC68HC05CL16 *VPP is available on MC68HC705CL16 only

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 C-1 APPENDIX C MC68HC705CL16 This appendix describes the differences between the MC68HC705CL16 and MC68HC05CL16. This part is for user system evaluation and debugging only, and is not recommended for mass production. C.1 INTRODUCTION The MC68HC705CL16 is an EPROM version of the MC68HC05CL16, and is available for user system evaluation and debugging only. The MC68HC705CL16 is functionally identical to the MC68HC05CL16 with the exception of the 16k-byte user ROM replaced by 16k-byte user EPROM and, the self-check routine is replaced by a bootstrap routine. C.2 MEMORY The MC68HC705CL16 memory map is shown in Figure C-1. C.3 BOOTLOADER MODE Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is at VTST and the PTB7 pin is at logic one. The Bootloader program and vectors are masked in the ROM area from $FE00 to $FFEF . This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass. The user code must be a one-to-one correspondence with the internal EPROM addresses.

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 C-2 REV 2.0 Figure C-1. MC68HC705CL16 Memory Map Ctimer/WTimer $FFF0 $FFF1 IRQn/KBI $FFF2 $FFF3 Caller_ID $FFF4 $FFF5 SWI $FFFC $FFFD SPI $FFF6 $FFF7 Timer $FFF8 $FFF9 IRQ $FFFA $FFFB Reset $FFFE $FFFF I/O Register $0000 $002F RAM $00FF Not Used $0030 Stack $082F $BDFF Bootstrap ROM $FFEF Bootstrap Vectors $FE00 User Vectors $FFF0 $FFFF $FFE0 $FFDF $00C0 Port A Data Register $00 Port B Data Register $01 $02 Port A Direction Register $03 Timer Pin Configuration Register $04 $05 $06 $07 Core Timer Control/Status Register$08 Core Timer Register $09 $0A $0B $0C $0D Caller ID Data Register $0E $0F $10 $11 Timer Status Register $12 $13Input Capture High Register 1 $14Input Capture Low Register 1 $15Output Compare High Register 1 $16Output Compare Low Register 1 $17 Counter High Register $18 Counter Low Register $19 Alternate Counter High Register $1A Alternate Counter Low Register $1B External Interrupt Control Register $1C External Interrupt Status Register $1D $1E Option Register $1F Not Used $095C Input Capture Low Register 2 Timer Control Register Output Compare Low Register 2 Output Compare High Register 2 Input Capture High Register 2 Caller ID Control/Status Register 2 Caller ID Control/Status Register 1 LCD Control Register Caller ID Control/Status Register 3 PLL Status/Data Register $FDFF $20 $21 $22 $23 $24 $25 $26 $2F $27 SPI Control Register SPI Status Register SPI Data Register Port C Data Register Port B Direction Register Port C Direction Register Watch Timer Control & Status Register A/D Control and Status Register A/D Data Register EPROM Program Control Register Reserved $0930 $0830 $0100 LCD RAM $0A5D $0A5C $0A30 Not Used $092F $095D $0A2F EPROM 16k Bytes $BE00

June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 MOTOROLA REV 2.0 C-3 C.4 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Register located at address $26. Please contact Motorola for programming board availability. C.4.1 EPROM Program Control Register (EPCR $26) This register is provided for programming the on-chip EPROM in the MC68HC705CL16. ELAT—EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit should not be set when no programming voltage is applied to the V pp pin. PGM—EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array. 1 = Programming power is switched ON to EPROM array. If ELAT „ 1, then PGM = 0. C.4.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time t PGMR 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes. EPCR $0026 bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 Read RESERVED ELAT PGM Write Reset 00000000

GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA MC68HC05CL48 C-4 REV 2.0 CAUTION It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. Figure C-2 shows the flow required to successfully program the EPROM. Figure C-2. EPROM Programming Sequence START ELAT=1 Write EPROM byte EPGM=1 Wait 1ms EPGM=0 ELAT=0 Write additional byte? Y N END

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