68000-8/BXA

68000 ETC1 | Alldatasheet

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Customer Specific Products DESCRIPTION PIN CONFIGURATION PIN CONFIGURATION ‘The 68000 is the first implementation of the 68000 16/32 bit microprocessor archi- tecture, The 68000 has a 16-bit data bus and 24-bitaddress bus, while the full archi- tecture provides for 32-bit address and a 7 A data buses. It is completely code-compat- oO |=) Os ible with the 68008 8-bit data bus o fs) 0° & a) implementation of the 68000 and is down- » G fa or ward code-compatible with the 68010 o & fal) oe virtual extension and the 68020 32-bit im- » FF fay ve plementation of the architecture. Any as (| Ea oso user-mode programs written using the ws [7 Fa) on Gl 4) 68000 instruction set will run unchanged ea 2) on the 68008, 68010, and 68020. This is os fel fl ow possible because the user programming ww [et fs] O13 model is identical for all four processors onack [9 [=] ow and the instruction sets aro proper wo faq ors sub-sets of the complete architecture. BOKCK [3] [53] co MACE Function Lee Funeven The 68000 possesses an asynchronous om Gal fs] aca 1 oO BM bus structure with a 24-bit address bus Yc Fz) a22 3 Be 2M anda 16-bit data bus. ox fa aa i & Pa The resources available to the 68000 user ono [i FB) vee 2 oS 4) 410 consist of the following: ror 17] faa) 20 8, he © 1732-bit data and address registers reser [i fe] ae " a he © 16MB direct adressing registers vox (i fs] 10 ae gue « 56 powerful instruction types i 4 Ey “ Bok gue * Operations on five main data types sm ass a ie + Memory-mapped iO ea Fay ase 2 ge * 14 addressing modes wo faa) ara Ze # ao ‘As shown in the programming model (Fig- mo 5) a2 5 & bi ure 1), the 68000 offers sixteen 32-bit roo [35] an am © oe ragisters and a 32-bit program counter. rer Ll fi} aro mre on ‘The first eight registers (D0 -D7) are used roo il fi] a» Be Hb as data registers for byte (8-bit), word » ba) a Bh & or (16-bit), and long-word (32-bit) opera- xB Es] a7 38 ee tions. The second set of seven registers a as (AO- A6) and the user stack pointer (USP) ey pa may be used as software stack pointers “& f=} +5 and base address registers. In addition, the registers may be used for word and long-word operations. All of the 16 registers may be used as index registers. July 25, 1986 363 853-0866 84743

Figure 1. User Programming Model Figure 3. Status Register

Table 1. Addressing Modes Data Types and Addressing Reale Indirect addressing wn etc., are provided in the instruction set.

Table 2. Instruction Set Summary Instruction Set Overview ABCD ‘Add decimal with extand subsets of these, and they appear in Table 3. ASL Avithmetic shit left languages to faciitate ease of programming. CHK ‘Check register against bounds (through traps).

Table 3. Variations of Instruction Types

‘Signetics Military Customer Specific Products Product Specification $$ SSsSsSsSSsSsSsSEee™/esrron 16-/32-Bit Microprocessor 68000 SSS DATA ORGANIZATION AND ADDRESSING CAPABILITIES 11 Wremdtocaaaganratorcttoesce, | [even nt erntome | tors and the data organization of the 68000. BYTE 000000 [BYTE 000001 a ee Operand Size a Operand sizes are defined as follows: a byte ‘equals 8 bits, a word equals 16 bits, and a long word equals 32 bits, The operand size for each WORD FFFFFE Merci einer pial enasesnbere ‘struction or implicitly defined by the instruction ‘operation. Implicit instructions support some ‘subset of all three sizes. Figure 4. Word Organization In Memory Data Organization in Registers Te ope a aaaisiers support data cperands Data Organization in Memory Effective address —use ofthe different efoctive of 1, 8, 16, or 32 bits. The seven address regis- Bytes aro individually addro: with the sing modes. tors together withthe stackpointerssupportad- |e a ie having an even adrose the _ dress operands of 32 bits cane an the werd or thew in Figure 4. The Implicit roforence ~ the definition of cortainin- low-order byte has an odd address that is one structions implies tre use of specific registers. Data Registers ‘count higher than the word address. Instruc- Each data rgistor is 92 bits wide, Byto oper- fone and multbyle data are accessed enly on Instruction Format ands ocoupy the low-order 8 bits. word oPer- wer (evenbyte) boundaries. along-wordda- Instructions are from one to five worden length ands he low-ordor 16 is, andlong-wordoper- tum is located at address n (n even). then the as shownin Figure 6, Tho length of the instruc. ans he onto 2 bits, The least significant bit secondword ofthatdatumislocatedataddress ton and the operation tobe performedis spoct Isaadressodas bit zero; hemos signifcant bit noe fied by the first word of the instruction which is 's addressed as jt Calledthe operation word. The remaining words When datarepistris used ethora source Jl ‘aumrty eared by to 69000 art her specily the operands. Those words are ‘oF destination operand, only the appropriate Grasses and binary-coded decimal data. Each _&therimmediato operands or extensions tothe (onrorder portion is changed: the remaining of tose data ypesis putin memory, as shown <feCtVe adcress mode specified in the opora- high-order portion is neither usednor changed. in Figure 5. The numbers indicate the order in 80 WOrd. which the: | would be acces {from the pro- Address Registers cessor. “ata sso Program/Data References Each address register and the stack pointer is ‘The 68000 separates memory references into Szbis wie andhoks ata 32-bhadoss Ad- Addressing two classes: program references and data ret- dress registers do not support the sized oper- . ‘erences. Program raferences, as the name im- lands, Therefore, whan an address register is_nstuctions fr the Boor ain two Kinds Of pigs are references to that soction of memory used as a source operand, either the low-order information: the type of function fo be per thatcontains the program being executed. Data word or the entire long-word operand is used formed and the location of the operand{s) 09 refarences refer to that sacton of memory that depending on the operation size. When anad- Which 10 perform that function, The methods contains data. Operandreads are trom the data dress register is used as the destination oper- Used to locate (address) the operand{s) are @x- space exceptin the case of the program counter and, the entre registerisaffectedregardless of _Painedin the following paragraphs, relative addressing mode, All operand writes the operation size. I the operation size is word, Instructions specify an operand location in one are to the data space. any other operands are sign extended to32bits of three ways: belore the operation is performed, Rogister specification the numberofthe regis- Register Specification ter is given in the register field of their instruc- The register field within an instruction specifies tion. the register to be used. Other fields within the instruction specify whether the register se- lected is an address or data register and how the register is to be used. July 25, 1986. 68

1 WORD» 6 ors

Figure 5. Memory Data Organization

Table 4. Effective Address Encoding Summary Table 5. Data Movement Operations

Signotics Military Customer Specific Products Product Specification 16-/32-Bit Microprocessor 68000 Program Counter with Index—Thisaddress- Effective Address Encoding Data movement Bit Manipulation ing mode requires one word of extension. The Summary Integer arithmetic Binary coded decimal address is the sum of the address in the pro- ‘i ing diel Program control gram counter, the sign-oxtended <isplacomant Tab daauedu heeedoncangeann Shiftand rotate System control integer in the lower eight bits of the extension The to range of ins ties word, and the contents ofthe index register. The plinheuetlih haley siben-arnid value in the program counter is the address of System Stack r jously proto evant “ ‘ in. described previously provide a very flexible the extension word. This reference is classified The system stacks used implicity by many in- 2° 0m as a program reference, structions; user stacks and queues may be ase for program development. — Thi |. Createdand maintained through the addressing creer ona or we see aeg mode fo mades. Address register soven (A7)isthosys. Data Movement Operations ponding on the size of the operation. tom stack pointor (SP). The systom stack point- The basic method of data acquisition (transter ° cris either the supervisor stack pointer(SSP) or and storage) is provided by the move (MOVE) Byto operation ~ operand is low-order byte of the user stack pointer (USP), depending onthe instruction. The move instruction and the effec- ‘extension word. state of the Sbitin the status register. lthe Sbit tive addressing modes allow both address and son — operand i indicates supervisor state, SSP is the active data manipulation. Data move instructions al- ‘Word operation ~¢ isextonsion word. SYetom stack pointer and the USP cannot be low byte, word, and long-word operande to be Long-wordoperation—operandis nthe twoex- referencodas an addrass ragister. Ifthe Sbitin- transferred from memory to memory, momory tension words, high-order 16 bits are in the first dicates user state, the USP is the active system to register, register to memory, and register to extension word, low-order 16 bits are inthe sec- stack pointer and the SSP cannot be reler- register. Address move instructions allow word ond extension word, ‘enced. Each system stack fills from high and Jong-word operand transfors and ensure Implicit Reference — Some instructions make — memory to low memory. that only legal address manipulations are ex- implicit reference to the program counter (PC), ‘ecuted. In addition to the general move instruc- the system stack pointor (SP), the supervisor |NSTRUCTION SET SUMMARY tion there are several special data movement stack pointer (SSP), the user stack pointer This section contains an overview of the form instructions: move multiple registers (MO- (USP), or tho status registor (SR). A solocted and stucture of the 68000 instruction sot. The VEM). move peripheral data (MOVEP), ex- Setofinstructions may reference the status reg- instructions form a sot of tools that include all change registers (EXG), load efectve address ister by means of the effective address field. the machine functions to pertorm the following (LEA). push effective address (PEA), ink stack These are: operations. (UK), unlink stack (UNLK), and move quick ‘ANDI to CCR OntwSA (MOVEQ). Table 5 is a summary of the data ‘ANDI to SR MOVE to CCR movement operations. EORI to CCR MOVE to SR EORI SR MOVE fromSR ORI 10 CCR July 25, 1986 372

Table 6. Integer Arithmetic Operations Integer Arithmetic Operations 8, 16,32 Dx + Dy+X—> Dx tions accepting all operand sizes. Address. (EA) = fx, be sued on all sizes of data operands. (Ax) - (Ay) -X 9 (AX, ‘summary of the integer arithmetic operations. Table 7. Logical Operations Logical Operations

Table 8. Shift and Rotate Operations ‘Shift and Rotate Operations be performed in either registers or memory. Table 9. Bit Manipulation Operations Bit Manipulation Operations

Table 10. Binary Coded Decimal Operations Binary Coded Decimal NOTE: —{) = indirect with predecrement. Table 11. Program Control Operations Program Control Operations Conditional , - branch instructions and return instructions. Table 12. System Control Operations ‘System Control Operations EORI to SR Logical EOR to status register ‘are summarized in Table 12.

Figure 8. Input and Output Signals Table 13. Data Strobe Control of Data Bus

• These conditions are a result of current implementation and may not appear on future devices.

detail about the function being performed. 00-07. true, independent of whether thatlevolis repre- Tupt cycles, address lines A1, A2, and A3 pro- _@Plained in the following paragraphs. gate or negation is usedto indicate thata signal ing serviced while address lines A4 through that there is a valid address on the address bus.

Signetics Miltary Customer Specific Products Product Specification eine in ea 16-/32-Bit Microprocessor 68000 ee Read/Write (R/W) — This signal defines the System Control counter which may come upin any state (.e., at data bus transfer as a read or write cycle. The The system control inputs are used tocither re- power on, itis impossible to guarantee phase RAW signal also works in conjunction with the set or halt the processor and to indicate to the relationship of E to CLK). E is a free-running data strobes as explainedin the following para- processor that bus errors have occurred. the clockandruns regardless of the state of the bus graph. three system control inputs are explainedin the on the MPU. Upper and Lower Data Strobe (UDS,LDS)— _ollowing paragraphs. Valid Peripheral Address (VPA) —This input These signals control the flow of data on the Bus Error (BERR) — This input informs the indicates thatthe device or region addrassodis data bus, as shown in Table 13. When the RW processor that heres a problem with the cycle synchronous family device and that data line ishigh, the processorwillreadtrom thedata currently being executed. Problems may be a tansfor should be synchronized with the en- ‘bus as indicated. When the PU/W ine is low the result of: able (E) signal. This input also indicates thatthe processor will write to the data bus as shown. 1. nonresponding devices, Processor should use automa vector fr Data Transfer Acknowledge(DTACK)—This 2. interrupt vector ni isition faire, interrupt. Refer to Interface with Synchro~ input indicates that to data transfor ie corn. erupt ect sumber aca nous Peripherals. pleted. When the processorrecognizes DTACK - illegal access request as determined by @ Valid Memory Address (VTA) — This output during a read cycle, datais latched andthe bus —-™emory management unit, or is used to indicate to synchronous peripheral cycle terminatod. When DTACK is recognized 4, other application dependent errors. dovices that thore is a valid address on the ad- during awrite cycle, the bus cycleis terminated dross bus and the processor is synchronized to (Reler to Asynchronous Versus Synchro- The bus error signal intoracts with the halt sig- enable. Ths signal only responds toa valid po- nous Operation). nal to dotormine if the current bus cycle should fipheral address (VPA) input which indicates be re-oxecuted or if exception processing thatthe peripheral is a synchronous family do- Bus Arbitration Control should be performed. Woo. ‘The three signals, bus request, bus grant, and bus grant acknowiedge form a bus arbitration Foferto Bus Error and Hal Operation ofe@ processor Status (FCO, FC', FC2) circuitto determine which device willbe the bus 3t0nal information about the intoracton of ‘These function code outputs indicate the state mastor dovice. bus error and halt signals. (useror supervisor) and the cycle type currently Bus Request (BR) — This inputis wire ORed Reset (RESET) — This bidirectional signalline being executed, as shown in Table 14. The in- Tih lohordcueccthatesuldbetusmastors, &t8 10 resot (start a systom intialzation $e- formation indicated by the function code out: This inputindicatos othe processor that some ence) the processor in sponse ton exter- puts is valid whenever address strobe (RS) is nal reset signal. An internally genorated reset active, ther davice desires to become the bus master. ola meseT instructs oxen Bus Grant (8G) — This ouputndcates taal devices to bo reel and tte eat of other potential bus master devices thatthe pro- tha proceseorie rotafocted. Atotalsystom re Table 14. Function Code Outputs cessorwillrelease bus control attho endofthe set (processor and external devices) is the re- FUNCTION ‘current bus cycle sult of extemal HACT and RESET signals | CODE OUTPUT Bus Grant Acknowledge (EGACK)— Thisin-appiodattho same ime. RelortoResetOper- [FOZ | FOi | FOO | Put indicates that some other device has be- _atlon for further information. ‘come the bus master. This signal should not be Hatt (HALT) — When this bidirectional line is | Low [Low | Low [(Undetined, reserved) | ‘assorted until the following four conditions are griven by an external device, it will cause the [Low [Low [High |Userdata | Me i rte ycle When Pe pececeornae boon [Low [Hah [tow [Userprearam | 1. a bus grant has been received, rent bus cycle. When the processor has been 2. address strobe is inactive which indicates halted using tis puta contrat ional ae [ Low [High | High | (Undatined, reserved) | that the microprocessor is not using the active State lines are put in thoir bus, 9 IN? high-impedance state (refer to Table 18). Refer [Fi [tow | tow me) " ___ to Bus Error and Halt Operation for additional [High [tow [High | Supervisor data | Sai tanier acodaon hast mich inmate bot be recon Sween tw [Fgh [gh | tw [Super ea in ‘memory nor peripher- als ae using the bus, and oe ore [Fian [Fiat | High | interupt acknowledge | When the processor has stopped executing in- 4. bus grant acknowledge isinactivewhichind- structions, such as in a double bus fault cond- — Cioek (CLK) cates that no other device is stil claiming tion (roferto Double Bus Faults), the HALT line The clock input is a TTL-compatible signal that bus mastership. isdrivenby the processor toindicatetoextemal js internally buttered for development of the in- devices that the processor has stopped. temal clocks needed by the processor. The Interrupt Controt (IPLD, TPLT, IPC) clock input should not be gated off at any time ‘These input pins indicato the encoded priority Peripheral Controt and the clock signal must conform to minimum levelot the device requestingan interrupt Level Th@S@ control signals aro used.to allow the in- and maximum pulse wicth times. ‘sevenisthehighestpriority whilelevelzeroind- ‘ertacing of synchronous peripheral devices catos that no interrupts are requested. Lavel with the asynchronous 68000. These signals sional summery ‘seven cannot be masked. The least significant _@F@ explained in the following paragraphs. Table 15 is a summary of all the signals dis- bitis givonin TPT and the most signficantbitis Enable(E)—Thissignalisthe standardenable _cussed.in the previous paragraphs. contained in IPL. These lines must remain signal common to all synchronous type periph- stable until the processor signals interrupt ac- eral devices. The period for this output is ten knowledge (FCO - FC2 are all high) to insure 68000 clock periods (six clocks low, four clocks that the interrupt is recognized high). Enable is generated by an internal ring July 25, 1986 377

The following paragraphs explain control signaling all signals itissues at both the startandend —_ asserting both upper and lower data strobes.

1. data bus DO through D15, and used by the 68000 for interlocked multiproces- gata is received, the processor correctly posi-
2. control signals Read ycle— During areadeycl,theprocos- nema

Sorrecelves dala rom the momory ora periph. Awordreadcycl flowchartis given in Figure 8. Table 15. Signal Summary

1. Function codes are placed in high-impedance state during HALT,

2 Peace Function cone on Foorce

Figure 9. Word Read Cycle Flowchart

‘eral device. The processor writes bytes of data datastrobe required{orthatbyte. Forbyteoper- byte write cycle flowchart is given in Figure 14. ‘operation, the processor writes both bytes. data strobe is issued. When the AO bit equals 15 details word and byte write cycle operation.

1 ERO somomeoce

Figure 13. Word Write Cycle Flowchart

2 Setawioweane

Figure 15. Word and Byte Write Cycle Timing Diagram

68000, this cycle is indivisible in that the ad- tion that uses the read-modity-write cycles and en in Figure 17.

2 BEAGE FUNCTION cODE On Fc0-Fc2

2 PASE BATA ON be-07 OR Ds-O6

3 SAear ow TeANSEER AIONORLEOOE

2 Puce DATAON D607 0R De-D1s

3 ASSERT UPPER DATA StRORE (UES) OR

3 Re wove Gxva FROM 00-07 OR 08-015

Figure 16. Read-Modify-Write Cycle Flowchart

29 SECT BUS NAGTER ASSERTS BUS GRANT

1 DoS WASTER NEGATES BR

Figure 18. Bus Arbitration Cycle Flowchart

Signetics Miltary Customer Spocifie Products Product Specification ss Oren 16-/32-Bit Microprocessor 68000 SSS a SUA ee I a ED Ss ED CED Se CED GH wa) >) > ee ee a an a a i OO SO ec a A a vrxcK \\_S \\_S LS \\S YS a a oe CD aD ee cy sx _ [| 5G \\ / \\ / ware /- — \\ — rrocesson —mefae— oma vevice refuge roctsson ———pefag ua vec: ——— Figure 19, 68000 Bus Arbitration Cycle Timing Diagram Requesting the Bus — External devices capa- asserted oindicate external devices thatabus until it negates bus grant acknowledge. Bus bleofbecomingbus mastorsrequestthe bus by cyclo is being executed. ‘grant acknowledge should not be negated until asserting the bus request (BR) signal. Thisis a after the bus cyclo(s) is (are) completed. Bus wire-ORad signal (alhough itaeed not be con- Je Bus grant signal may be routed though a as wrshipietaminatedat the nogaton of bus e ing, d2i8y-chained network or through a specific Struct trom open-collecior devions) that ind or ccdmatwork Therrenoese ner antacknowlodge vice reacts central me extemal do~ sctadby he oxtornal method arbivation as Thebus equestfrom the grantoddevice should wee at tiOL OF the oxto ‘onty (Og as the protocol is obeyed. be dropped after bus grant acknowledge is as- processor is effectively at a lower bus priority serted. If bus requests stil pending, anothor level than the external device and willrelinquish bus grant wil bo assertod wither toc clocke of thobus aterithas completed he ast bus cyclo Acknowledgment of Mastership—Uponre- bus Grant wi be asse Rotor to Bow Ar ithas started. ceiving a bus grant, the requesting device waits the negation of the bus grant. Refer to Bus Ar- until address stobe, data transfer acknowl. bitration Control. Note that the processor {hen no acknowledge is received before the edo, and bus grant acknowledge are negated does not perform any extomal bus cycles be- bus request signal goes inactive, the processor before issuing its own SGACK The negation of fore it re-asserts bus grant. willcontinue processingwhenitdotects thatthe the address stiobe indicates that tho previous bus request is inactive. This allows ordinary masterhas complotedits cycle; thenegation of Bus Arbitration Control Processing to continue the arbitration circuity bys grant acknowledge indicates that the pre- The bus arbitation control unit in the responded to noise inadvertently. vious master has released the bus. (While ad- SCN68000 is implemented with a finite state dress strobeis asserted, no devices allowedio machine. A state ciagram of this machine is Receiving the Bus Grant—The processoras- “break into” a cycle.) The negation of data shownin Figure 20. Allasynchronous signals to Sorts bus grant (BG) as soon as possible. Nor- transfer acknowledge indicates the provious the SCN68000 are synchronized botore being ‘mally this is immediately after internal synchro- slave has terminated its connection to the pre-_usedinternally. This synchronization is accor. nization. The only exceptionto this eccurswhen vious master. Note that in some applications _plishedinamaximum ofone cycleo! the systom the processor has made an intemal decision to data transfer acknowledge might not enterinto clock, assuming that the asynchronous input execute the next bus cycle but has not prog- this function. General purpose devices would setup ime (#47)has been met see Figure 21). ‘essed far enough into the eycle to have as- thenbeconnected such that they were only de- The input signalis sampled on the faling edge Sorted the addrass strobe (KS) signal. n this pendenton address strobe. When bus grantac- ofthe cock andi valid intamally attr the noxt case, but grant will be delayed until AS is _knowledgeisissued, the deviceisabusmaster falling edge. July 25, 1986 386

Figure 20. 68000 Bus Arbitration Contro! ‘Unit State Diagram

Signetics Miltary Customer Specific Products Product Specification 16-/32-Bit Microprocessor 68000 eee bus astareD BUS RELEASED FROM THREE STATE AND BUASSERTED PROCESSOR STARTS NEXT BUS CYCLE BR ASSERTED [VORCK NEGATED INTERNAL {BR VAUD INTERNAL ‘WORCK SAMPLED BH SAMPLED | [BRACE NEGATED 4 o TLL LLL LLL LLL $e ss os ox ma / a \\ / ore — \\ / i, ee, OD, eS ee ee CED = a so NYS __ i _ S/S Se a ne a os ee ee ee pd — vc _—— aN a a. i cr ~<— rrocesson ——— fq suremare ous uasten se} pocesson ——pe- Figure 22, Bus Arbitration Timing Diagram—Processor Active ‘As shown in Figure 20, input signals labeled R_ the busis inactive (.0,, executing internal oper- that the handshake might not occur. Since it- ‘and Aare intemally synchronizedon the bus e- ations suchas.amultply instruction) is showin ferentsystems will require a diferentmaximum uestand bus grantacknowlodge pins,respec- Figure 23. response time, abus errorinputis provided. Ex- tively. The bus grant outputs labeled G andthe . tornal circuitry must be used to determine the intemal State contol signal Tis tue, the aPuproavestemaccataline when teMPU duration between address strobe and data address, data, and control buses are placedina beenansorad Deasitosay EE willrothess, Wansteracknowiedge botoreissuing abus error high-impedance state when 7S is negated Al oe a ee eee Beam signal. When abus eror signal is received, the signals are shown in postive logic (active high) fvted i palpi ae es ing edge follow. PFOC@SSOF has two options: initiate a bus error rogardess of their tuo active voltage lovel, Pe celayed unt tha Mion The cocrenen, _@xcoption sequence or ty running the bus cyclo ‘State changes (valid outputs) occur on the next a i as 2k ns Sequence IS oain, rising edge attor the internal signalis valid, Shown in Figure A timing diagram of tho bus arbitration £0- Bus Error and Halt Operation uence during @ processor bus cycle is shown in a bus architacture that requires a handshake in Figure 22, the bus arbitration sequence while from an external device, the possibilty exists July 25, 1988 388

Figure 23. Bus Arbitration Timing Diagram—Bus Inactive

Signetics Military Customer Specific Products Product Specification $$ ACTS poetcation 16-/32-Bit Microprocessor 68000 _—_ TSS Bus a-staTED BUS RELEASED FROM THREE STATE AND wuanscaTeo PROCESSOR STARTS NEXT BUS CYELE ‘BR VALIO INTERNAL [WGREK NEGATED INTERNAL BR SAMPLED WORCK SAMPLED r ASSERTED [BRACK NEGATED 4 o SLL LLL LLL LL Ce ee so 2 4s m= 7\\ /~ ws \\ / a — \\ / fe a a a a nS oy es We Xs Se eee ae vos So NY >7—\\r os So VN >?—_ or a a oak _/—\\ / _ ~ \\ / So ~<—_ Processon ————e fg aremnare aus master ef processon ———e- Figure 24, Bus Arbitration Timing Diegram—Special Case Bus Error Operation — When the bus error this location. A sofware bus error handler rou- made to guarantee thatthe entire cycie runs Signalis agsertod, the currentbus.cycleistermi- tine is then executed by the processor. Refer to correctly and that the wrte operation of nated. i BEFA is asserted boforo tho faling Exception Processing for additional informa- tast-and-set operation is portormed without ‘edge of S2, AS will bo negated in S7in either a tion, ever roleasing AS, if BERA and HALT are as- read or write cyclo, As long as BERA remains sorted during a read-modify-writo bus cycle, a acserted, tho data and adress buses willbo in ResBun Operation — When arg a ia B® 8Tor operation resus dase erpedan sor wilbogin sacking tron, adh hal pinisbeieg driven by an oxnal Halt Operation — The hat input signal to the ception processing. Figure 25 is a timing dia- 2vice, the processor enters the re-run se- 68000 performs a halt/run/single-step function gram for the exception sequence. The se- Q2NCS. Figure 26 is a timing diagram for ina similar fashion to the synchronous device i ing re-running the bus cycle. haltfunction. The halt and run modes are some- ‘quence is composed ofthe following olements: iat celery intarwhor bhatt. 1. stacking the program countorand statusreg- The processor terminates the bus cycle, thon Tati 2 eipmamay in at processor “halts” ister, Puts the address and data output ins in tho (ie Conta ace te Brod ‘signals con. a high-impedance state. The processorremains {Coca noting) and when the halt signal (coos 2. stacking the error information, “halted", and will not run another bus cycle until something) proces reading the bu: le entry, and the halt signal is removed by external logic. Z 8 ‘Rebus errorvectortable enty,and hat s Processor will re-run the previous This single-step mode is derived rom correctly 4. executing the bus error handler routine, cycle using the same function codes, the same timed transitions on the halt signal input, It . ata (lor a write operation), andthe same con- forces the processor to execute a single bus ‘The stacking of the program counter and the trols. The bus. ‘error signal shouldberemovedat cycle by entering the run mode until the proces- seaunreplgor's he same asitaninterupthad jeastoneclock cyciabeore the halt signalisre- sor starts a bus cyelo then changing tothe hat ccurred. Several additional itams are stacked moved, ‘mode. thus, the single-step mode allows the ‘when a bus error occurs. These items are used User to proceed through (and therefore debut) ‘o determine the nature ofthe errorandcorect ote processor operations one bus cycle at a time. iif possiti. The bus error vector is vector The processor wil not retun a ‘number two located at address $000008. The rea4modiy-wite cycle. This receicion if processor loads the now program counter from July 25, 1986 390

reset lines must be asserted to ensure total re- No other registers are affected by the reset se- the reset instruction. cessor responds by reading the reset vector the restof the system. Therefore, there isnoet — 100ms. Figure 28. Reset Operation Timing Diagram

Table 16. DTACK, BERR, and HALT Assertion Results The Relationship of DTACK, may be ignored if the above conditions are. FACT DTACK occurs frst (Case 1). N-the number of the current even bus state (@.g., S4, S6, etc.) DIRK. Table 17. BERR and HALT Negation Results persek nk nein BERR legal sequence; usually when address strobe is negated). BERR neously after time out (Case 4). Normal May lengthen next cycle. same time as DTACK if data in error (Case 4).

Signotics Military Customer Spacific Products Product Specification ii i 16-/32-Bit Microprocessor 68000 NN Asynchronous Versus sence of DTACK inwhich easeitwilterinate The privilege mechanism provides security by ‘one clock cycle laterin S9.VPAissampledonly allowing most programs to execute in user Synchronous Operation con the third falling edge of tho systom clock be- stato. in this stata, tho accesses are controled, {ore the rising edge of the E clock. and the effects on other parts ofthe systom are Esc breaiorrseeiaeel indo ata Limited. The operating systom exocutos in the system love, the 68000 can be used in an PROCESSING STATES supervisor stato, has access foal resources: aetnrenous manner This entals using only This section describes the actions ofthe 68000 i! Performs fhe overhead tasks for he user the bus handshake lines (AS, UDS, TDS, which are outside the normal processing asso- state programs. DTACK, BERR, FACT, and VPA) to control this ciated with the execution of instructions. The data vanstor. Using his method, XSeignalsthe functions of the bits in the supervisor portion of Supervisor State . Start ofa bus cyde and the data stobes are the stalus register are covered; he supervisor? Te supervisor stam the highos Stato of priv care ats comtton for valid data on a write user bi the trace enable bit, andthe processor 1999. For instruction execution, the supervisor Gye. The slave device (memory or peripheral) interrupt priority mask. Fnaly, the sequence of states determinedby he Shito| He stausrog. Sercmencebplecrctorecuereddataon mamory references and actos takan by tho isteifthe biti assorted igh), theprocessor Teds tus for road ercleorlstching data on processoron exception conditions aredetalod. _‘Sinthe supervisor stata. Alinsinvctons car be swntocyaeandassoring datas ac Ty 2oc0isawaysinonesl eo processing Sys gure by tucion oxen Krowledgesignal(DTACK) oteminaiotebus Jaxer nornloncapton, or halos The nor frosopuriaorsatareclasifodas supers «Bie slave responds ortho accessis i” al rocaring snes tht essocaied wih. ferences, Whio fe processor isin be sp blister ele BERR. siucionexoouton:themomory references are visor pivige slate, those instuctons which foods signal to. abort or rerun the 19 eich instructions and operands, andto store use either the system stack pointer implicitly or a results. A special case of the normal tateis the addressregister seven explicitly access the su- ‘The DTACK signalis allowodtobeassertedbe- stopped statewhich the processor enterswhen —_porvisor stack pointer. fore the data from a slave device is valid on a stop instruction is executed. In this state, no i A read cycle. the length of time that DTACK may _ further references are made. ‘A exception processing ts donein the super procode daa gion as paramo #21 andi Thy exception processing stato ls essocatad Thebuscyte Deedee canton pe mustbe metin any asynchronous systemtoin- with interru inet. i Tnebus cycles generated during exception pro- ‘, Ipts, trap instructions, tracing, and cessing areciassifiedas supervisor references. suro that validdataislatchedintotheprocessor. ther exceptional conditions, The exception Notice that there is no maximum time specified Thay be internall Ail stacking operations. during exception pro- from the assertion of AS o tho assertion of ay einternaly gonoratecty an neinichon er _cossing use the supenisor stack pointer. by an unusual condition arising during the ex- DTACR. This is because the MPU wil insert wait ayeloe of M ecution of an instruction. Externally, exception User State cycles of one clock period each untl processing can be forced by an interrupt, by a i DTACK is recognized. t.bY a Theuserstateis the lower state of privilege. For Gerigned pouseancticentcontxtawich TatussyeStast he cut ogateni hes nohronous Operation mined by the S bitof the status register ifthe S eeien ta tee eters which yo tho sys. Sothatthe processor may handle unvvalcen- bitis negated (ow), he procassori executing tem clock as a signal to gonerate DTACK and instructions in the user stato, other asynchronous inputs, the asynchronous The halted processing state is an indication of Mist instructions execute the same in user input setup time is given as parameter #47. If catastrophic hardware fallure, For example, if state asin the supervisor state. However, some this setup is met on an input, such as DTACR, during the exception processing of a bus error instructions which have important system of- the processor is guaranteed to recognize that another bus error occurs, the processor as- fects are made privileged. User programs are signal on the next falling edge of the system sumes that the system is unusable and halts. not permitted to execute the stop instruction or clock. However, the converse is notirue—if the Only an external reset can restarta halted pro- the resetinstruction. To ensure thata user pro- input signal doos not meet the setup time it is c@ssor. Note that a processor in the stopped gram cannot enter the supervisor statg except not guaranteed not to be recognized. In addi- state is not in the halted state, nor vice versa. in a controlled manner, the instructions which tion, it TACK is recognized on a faling edge, modity the whole state register are privileged. valid data willbe latched into the processor (on Privilege States To aid in debugging programs which are to be read cycle) on the next falling edge provided The processor operates in one of two states of used as operating systems, the move to user that the data meots the sotup time given as pa- privilege: the “supervisor" state or the “user” stack pointer (MOVE to USP) and move from rameter #27. Giventhis, parameter #31 may be state, The privilege state determines which op- user stack pointer (MOVE from USP) instruc- ores, Note that it DIACK is assaried, with erations are legal, are used to choose between _ tions are also privileged. 10 roquired setup time, before tho falling edge the supervisor stack pointer and the user stack O1S4-nowaitsiates wilde incuredandthe bis poisern insvucton oforences, and may be Tatu CY ne eo eer yclewillunattsmaximumspeedottourciock Ysadby an extemal memory management do: SCu“\\tyersnace’ “This allows, an, extomal periods, v ox state references. This allows an extemal ce to control and transiate accesses. memory management device to translate the . ‘The priviloge state is amechanism for providing address and to control accass to protected por- Note ppaciart eve attne security in a computer system, Programs tions ofthe address space. While the processor clock st ‘with S2. DTACK is sampled on should access only their own code and data _ is in the user privilege state, those instructions overy Hei “edge ofthe clock starting with S¢ 2°85. ‘and ought to be restricted from access- which use either the system stack pointer im- ‘and dataislatchedon the fallin ing information which they do not need and _Plicity or address register seven explicitly, ac- wedge ot Sédur- i 08s the user stack pointer. ingaroad. Thebuscyclewillthenbeterminates TUStnot modily in S7 except when BERR is asserted in the ab- July 25, 1986 395

Table 19. Exception Vector Table ments by Signetics. No user peripheral devices should be assigned these numbers. may overlap atthe discretion of the systemsde- _ternally generated exceptions come from in- _rupt after each instruction execution. signer. structions, or from address errors or tracing.

a conditons for both arise. simutanoousy,. Figure 32. Exception Stack Order (Groups 1 and 2) reer inte tay tie ener tu ren ‘exception has priority, and is processed first. Table 20. Exception Grouping and Priority over, the intorupt excopton ie also. pro. Tevet Exception process 7 ‘ences finaly in the interrupt handler routine. bus error is given in Table 20. ‘execute unhindered by tracing. For the reset cording to their occurrence and priority. The _pervisor state and the trace state is forced off. ‘dress given in the exception vector is fetched, Priority relation within Group 2.

Signetics Miltary Customer Specific Products Product Specification 16-/32-Bit Microprocessor 68000 processor. Interrupt priority levels are num- stack. The saved value ofthe program counter Instruction Traps oredtrom one to seven, with level saven being is the address of the instruction which would Traps are exceptions caused by instructions. the highest priority. the status register contains have been executodhad the interrupt not been They arise either from processor recognition of 23-bit mask which indicates the current pro- present. The content of the interrupt vector abnormal conditions during instruction execu- cossorpriority, andinterrupts areinhibitedforall whose vector number was previously obtained — tion, or from use of instructions whose normal priory levels lass than or equal to the current is fetched andloadedinto the program counter, behavior is trapping. processor priority. ‘and normal instruction execution Commenc8$ Gomg instructions are used specifaly to gon- Anintorruptrequestismadotothe procossorby | Psneinerrupt Jooulouge cov A ene erate traps. The TRAP instruction always encoding theinteruptraquestiovalonthointor- Fires, me acknow ‘diagram is given in Figure forces an exception andis useful forimplement- ruptrequest lines; a zero indicates no intorrupt gS\\re Sy 2 tnnng Sagram ls @ inane ing system calls for user programs. The TRAPV request. Interrupt requests arriving at the pro- 2. unc Nes Meet ate and CHK instructions force an exception if the cessor do not force immediate exception pro. Shewnn Figure user program detects a runtime error, which cessing, but are made pending. Pending inter- Priority level seven is a special case. Level may bean arithmetic overfiow ora subscriptout rupls are detected between instruction execu- seven interrupts cannot be inhibited by the in- of bounds, tions. Ifthe priority of the ponding interrupt is terupt priority mask, thus providing a “non— . , . lower than or equal to the current processor maskable interrupt" capability. An interrupt is _T# Signed divide (DIVS) and unsigned (DIVU) instructions will force an exception it a division priory, exocuton continues with tho next in- generatodeach ime thointoruptrequostioval svuctor wit oiee an encontion Ba slik structionandtheinterruptexceptionprocessing changes from some lower level to level seven is postponed. (The recognition oflevel sevenis Note that a level seven interrupt may stil be slighty ditferent, as explained in the following caused by the level comparison if the request egal and Unimplemented Instructions paragraph.) levelis a seven and the processor priority is set “legal instruction” is the term used to rofer to it i i to a lower level by an instruction ‘ny of the word bitpatioms which are not the bit Ifthe priority of the pending interrupts greater patiorn of the frst word of a legal instruction than the current processor priority the exoep- During instruction execution, if such an instruc- tion processing sequence is started. A copy ot | Uninitlalized Interrupt - tion is fetched, an illegal instruction exception the status rogistoris saved, the privilege stateis An interupt device asserts VPA or provides an ours. Signetics reserves the right io define in- sent to the supervisor stack, tracing is sup- _'Nterruptduring an interrupt acknowledge cYCI@ structions whose opcodes may be any of the il pressed, and the processor priority lovelis set {© P@ 68000. Ifthe vectorragistor has notboen Joost instructions. Thae bt patterns will aways. to the love ofthe interrupt acknowledged. The _nitalized, the responding 68000 family periph tor<5 anillogalinstructiontrap on all6000 fam- processor fetches the vector number rom the alwilprovde vecter15,theuniniaizedintar- jp'a7 Degas on tay are interrupting device, classifying the reference as ‘WPt Vector. This provides a uniform way toe axEx RFE. and ZAFT. Two of the pattoms, an interrupt acknowledge and displaying the COV8r from a programming error. ‘AFR and JAF, are reservedior Signetics sys- level number of the interrupt being acknow!- tems products. The third pattorn, AAFC, is re- ‘edged on the addross bus. If extornal logic re-_ Spurlous Interrupt sorved for customer use. ‘quests an automatic vectoring, the processor {during the interrupt acknowledge cycte no de- internally generates a vector number which is _Vioe responds by asserting DTACK or VPA, the Word patterns with bits 15 through 12 equaling determined by the interrupt lovel number. Ifex- US erTor line should be asserted to terminate 1010 or 1111 are distinguished as unimplem- tornallogicindcates abus error, theinterruptis the Vectoracquisition. Theprocessorseparates ontedinstructions and separate exception vec- takon tobe spurious, andthe generated vector the processing ofthis error from bus error by tors are given to these pattorns to permit aff- number references the spurious interrupt vec. f6Iching the spurious intoruptvectorinstead of cient emulation. This facility allows the operat- tor. The processor then proceeds with the usual ‘8 bus error vector. The processor then pro- ing system to detect program errors, or to emu- exception processing, saving the program 022d8 with tho usual exception processing, _lato Unimplementod instructions in software counter and status register on the supervisor July 25, 1986 399

3 Neate Gas AND eos

Figure 33. Vector Acquisition Flowchart

9 CD el —__

Figure 34. Interrupt Acknowledge Cycle Timing Diagram

Signotics Miltary Customer Spocitic Products Product Specification or — 16-/32-Bit Microprocessor 68000 a ust aus cycus ck ‘Gunma wae ors enter (vecTOR NOMBER TEocRZEDy” ACQUISITION) stack READ FeTeMARST TWO FORMATIOFFSET victor vEcTOR INSTRUCTION WORDS WORD. Haan Low ‘OF INTERRUPT (aT S8P-2) atenza) unas) ROUTINE NOTE: "SoF te tone valve one perio stack pinta belt th torr cu. Figure 35, Interrupt Processing Sequence Privilege Violations by that instruction, the forced exception is pro- error occurred during the fetch of the next in- In order to provide system security, various in- cessed before the trace exception. struction, the saved program countor has a val structions are privloged. An attemptto execute i Le in the vicinity of the currentinstruction, even cone of the privileged instructions while in the AS On cxzome llustaton of he jnow res: ithe currentinstrucon is abranch,ajump, ora User state will cause an exception. The privi- : erupt anon return instruction. Besides the usual informa- tate wil ecution of a TRAP instruction while tracing is ‘® : logod instructions are: tion, the processor saves its internal copy of the ‘nablod. First the trap exception is processad, fo" Wve ras puss boing procoseodand sToP AND Immediate to SR then the trace exception, and finaly the inter- ys ouol tu nshucton mama proseeats RESET EOR Immediate to SR —_rupt exception. Instruction execution resumes - ad ATE orig aborted bus cycle. Specific information about 110 SR_—_in the interrupt handler routine. HOVEWSR MOVE DUSP the access is also saved: whethor itwas.a read pus ‘orawrita, whether or not the procossorwas pro- Tracing Bus error exceptions occur when the external Santas on te ramet code outpuss wen To aid in program development, the 68000 in- _logicrequests that abus error be processedby the buy error oscurred. The procassor i pro. cludes a facility to allowinstruction-by-instruc- an exception. The current bus cycle which the Ov. cine ar inepuctionif itis in the normal Stato tion tracing, In the trace stato, after each in- processor is making is then aborted. Whether CP. eacvating 2 Group 2 envopiion; the proces. structionis executed an excoptionis forced, al- the processor was doing instruction oF excep- Fie not processing an instruction if itis pro- lowing a debugging program to monitor the ex- tion processing, that processing is terminated, 2°03 Group 0 ora Group 1 exception. Fig- ‘ecution of the program under test and the procestorimmediatoly begins excep: Sosbds Group ora our! excopton, Fg ‘The trace facility uses the Tbutinthe supervisor HOP Processing, nized on the supervisor stack. Although this in- portion of the status rogister. Ifthe T bitis ne- Exception processing for the bus error follows formation is not suficiontin general to effect full {gated (off), tracing is disabled, and instruction the usual sequence of steps. The status regis- recovery from the bus error, it does allow soft- ( tog ‘execution proceeds from instruction to instruc- ter is copied, the supervisor state is entered, ware diagnosis. Finally, the processor com- tion as normal. Ifthe Tbitis asserted (on) atthe and the traco state is turned off. The vector _mences instruction processing at the address beginning of the execution of an instruction, a number is generated to refer to the bus error containedin vactor number two. Its therespon- trace exception will be generated alter the ex- vector. Since the processorwasnotbetweenin- sibility of the arror handler routine to clean up ecution ofthatinstuction is completed. Ithein- _structionswhen the bus errorexception request _ the stack and determine where to continue @x- struction is not executed, either because an in- wasmade, the contextof the processors more _ecution. torrupt is taken, othe instruction is illegal or dotailed. To save more of this context, adition- privieged, the trace exception does not occur. alinformationis savedon the superisor stack, 1 DUS eror occurs duneg he excapson prs: The trace exception also doos not occur if the Theprogram counter and the copy of thestatus jhe Hs sor is hated and all processing instruction is aborted by a reset, bus error, or register are of course saved. The value saved Sua Pease ‘plifes the Cwacten of address error exception. ifthe instruction isin- forthe program counter is advanced by some Shc eystom failure, since the ae doed executed and an interrupt is pending on amount, one to fiva words beyond the address ae toon tre ‘system rabvor than do- completion, the trace exception is processed of the first word of the instruction which made o¥s ‘ats, Only the RESET before the intorrupt exception. If, during the ex- the reference causing the bus error. tthe bus S\\"°Y any memory FOr ¥ during in can restart a halted processor. ‘ecuition of the instruction an exception is forced Las July 25, 1986 401

Signetics Military Customer Specific Products Product Specification eee 16-/32-Bit Microprocessor 68000 ——_—— SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSHesesese PROCESSOR sue 1) THE PROCESOOR STARTS ANORMAL READ OAWATE CYELE PERIPHERAL ADORESS (VPA) 1) THE PROCESSOR MONITORS ENABLE (E) The PROGESOON ASSERTS VALO SERS ASTIVE AND THEN TRANSFERS THE OATA AND DRIVES THE E CLOCK LOW (ON A READ CYCLE, THE DATAISLATOED AS E-Goes LOW NTERNALY) 2) THE PROCESSON NEGATES THK Figure 38, Synchronous Interfacing Flowchart Data Transfer Operation andin state 4 the data strobes areissuedtoind- then VPA will be recognized as being asserted Three signals on the processor provide the syn- cate valid data on the data bus. The processor onthe falling edge of S4. In this case, no “extra” chronous interface. They are: enable (E), valid "OW inserts wait states until it rocognizes the wait cyctes will be inserted prior to the recogni- memory address (VMA), and valid peripheral assertion of VPK. tion of VPA asserted and only the wait cycles in- address (VPA). Enable corresponds o the Eor The VPK input signals the that the S@"tedto synchronize with the E clock willdeter- phase 2 signal in oxstng synchronous 6yS- addrosson hebusis tho adsross ota synchro: ina the tla longth ofthe cyto, n any caso, toms. The bus frequency is one tenth ofthe in- ous dovice (or an area rosorved for synchro. tnesynchronization delay willbe some integral coming 68000 clock frequency. The timing ofE nous devices) and thatthe bus should conform umber of clock cycles within the following two allows 1MHz peripherals tobe used with 8MHz tg the phase 2 transler characteristics of the | @xe™es: £80008, Enabiohas a6040dulyoyie:thats,t Synchronous bus, Valid peripheral adtoss is B28tCase— VPRis ecogrizodas being as- islow'or sixinput locks andhhighforfourinput Gorived by decoding the address bus, cond. __Sertedonthe ling edge three clock cycles clocks, This duty cycle allows the processor 10 tionedby the address strobe. Chip selectforthe - Before E rises (or three clock cycles after E do successive VPA accesses on successiveE synchronous peripherals should be derived by ls) pulses, decoding the address bus conditioned byVMA. 2. Worst Case — VPs recognized as being ‘Synchronous cycle timing is given in figures 39, after, ition of VPA, th assertedon the falling edge twoclock cycles 40, 48, and 49. At state zor0 (SO) in the cycle. thatihe evabio (is tow, ty wallng i races: before E rises (or four clock cycles after E the address busisinthehigh-impedancestale. sary, and subsequently “asserts VME. d falls). ‘Afunction code is asserted.on the functioncode memory address is then used as partof the chip utputlines. One-half clocklater, in state 1,the select equation of the peripheral. This ensures Du*ing a read cyclo, the processor latches the address bus is reloased from the high~impe- that the synchronous peripherals are selected Perieheraldata in state 6. For all cycles the pro dance state, andeselected atthe correct ime. The periph- COs#0" Nogales Whe across and dala suobos . ‘ ie one-half clock cycle | 7 During stato 2, the address strobe (KS) is as- eralnow runsits cycle during the high portonot 2h Snal goes low athe ine Potente sorted toindicate thatthereis.avalidaddress on the E signal. Figures 39 and 40 depict the best ocx tater, the address bus is put in the high— the address bus. tthe bus cycles areadcycle, and worstcase synchronous cycle tming. This impedance state. During a write cycle, the data theupporandiorlowerdatastrobesare alsoas. <yclolengthis dependent strict onwhon VPA ye. tin we high-im 4 i - serted ir ¢ 1) \\pedance state and the sertedin state 2. Ifthe bus cycleisawritecycle, 'S ass in relationship to the E readiwrite signal is switched high. The periph- te one (PU) signal is switched 1 ‘ow Itweassumethatextemal circuitry asserts VPA eral logic must remove VPA within one clock af- a on talor, i tion of AS, the addi ‘tated, thowrte date chaos eerie 8 S00n as possibe ater he sxzarion of ter the address strobe is negated. July 25, 1986 403

"Athovgh ODS and TDS are assorted, no da roa rom he bus ing the autovctr cyt, The vector nubs generated italy. Figure 41. Autovector Operation Timing Diagram The following paragraphs provide information able and memory addresses, and the lator ro ‘address mode.

Table 21. Effective Addressing Mode Categories

110 Register number

Table 22. instruction Set

Table 22. Instruction Set (Continued)

5 Weg thon 1's — Destination alse

1. When execution of an instruction begins, -
2. In the case of muli-word instructions, as Absolute short 12190)
3. Thelast fetch for an instruction from the in- Immediate (20)

oO et ‘The size of the index register (ix) does not atfact execution time.

1. The number of bus read and write CYCI@s Words, the addross computation, and fetching
2. Inthecaseotaninterruptortrace exception, _foreachinstructonis also included with thetim- Pina" De Naaees Camp OR eS
3. The program counter usually points to the esos inners shee periods and is as (7), Note thare are no write cycles involved

last word fetched fom the lnsveton Spoon anda late usnber elena in processing the effective address. clock (CLK) periods. in this timing data, itis as- ‘ycles is shown in parenthesos as (cw). Table 24. Move Byte Instruction Execution Times

Table 25. MOVE LONG Instruction Execution Times

• Tho size of the index register (ix) does not atfect execution time.

struction. The number of bus read and write indicated. tfoctive address operand. Table 26. Standard Instruction Execution Times + Add offective address calculation time. *** Only available effective address mode is data register direct. DIVS, DIVU — The divide algorithm used by the 68000 provides less than 10% difference between the best and worst case timings. MULU: ne the number of ones in the <ea>. ens when the source is $5555.

‘Signetics Military Customer Specific Products Product Specification ile ili ee oar ry 16-/32-Bit Microprocessor 68000 a Immediate Instruction Execution Times Table 27. Immediate Instruction Execution Times Te number of lock periods shown in Table [INSTRUCTION | [opsn [ops An [opm | trce, parr fo opraione, ce bo - a ‘ands, perform the operations, store the re- | Pee (20) sults, andread the next operation. The num- [tong | t6(8) = acai ber of bus reed and write cycies Is shown in [bye wors [avy [voy acre parenthoses as (ch). The number of dock Pe [tong acre) ery 2cvraye tiods and the number of read and write cycles must be added respectively to those of the of- [ byte, wore [aay zee fective address calculation where indicated [tong [1680 20a In Tablo 27, the headings have the following [bre word [aay = 820+ meanings: # =immediata operand, DN =data [7 tong] taeoy tase raglster operand, An = adress register ope |e Pees ee ee J, M = memory operand, and SR = status CL register. [Ptong | 36080) | wovea [tong [aro | bye, wars | 6@0) [22 [tong [690 = 2002 | [ “bye, word [aay zene ee [erie wors [avy Tavares [tong acvvoy avy ae NOTE: + 806 etfective address calculation ime * word only Single Operand Instruction Execution Table 28. Single Operand Instruction Execution Times ies [wwstauction [swe | recisten [Memory | ‘Table 28 indicates the number of clock periods: [em | for the single operand instructions. The num ———— Ste ber ofbus read and write cyctes is shownin pa- [tong 10) tart tanthosas as (i), The numberof lock par Nacd [bye ev) ati baropeiriiiiiedethrntahablart eed [byte word aoy aie mustbe added respectively to those of the of- ; | byte. word 410) Se fective address calculation where indicated. a [tong eo) saivzye Nor A Sco a1) [reve Tc) a OCC) TC TST [| byteword Tac) avo = (C1 NOTE: + add effective address calculation time July 26, 1986 an

‘Signetics Military Customer Specific Products. Product Specification 16-/32-Bit Microprocessor 68000 See ‘ShifvRotate Instruction Execution Times Table 29. Shift/Rotate Instruction Execution Times. Taverendcaus trarumbarotdockparode [WSTRUCTION [Swe | REGISTER [MEMORY] for the shift and rotate instructions. The num- bororbuc reececienueracete stoner | Bye, wort [6 enqvo) [ae | renthosas as (¢w). Tha numberof lock por a od andthe numberof read and wrtecyces |LSR ISL | bye.word | 6+ anv) | ane | (rust be added respectively to those of thee [~ eng [erent * alciatcn wherein ROR FOL | bye, word | evant) | __ ave | [ens | [= | ROKR, ROXL [eng 8 angn) NOTE: + add effective address calculation time nis the shift or rotate count Blt Manipulation Instruction Execution Table 30. Bit Manipulation Instruction Execution Times Times INSTRUCTION [____bvnamic stance Talo S0inccats the umberct lock poriods | mermveron | sz | roquied forthe bit manipulation insivefone, | Register [_Memery | Register | Memony_| The numberof bus read and wit cycos is [ere [= aie = [tee] showninparonthoses a ()Thenumber of | cysotmutbo nddecronpacaioyteee | SR | bre | = | ain | - | ee] cycles must be added respectively to those of byt tho effective adeross calclaton where nt [eng [youre = | iaeor [| cated. [ene [aie [ee] [eng [amr [| emer [| [= pep ae = [ong] eqn [ore = NOTES: + add effective calculation time * indicates maximum value Conditional instruction Execution Times Table 31. Conditional Instruction Execution Times ‘Table 31 indicates the number of clock periods BRANCH required for the conditional instructions. The | INSTRUCTION | DISPLACEMENT | BRANCH TAKEN number of bus read and write cycles is indi- Calodinparontosesas (vw) Tre numberot_| 856 a | clock periods andthe number freed and rio [word | s0)r2r20) cyeles must be added respectively those of [be 010) Seat tve adeross calculation where inc a a | cated, [= ee DBce [ec we = 00) [ec tals [toe ra(80) —] July 25, 1986 412

Table 32. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times

Table 34. Miscellaneous Instruction Execution Times Table 35. Move Peripheral Instruction Execution Times

‘Signetics Military Customer Specific Products Product Specification —_—e OO 16-/32-Bit Microprocessor 68000 Sn Miscellaneous instruction Execution Times Table 36. Exception Processing Tables 34 and 36 indicate the number of clock tion Times periods forthe following miscollancousinstuc. Execution Time: tions. The numberof bus readandwrite cycles. [ EXCEPTION —_—‘| PERIODS eae ce Norte naketieedcndents | —Aastesseror | sar) | clock periods plus the number of read andwrite cycles must be added to those ofthe attctive | Buseror | 6047) | address calculation where indicated. 44(5/4)+ a Exception Processing Execution Times Baap ‘Table 36 indicates the number of clock periods for exception processing. The umber ofclock | Interupt | 4at6ay | periods includes the time for all stacking,. the Privilege violation vector fetch, and the fetch of the first two in- stucionwordsofthehanderroutine.thenum- | RESET™ | 404600) _| berofbusreadandwriacydesisshowninpa- |" Trace | saa) _| a ‘onmoneees cn sa) TRAPY instruction 34(4/3) NOTES: + add effective address calculation time. * The interrupt acknowledge cycle is as- sumed to take four clock periods. ** Indicates the time from when RESET and ALT are first sampled as negated to whon instruction exocution stars, ABSOLUTE MAXIMUM RATINGS svupot [Panawerer [raring | unit | Supply voltage range [Fo | Maximum powor dissipation, (Po) [sw || teactomperatresoterng Seacondsy [270 |__| [ts | sunctontemperanre | tse |e: | Thomalresisiancejnciontocaso | 15,cvabinine | Sonw | [en | Thermal resistance, junction to ambient 90, gual n-ne NOTE: ‘This device contains circuitry to protect the inputs against damage due to high static voltages or eloctric fields; however, it is advised that normal precautions be taken to avoid application of any ‘voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of opera- tion is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND oF Voc). July 25, 1986 415

Signetics Military Customer Specific Products Product Specification 16-/32-Bit Microprocessor 68000 SSMS RECOMMENDED OPERATING CONDITIONS smeou[paRaweTeR SSSR i ee | vx [7 Hichievetineutvetage eniciputy 20m | Low level input veltage (ogc inputs) |__| Minimum righiovetouputvorsge eT |__| Masimumiowiovetouputvotage PT Frequency of operation: 68000-6 4.0106.0 68000-8 4018.0 68000—10 4.010 10.0 [eee DC ELECTRICAL CHARACTERISTICS Voc = 5.0VDC +5%; Tc =-55°C TO +110°C (s00 figures 42, 43, and 44) cs ~85°C<Te<+110°C, Vec=sv+5% [ Min | Max | UNIT | [Yow [Heinle al np [some f ewe || a ee od Toriowtaupavongences FCOzBE | Ta=sana[Weoremv | | 08 |v] [en [tow opi eins FATT [ex eténa[Vooearv | [os |v _ SC a a [es [Seen | Yeeesa a [| Vw =0V a a July 25, 1986 416

Signetics Military Customar Spocific Products Product Specification 16-/32-Bit Microprocessor 68000 Power Considerations The average chip-junction temperature, Ty, in ” ww °C can be obtained from: Ty= Tat (Pot, (0) Whaat * (Portia son nora Ta = ambient temperature, °C RESET vot 1a = package thermal resistance, junction-to-ambient, °C/W 130 Pp = pwr+Pvo T oF = 70pF Pwr = loc X Voo, watts-chip internal = + power Pyo_ = power dissipation on input and ‘output pins — user determined For most applications Pye<Pyr and can be Figure 42. HESET Test Load Figure 43. HALT Test Load neglected... ‘An approximate relationship between Pp and Ty (if Pyo is neglected) is: wv Po=K + (T1+273°C) @ Solving equations 1 and 2 for K gives: eso Remon = Tow °C) +0 nek ce rust i K = To®(Ta+279°C) +¢,ePo2 @) b+ Opts qu panasines) Foner OR EQUVALExT Were Kis constant pertaining tthe paricu- | m» aonn, TF ces lar part. Kcanbe determined from equation 3 by. P03, BOOS measuting Pp (at equilibrium) for a known Ts. | +R = 122k FOR ATIHoS, BG Foo-Fc2 CL ie Using this valueof Kthe values of Pp andT,can T bbe obtained by solving equations (1) and (2) it = + uoro0e eratively for any value of Tp. (OR EQUVALEN! Figure 45 ilustrtes the graphic solution to the ‘equations, given above, for the specification aa power dissipations of 1.50 and 1.75 watts over = the ambient temporatura range of ~85°C to 125°C using an average @ x of 40°C/W to rep- resent various 68000 packages. Figure 44. Test Loads However, actual @,,’s in the range of 30°C to 50°C/W only change the curves slightly. The tot bemalresstancoa package (Ou) 2ff TP Tet . Focal TT Trt can be separated into two components, Oc and $ou i ca, representing the barter to heat fow from t.esy_ftt ff ty te semicon jrcton fo the protage is OC (case) surface (8c) and from the case to the H “ [| LTT ‘outside ambient (Bca). These terms are related 12 ia {| by the equation: ry LI a Bin = Oxc+8ca (4) 4s 7 8 101s @,cis a device related and cannotbe influenced AMBIENT TEMPERATURE (Ta) °C the user. However, is user dependent eidcanboriazedoy thermalmanage- Figure 48. 68000 Power Dissipation (Pp) vs Amblent Temperature (Ta) ment tochniques as heat sinks, ambient air ‘cooling and thermal convention. Thus, good —_ Values for thermal resistance presented in this thermalmanagementonthepartoftheusercan —_data sheet are provided for design purposes significantly reduce Oc, so that O,, approxi- _ only. Thermal measurements are complex and mately equals 8c. Substitution of 8ycfor@jqin _ SOPeNdent on procedure and setup. User ‘equation (1) will result in a lower semiconductor derived values for thermal resistance may junction temperature. Gifier. July 25, 1986 4i7

1. Maximum Power Dissipation by Package Type Modes

Figure 46. Clock Input Timing Diagram

Signetics Military Customer Specific Products Product Specification SmratcaMian CutemerspeciePegets ee 46-/32-Bit Microprocessor 68000 a ee (AC ELECTRICAL CHARACTERISTICS'—Read and Write Cycles -55°C <7. -$+110°C (See Figures 47 and 48) al ied a esa [iain [wax [win [Max [ in [wax | a a a a ee a eS a en a Se ee ye ectaneamenremaimnima Te >-tet-el-[« | eee earners Dee imm ———t= Pe pe Pepe eye | [oe ea eer wr OS imo) [T= -f- t= t-te | ee a La ee [rece DS eiowtsiom) |e} —pe|-le[-| = | be [ee earns pep Pe a | Hite a ittawasnrtmaa ————et--e=t-tay-[e | Lea fas Seen ew eas ar = Poot pet [| Le a a a Le ee prstsiarenmngs = Pet fe-e | [ie | resme[CockrignwAWhighimaimom «t= * | | - | m [= [eo fn | [io | sounn | Gockrigno RWrigh nme «dt = | -— | - |= [= T= fo | a ae a a [Ea] wom [Fovidonew SCT mT fmm Pmt Te | Ee CT A a ee eee loco ean imei =f fT a a i Ee a a TO a [ee esnemannecm pot -tet-fel-[e| ees aetarwseme oe ef fe fT | Era | eae [otek oneal Samia = at opt | [sa [tur [FALTandRESETinpatwensiontme __—+| © | aw | 0 | ao0 | 0 | 200 | ne | a rc a a a Cs Ce CO ER Ca July 25,1986 a9

‘Signetics Military Customer Specific Products Product Specification ern Pret Spoiication 16-/32-Bit Microprocessor 68000 ee AC ELECTRICAL CHARACTERISTICS '—Read and Write les (Continued, [mf emnee CHARACTERISTIC _ ae [ win [wax | win [Mex | win [Max | [serie [eww [BRGh to EG hgh | a8 [ooo [a | a0 [08 | +00 |e per | [377 [ear [BGRCRIww BGI as [ns [as [ns [08 [NS [Ok por | [277 [worn [BEXCRIow w BRrih (oprveroatirasar) [aoe | 18 [ow | 18 | 20m | 18 [ok por | [22" | tax [tow eto ish impocance win Shan) [| - [woof - [| - | 70] om | a a BS [20 |e [Coskiowtomiow SSC PP Pw] fm] me | ER CS A [227 [eu [Eountisomnstanine Sd Pp | pe] [4" [tamen [WiRIowoenh «| wT = feo | - [mot - | | [2 [owen [AS DShightoVPRRGA |e [eo | o | ao] 0 [oo] me | [| ten [Eowoadsen mmronas its | - pm] - | ot-] «| a Sr A OS eB Sa RC SR 6 [er [tas [EtwioS Dimas «do me os ee |e [se _ [ex [wis igh feo aso [= a |e _| A [2 | teen |e omnsediootme = = = [ss [eco [Paahoaiemeoanon Po [Po [- fol] | [oer [ coe [Daahotttometowwiee ST - [|e t-[ | [5 [nso [Rifecaatusinpawarcosarae Sit | - |] -|o]-] | [ser [arm [RACTIRESET puso wan | | = | 1 | - | 0 | - [okom| [7 | erco |BERERTIGh oconetoosaeen as = ts Pf oe | foe] [se | tereo [BGhighto convotbusaiven st tS | - | 18 | - | 15] - [om per] NOTES: 1. After Voc has been applied for 100 ms. 2. All roe, unloaded except for load capacitance. Clock should be either 4MHz or Fuax. Low: HALT, RST, (Partis held in reset). High: , BR, BGACK, IPLO-2, VPA, BERR. ‘3. Guaranteed but not tested. 4. Voc =5Vt5% 5. After Voc has been applied for 100ms. 6. All rr aes, ‘except for load capacitance. Clock should be either 4MHz or Fwax. Low; ", RST, (Part is held in reset). High; DTACK, BR, BGACK, IPLQ-2, VPA, BERR. 7. As aminimum, tested initially and for process or design changes only. 8. For invalid, as a minimum, tested initially and for process and design changes only. ‘9. Fora loading capacitance of less than or equal to S0pF, subtract 5ns from the values given in the maximum column. 10. Combined with the above parameter. Previous specification of Ons was theoretical and not attainable. 11. Actual value depends on clock period. 12, For power up, the MPU must be held in RESET state for 100ms to all stabilization of ‘on-chip circuitry. After the system is powered up, 56 refers to the minimum pulse width required to reset the system. 13. Combined with 16, control bus specification 14, If 47 is satisfied for both DTACK and BERR, 48 may be Ons. 15. When AS and RAW are equally loaded (420%), subtract 10ns from the values given in these columns. 16. Deleted, useful only if E clock used to drive clock input on MC6809 Microprocessor. 17. If the asynchronous setup time (47) requirements are satisfied, the DTACK low to data ‘Setup time (#31) requirement can be ignored. ‘the data must only satisty the data in to clocktow ‘setup time (#27) for the following cycle. 18. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BTACK. July 25, 1986 420

functional description of the input and output. ‘signals. Refer to other | functional descriptions and their related diagrams for device operation.

1 Seti oe pynctvonous neue BOXTK PO, Po ngctewerce eae cock

Figure 47. Write Cycle Timing Diagram

Signetics Miltary Customer Specific Products Product Specification EE 16-/32-Bit Microprocessor 68000 ———SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSMMsse ‘These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation. ssi os ss es se oy © © ual © + r| PL © ge? a Oa im wae ee et 10, x Leto -|tseteioto_ re © @ cms eat I re Ire q Gi) cr “fo fret fh rack ® e l ® @) (| +] @ @ @ ® ‘nores) ® | @ ey @ mem rey "INPUTS ore) wores: 7 1 Mier Sa wr pan Sg ete Coo Sake es aaget 20 ues otherwise noted. The vokage swing through thie range should 2. Bocas of oadng varaons, 1 ray bm vas ter KS oven though behave bythe ty deo $2 (Spacain 204) | Figure 48. Write Cycle Timing Diagram (Continued) July 25, 1986 422

Figure 49. 68000 to M6800 Peripheral Timing Diagram — Best Case

‘Signetics Military Customer Specific Products Product Specification 16-/32-Bit Microprocessor 68000 San * pa™ ® ic) m @ @ a @ zB COR @ @ m TORE wx ne roo-rea asa oops Figure 51, Bus Arbitration Timing Diagram — Idle Bus Case July 25, 1986 425

Figure 52. Bus Arbitration Timing Diagram — Multiple Bus Requests

NAPC/ SIGNETICS/MILITARY 20 D MM 6653926 OOOlli1 3 Mm | inf ti T:40-20 Military Products SIGNETICS STANDARD Acase outline suffix number is jassignodherein @ Ceramic: Chip Carriers; tiple laminated, PACKAGE DESCRIPTIONS for identieaton purposes erly; andl et mea-idded LCC (G package family) wth iB con current rei ‘Signetics Military products areoffered inawide © Pin Grid Array; metal-idded ceramic pin MIL-M-38510, Appandix C, except for package _ pen wch are ret nuded nat pete tango o package configurations to opimaly Ft rd (P package family) with 68-100 leads ion. ‘© Shown in Table 1 are the case outline let- ‘The physical dimensions for standard package © Dual-in-line Packages; Frit glass sealed tors assigned according to Appendix C of ‘types which are not included nAppendix © ae CERDIP (F package family) with 840 MIL-M-38510 and JEDEC publication 101. Included herein In Appendix C format. Case leads, and side-brazed ceramis (| package ‘Unless otherwise noted, all package types ‘outline lettors are assigned to these packages familly) with 48-64 leads. ‘are Configuration 1 and all lead finishes aro according to JEDEC Publication 101 as follows: . hot solder dip Finish "A. U: Loadtess chip carriers © Flat Packages; Frit glass sealed alumina X: Dual-in-line packages: CERPAC (W package familly) with 14-28 Y: Flatpackages feads, and brazed leaded ceramic (Q pack- Z: Allother configurations: ‘age family) with 52 leads. Table 1. Pacagebesipon | pew | GavOutne ‘| Toemvoveumnt | 8DIPS D4 P 28 14D1P3. Pol Cc 28 16DIPS. 0-2 E 28 18DIP3 0-6 v 28° 20DiP3 0-8 aR 28 ‘2201P4 o-7 Ww 2 24DIP3 D-9 L 23 2aDIP4 D-11 x 28 24DIP6 D3 J 2B 280IP6 DA0 x 28 40DIP6 oS Q 28 48DiP6 D-t4! x 23 SODIPS O-12! x . 28 64DIPO D-13" . bg 28 14FLAT F-2 D 22 16FLAT ES F 22 18FLAT F-10 ye 22 ‘20FLAT F-9 s 2 24FLAT F6 K 22 20FLAT Feit ye 22 ‘S2FLAT yet! Va 2 Tacs C8, v 2 20LLeo oe 2 2 2aLLCc ca 3 20 32LLoc C12 we 20 4autec cs ve 2 68LLCG o7 ue 20 ‘68PGA P-AB S 84PGA P-AB 2 NOTES: 1. Configuration 2. 2. PerJEDEC publication 101, 8. Dimension A (LLCG thickness) is 7Smils maximum. 4. See RADG test report RADC-TR-£6-97 for thermal resistance confidence and derating. January 1990 9

NAPC/ SIGNETICS/MILITARY 20 D M@ 6653526 0001112 5 Signotics Miltary Products T- 90 -20 7 _- - Packaging Information a CASE OUTLINES Y (FLAT PACKAGES) D . A ‘ s >| SEE i + SEE + NOTE 4] & g NOTE 1 E ESS En 7 Hy L L ¢ kK e 8 a je s s| a} seats 4 Configuration 1 Configuration 2 1. Alead tab (enlargement) or index dot Is located within the shaded area shown at Pin 1. Other pin numbers proceed | conriaunation | 2 _—| Sequentially rom Pin 1 counterclockwise (as viewed from the 2. This dimension allows for off-center id, meniscus, and glass NOTES 8. The reference pin spacing Is 0.050 between centerlines, Each pin centerline is located within + 0,005 of is logitudinal [__wenes | sition relative to the fist and last pin numbers. 4. This dimension le measured altho port of ext ofthe lead SYMBOL [win | wax _| body. 5. This dimension applied to all four comer pins, A 0.045 0.100 6. Lead dimensions include 0,003 inch allowance for hot solder b 0015 | 0.026 6 Sp oad trish. © 0.008 0.015, 6 D 1.330 2 E 0.620 | 0.660 e 0.050 BSC 3 L 0.250 | 0370 Q 0.054 | 0.0666: 4 8 - 0.045 5 : st 0.005 : 5 January 1990 10 2 a)

NAPC/ SIGNETICS/MILITARY 20 D MM 6653926 0001113 7 mm ‘Signotics Military Products —_ =. 7-90-40 ; Packaging Information eee EEO ees aaasa_0_>saaam> (CASE OUTLINES X (DUAL IN-LINE PACKAGES) A A ai seeyores ek seenores ae ae an FE Fz t T : : i —— ee — a Pa Coniguration 4 Contiguation 2 1. An index notch Is located within the shaded area shown. Pin 1 Is adjacent to the notch to the immediate left (as viewed from the top of the device) and other pin numbers proceed sequentially from Pin 1 counterclockwise. 2, The minimum limit for Dimension b1 Is 0.023 inches for all four corner pins. 3, This dimension allows for off-center lid, meniscus, and glass overrun. 4, This dimenston is measured at the centerline of the leads for Configuration 2. 5. The reference pin spacing is 0.100 between centerlines. Each pin ‘centerline is located within +0.010 of its longitudinal position relative to the first and last pin numbers. 6, This dimension is measured from the seating plane to the base plane. 7. This dimension applies to all four corner pins. 8. Lead dimensions include 0,003 inch allowance for hot solder dip lead finish. January 1990 a

NAPC/ SIGNETICS/MILITARY 20D MM bbS3424 o001ll4 4 —- ‘Signetics Military Products Tr 0 : : Packaging Information 2 ot 70-20 LEADLESS CHIP CARRIER (LLCC) PINOUTS OOO OOO @@QQOOO ogofofofafofa| ofefofofafofo| @B a@ QB a® Qa a® Qa a0) Ou a® Ow a® ve [3] ing gs BQ @s 210) Ow a@ Ou a@ @a A® Ou a@® On a@ Ge) le el a le (TOP VIEW) (TOP VIEW) (24-Lead Logle Pinout for 26 Terminal Chip Carrier 26-Lead Pinout for 28 Terminal Chip Carrier. for all Device Types OOO“ OOO QOO“ OOO faqofofofafape| fafofofafafofa] Chi Bi et et eS, On a® @a ty "TarO) @n ao out = Taro) gs an ve 1) x @ a®@ eu Tel) @a a@ us i a1G) ou a© veo "Jelo) LRARA RA AY olyale]=|a) eyyayayoyale) O@@” OOO OOOLIO OO) (TOP VIEW) (TOP VIEW) 24-Leed Memory Pinout for 28 Terminal Chip Carrier 22-Lead Memory Pinout for 28 Terminal Chip Carrier C1 hip cat er Ranta O = Dual In-Line Lead Number Rochoconea January 1990 12 Se . im