FAN6754 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
High-Voltage Startup AC Input Brownout Protection with Hysteresis Low Operating Current: 1.7mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 13V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Open-Loop Protection (OLP); Restart for MR, Latch for ML Built-in 8ms Soft-Start Function Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters
Description
The highly integrated FAN6754 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency under light-load conditions. Under zero-load and very light-load conditions, FAN6754 saves PWM pulses by entering deep burst mode. This burst mode function enables the power supply to meet international power conservation requirements. FAN6754 integrates a frequency-hopping function internally to reduce EMI emission of a power supply with minimum line filters. Built-in synchronized slope compensation is accomplished by, proprietary internal compensation for constant output power limit over universal AC input range. Also, the gate output is clamped at 13V to protect the external MOSFET from over-voltage damage. Other protection functions include AC input brownout protection with hysteresis and V DD over-voltage protection. For over-temperature protection, an external NTC thermistor can be applied to sense the external switcher’s temperature. When V DD OVP or OTP are activated, an internal latch ci rcuit is used to latch-off the controller. The latch mode is reset when the V DD supply is removed. FAN6754 is available in an 8-pin SOP package.
Ordering Information
Status Package Packing Method FAN6754MRMY -40 to +105°C RoHS 8-Pin, Small Outline Package (SOP) Tape & Reel FAN6754MLMY -40 to +105°C RoHS 8-Pin, Small Outline Package (SOP) Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Figure 3. Top Mark Figure 4. Pin Configuration (Top View) placed between VDD and GND is recommended. threshold voltage (around 4.6V) for more than 55ms, the controller latches off the PWM. cycle-by-cycle current limiting to achieve cons tant output power limiting with universal input. Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND. drops below the threshold voltage, the controller latches off the PWM.
7 VDD
Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. turn-on and turn-off is 16.5V and 9V, respectively. The operating current is lower than 2mA.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754 • Rev. 1.0.0 4 FAN6754 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VVDD DC Supply Voltage (1, 2) 30 V VFB FB Pin Input Voltage -0.3 7.0 V VSENSE SENSE Pin Input Voltage -0.3 7.0 V VRT RT Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW ΘJA Thermal Resistance (Junction-to-Air) 141 °C/W TJ Operating Junction Temperature -40 +125 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C Human Body Model, JEDEC:JESD22-A114 4.5 kV ESD Charged Device Model, JEDEC:JESD22-C101 1500 V Notes: 1. All voltage values, except differential voltages, ar e given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximu m Ratings may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Typ. Max. Unit TA Operating Ambient Temperature -40 +105 °C RHV HV Startup Resistor 150 200 k Ω
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754 • Rev. 1.0.0 5 FAN6754 — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 24 V VDD-ON Start Threshold Voltage 15.5 16.5 17.5 V VDD-OFF Minimum Operating Voltage 8 9 10 V VDD-OLP I DD-OLP Off Voltage 5.5 6.5 7.5 V VDD-LH Threshold Voltage on VDD Pin for Latch-Off Release Voltage 3.5 4.0 4.5 V VDD-AC Threshold Voltage on VDD Pin for Disable AC recovery to avoid Startup Failed V DD-OFF +2.5 VDD-OFF +3.0 VDD-OFF +3.5 V IDD-ST Startup Current V DD-ON – 0.16V 30 µA IDD-OP1 Operating Supply Current when PWM operation VDD=20V, FB=3V Gate Open 1.7 2.0 mA IDD-OP2 Operating Supply Current when Gate Stop VDD=20V, FB=3V 1.2 1.5 mA ILH Operating Current at PWM-Off Phase Under Latch-Off Conduction V DD=5V 30 60 90 µA IDD-OLP Internal Sink Current under Latch- Off Conduction VDD-OLP+0.1V 180 210 240 µA VDD-OVP V DD Over-Voltage Protection 24 25 26 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 75 165 255 µs HV Section IHV Supply Current from HV Pin VAC=90V(VDC=120V), VDD=0V 1.50 2.75 4.00 mA VAC-OFF Brownout Threshold DC Source Series R=200kΩ to HV Pin See Equation 1 92 102 112 V VAC-ON Brownin Threshold (Eq.2) DC Source Series R=200kΩ to HV Pin See Equation 2 104 114 124 V △VAC VAC-ON - VAC-OFF DC Source Series R=200kΩ to HV Pin 6 12 18 V FB > VFB-N 220 tS-CYCLE Line Voltage Sample Cycle FB < VFB-G 650 μs tH-TIME Line Voltage Hold Period 20 μs FB > VFB-N 65 75 85 ms tD-AC-OFF PWM Turn-off Debounce Time FB < VFB-G 180 235 290 ms Continued on the following page…
VDD=15V and TA=25°C unless otherwise noted. Figure 8. V
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754 • Rev. 1.0.0 8 FAN6754 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Feedback Input Section Current-Sense Section tPD Delay to Output 100 250 ns tLEB Leading Edge Blanking Time 230 280 330 ns Vlimit-L Current Limit at Low Line (V AC=86V) VDC=122V, Series R=200kΩ to HV 0.43 0.46 0.49 V Vlimit-H Current Limit tat High Line (V AC=259V) VDC=366V, Series R=200kΩ to HV 0.36 0.39 0.42 V tSS Period During Soft-Start Time Startup Time 7 8 9 ms GATE Section DCYMAX Maximum Duty Cycle 86 89 92 % VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V tr Gate Rising Time V DD=15V, CL=1nF 100 ns tf Gate Falling Time V DD=15V, CL=1nF 50 ns VGATE- CLAMP Gate Output Clamping Voltage V DD=22V 9 13 17 V RT Section RRT Internal Resistor from RT Pin 9.50 10.55 11.60 K Ω VRTTH1 0.7V ＜ VRT ＜ 1.05V, after 12ms Latch Off 1.000 1.035 1.070 V VRTTH2 Over-Temperature Protection Threshold Voltage VRT ＜ 0.7V, After 100µs Latch Off 0.65 0.70 0.75 V VRTTH2 ＜ VRT ＜ VRTTH1 FB > VFB-N 14 16 18 tD-OTP1 VRTTH2 ＜ VRT ＜ VRTTH1 FB < VFB-G 40 51 62 ms VRT< VRTTH2 FB > VFB-N 110 185 260 tD-OTP2 Over-Temperature Latch-Off Debounce VRT< VRTTH2 FB < VFB-G 320 605 890 µs Over-Temperature Protection Section (OTP) TOTP Protection Junction Temperature +135 °C TRestart Restart Junction Temperature T OTP-25 °C
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754 • Rev. 1.0.0 11 FAN6754 — Highly Integrated Green-Mode PWM Controller Functional Description Startup Current For startup, the HV pin is connected to the line input through an external diode and resistor; R HV, (1N4007 / 150KΩ recommended). Peak startup current drawn from the HV pin is (VAC× 2 ) / R HV and charges the hold-up capacitor through the diode and resistor. When the V DD capacitor level reaches V DD-ON, the startup current switches off. At this moment, the V DD capacitor only supplies the FAN6754 to keep the V DD until the auxiliary winding of the main transformer provides the operating current. Operating Current Operating current is around 1.7mA. The low operating current enables better efficiency and reduces the requirement of V DD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. V FB, which is derived from the voltage feedback loop, is taken as the reference. Once V FB is lower than the threshold voltage (V FB-N), switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and V FB, the feedback voltage. When the voltage on the SENSE pin reaches around V COMP = (VFB–0.6)/4, the switch cycle is terminated immediately. V COMP is internally clamped to a variable voltage around 0.46V for low-line output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V and 9V, respectively. During startup, the hold- up capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply V DD until the energy can be delivered from auxiliary winding of the main transformer. V DD must not drop below 9V dur ing startup. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6754 inserts a synchronized, positive-going, ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage across sense resistor R SENSE reaches the threshold voltage, around 0.46V for low-line condition, the output GATE drive is turned off after a small delay, t PD. This delay introduces an additional current proportional to t PD • VIN / L P. Since the delay is nearly constant regardless of the input voltage V IN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by the HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the current limiting comparator. This results in a lower current limit at high- line inputs than at low-line inputs. Brownout and Constant Power Limited by HV Pin Unlike previous PWM controllers, FAN6754’s HV pin can also detect the AC line voltage brownout function and set the current limit level. Using a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and is stored in a register at each sampling cycle. When internal update time is met, this peak value is used for brownout and current-limit level judgment. Equation 1 and 2 calculate the level of brownin or brownout converted to RMS value. For power saving, FAN6754 enlarges the sampling cycle to lower the power loss from HV sampling at light load condition. 2 / ) 1.6 1.6) (R 0.9V ( (RMS) V HV ON- AC +×= (1) Ω+×= kis R of unit the ; 2 / ) 1.6 1.6) (R 0.81V ( (RMS) V HV HV OFF- AC (2)
Figure 25. Linearly Current Limit Curve turned off, VDD begins decreasing. power MOS gate resistance improve performance.
B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
Figure 26. 8-Pin SOP-8 Package specifically the warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754 • Rev. 1.0.0 14 FAN6754 — Highly Integrated Green-Mode PWM Controller