SG6742HR_HL FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
High-Voltage Startup Low Operating Current: 2.7mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 100KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Internal-Sense, Short-Circuit Protection Built-in 6ms Soft-Start Function Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS
Description
The highly integrated SG6742HL/HR PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. To further reduce power consumption, SG6742HL/HR is manufactured using the BiCMOS process, which allows an operating current of 2.7mA. SG6742HL/HR integrates a frequency-hopping function internally that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary, internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90V AC to 264VAC. SG6742HL/HR provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until V DD drops below the UVLO lower limit, when the controller starts up again. As long as V DD exceeds ~25V, the internal OVP circuit is triggered. SG6742HL/HR is available in an 8-pin SOP package.
Ordering Information
SG6742HLSY -40 to +105°C Latch 8-Lead Small Outline Package (SOP) Green Tape & Reel SG6742HRSY -40 to +105°C Restart 8-Lead Small Outline Package (SOP) Green Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 4 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VVDD DC Supply Voltage (1, 2) 30 V VFB FB Pin Input Voltage -0.3 7.0 V VSENSE SENSE Pin Input Voltage -0.3 7.0 V VRT RT Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW ΘJA Thermal Resistance (Junction-to-Air) 141 °C/W TJ Operating Junction Temperature -40 +125 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C Human Body Model, JEDEC:JESD22-A114 All pins except HV pin 4.0 ESD Charged Device Model, JEDEC:JESD22-C101 All pins except HV pin 1.5 kV Notes: 1. All voltage values, except differential voltages, ar e given with respect to the network ground terminal. 2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 5 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 22 V VDD-ON Start Threshold Voltage 14.5 15.5 16.5 V VDD-OFF Minimum Operating Voltage 8.5 9.5 10.5 V IDD-ST Startup Current V DD-ON – 0.16V 30 µA IDD-OP Operating Supply Current V DD=15V, GATE Open 2.7 3.7 mA IDD-OLP Internal Sink Current VTH-OLP+0.1V 30 60 90 µA VTH-OLP I DD-OLP off Voltage 6.5 7.5 8.0 V VDD-OVP V DD Over-Voltage Protection 24 25 26 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 75 125 200 µs HV Section IHV Supply Current from HV Pin VAC=90V (VDC=120V), VDD=0V 1.75 2.30 3.35 mA IHV-LC Leakage Current After Startup HV=500V, VDD=VDD- OFF+1V 1 20 µA Oscillator Section Center Frequency 90 100 110 fOSC Frequency in Normal Mode Hopping Range ±4.2 ±4.7 ±5.2 KHz tHOP Hopping Period 4.9 5.6 6.3 ms fOSC-G Green-Mode Frequency 18 22 25 KHz fDV Frequency Variation vs. VDD Deviation VDD=11V to 22V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to 105°C 5 % Continued on the following page… Figure 5. V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 6 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Feedback Input Section AV Input Voltage to Current-Sense Attenuation 1/4.15 1/4.00 1/3.85 V/V ZFB Input Impedance 4 7 k Ω VFB-OPEN Output High Voltage FB Pin Open 5.2 V VFB-OLP FB Open-Loop Trigger Level 4.6 4.8 5.0 V tD-OLP Delay Time of FB Pin Open-loop Protection 50 56 62 ms VFB-N Green-Mode Entry FB Voltage 3.1 3.3 3.5 V VFB-G Green-Mode Ending FB Voltage VFB-N- 0.5 V VFB-ZDC Zero Duty-Cycle Input Voltage 1.6 V Current-Sense Section ZSENSE Input Impedance 12 K Ω VSTHFL Current Limit Flatten Threshold Voltage Duty cycle=45% 0.97 1.00 1.03 V VSTHVA Current Limit Valley Threshold Voltage V STHFL–VSTHVA 0.27 0.30 0.33 V tPD Delay to Output 100 200 ns tLEB Leading-Edge Blanking Time 100 140 180 ns VS-SCP Threshold Voltage for SENSE Short- Circuit Protection 0.10 0.15 0.20 V tD-SSCP Delay Time for SENSE Short-Circuit Protection VSENSE<0.15V 100 150 200 µs tSS Period During Soft-Startup Time Startup Time 5 6 7 ms GATE Section DCYMAX Maximum Duty Cycle 60 65 70 % VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V tr Gate Rising Time V DD=15V, CL=1nF 150 250 350 ns tf Gate Falling Time V DD=15V, CL=1nF 30 50 90 ns IGATE- SOURCE Gate Source Current V DD=15V, GATE=6V 250 mA IGATE-SINK Gate Sink Current V DD=15V, GATE=1V 300 mA VGATE- CLAMP Gate Output Clamping Voltage V DD=22V 18 V RT Section RRT Internal Resistor from RT Pin 10.08 10.50 10.92 K Ω VRTTH1 0.7V ＜ VRT ＜ 1.05V, After 12ms Latch Off 1.015 1.050 1.085 V VRTTH2 Over-Temperature Protection Threshold Voltage VRT ＜ 0.7V, After 100µs Latch Off 0.65 0.70 0.75 V tD-OTP1 V RTTH2 ＜ VRT ＜ VRTTH1 16 20 24 ms tD-OTP2 Over-Temperature Latch-off Debounce VRT< VRTTH2 90 130 170 µs Over-Temperature Protection Section (OTP) TOTP Protection Junction Temperature (3) +135 °C TRestart Restart Junction Temperature (4) T OTP-25 °C Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output agai n and resetting the latch after OTP has been activated.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 9 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller Functional Description Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, R HV, (1N4007 / 100K Ω recommended). Typical startup current drawn from pin HV is 2.3mA and charges the hold-up capacitor through the diode and resistor. When the V DD capacitor level reaches V DD-ON, the startup current switches off. At this moment, the V DD capacitor only supplies the SG6742HL/HR to keep the V DD before the auxiliary winding of the main transformer to provide the operating current. Operating Current Operating current is around 2.7mA. The low operating current enables better efficiency and reduces the requirement of V DD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides an off- time modulation to reduce the switching frequency in the light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. V FB, which is derived from the voltage feedback loop, is taken as the reference. Once V FB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and V FB, the feedback voltage. When the voltage on SENSE pin reaches around V COMP=(VFB–0.6)/4, a switch cycle is terminated immediately. V COMP is internally clamped to a variable voltage around 0.85V for output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 15.5V and 9.5V. During startup, the hold-up capacitor must be charged to 15.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply V DD before the energy can be delivered from auxiliary winding of the main transformer. V DD must not drop below 9.5V during this st artup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 6ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode cont rol and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6742HL/HR inserts a synchronized positive-going ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage, across the sense resistor R S, reaches the threshold voltage, around 1V, the output GATE drive is turned off after a small delay, t PD. This delay introduces an additional current proportional to t PD • V IN / L P. Since the delay is nearly constant regardless of the input voltage V IN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. VDD Over-Voltage Protection (OVP) VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. If the V DD voltage is over the over-voltage protection voltage (V DD-OVP) and lasts for t D-VDDOVP, the PWM pulses are disabled until the V DD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 10 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller Functional Description (Continued) Thermal Protection An NTC thermistor, R NTC, in series with a resistor R A, can be connected from the RT pin to ground. A constant current I RT is output from the RT pin. The voltage on the RT pin can be expressed as V RT = IRT • (RNTC + R A), where I RT is 100µA. At high ambient temperatures, RNTC is smaller, such that V RT decreases. When V RT is less than 1.05V (V RTTH1), the PWM turns off after 20ms (t D-OTP1). If VRT is less than 0.7V (V RTTH2), PWM turns off immediately after 130µs (t D-OTP2). Limited Power Control The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than t D-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. When VDD goes below the turn-off threshold (~9.5V) the controller is totally shut down. V DD is charged up to the turn-on threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. When V RT is less than 1.05V (V RTTH1), the PWM is turned off after 20ms (tD-OTP1). If VRT is less than 0.7V (V RTTH2), PWM is turned off immediately after 130µs (tD-OTP2). Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6742HL/HR, and increasing the power MOS gate resistance improve performance.
Figure 21. 60W Flyback 12V/5A Application Circuit
B) ALL DIMENSIONS ARE IN MILLIMETERS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
1.75 MAX
Figure 22. 8-Pin SOP-8 Package specifically the warranty therein, which covers Fairchild products.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com SG6742HL/HR • Rev. 1.0.4 13 SG6742HL/HR — Highly Integrated Green-Mode PWM Controller