670M-03ILF

670M-03ILF IDT | Alldatasheet

Document overview

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Technical content

Features

• Packaged in 16-pin SOIC
• Pb (lead) free package, RoHS compliant
• Clock inputs from 5 to 210 MHz (see page 2)
• Patented PLL with low phase noise
• Output clocks up to 210 MHz at 3.3V
• 15 selectable on-chip multipliers
• Power down mode available
• Low phase noise: -124 dBc/Hz at 10 kHz
• Output enable function tri-states outputs
• Low jitter 15 ps one sigma
• Advanced, low power, sub-micron CMOS process
• Industrial temperature rated
• Operating voltage of 3.3 V or 5 V Block Diagram Divide by N Voltage Controlled Oscillator FBCLK OE1 Phase Detector, Charge Pump, and Loop FilterFBIN S3:S0 ICLK CLK24 OE2 VDD GND External Feedback from FBCLK is recommended.

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 2 ICS670-03 REV J 051310 Pin Assignment Multiplier Select Table Pin Descriptions VDD VDD VDD GND CLK2 OE2 GND FBCLK S3OE1 ICLK FBIN GND S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz)

0000 L o w ( P o w e r d o w n

entire chip) 0001 I n p u t x 1 . 3 3 3 1 8 - 157.5

0010 I nput x6 5 - 35

0011 I n p u t x 1 . 5 1 6 . 6 7 - 1 4 0 0100 I n p u t x 3 . 3 3 3 7 . 5 - 6 3 0101 I n p u t x 2 . 5 0 1 0 - 8 4 0110 I nput x4 6 - 52.5

0111 I nput x1 25 - 210

1000 I n p u t x 2 . 3 3 3 1 1 - 9 0 1001 I n p u t x 2 . 6 6 6 1 0 - 7 8 . 7 5 1010 I nput x12 5 - 17.5

1011 I nput x3 8 - 70

1100 I nput x10 5 - 21

1101 I nput x5 6 - 42

1110 I nput x8 5 - 26.25

1111 I nput x2 12 - 105

1 - 3 VDD Input Power supply. Connect both pins to the same voltage (either 3.3 V or 5 V). 4 CLK2 Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 5 OE2 Input Output clock enable 2. Tri-states the clock 2 output when low. 6 FBCLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low. 8 FBIN Input Feedback clock input. 9 ICLK Input Clock input. Connect to a 5 - 210 MHz clock. 10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up. 11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up. 12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up. 13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up. 14 - 16 GND Power Connect to ground.

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 3 ICS670-03 REV J 051310 External Components The ICS670-03 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01mF should be connected between VDD (pins 1, 2, and 3) and GND (pins 14, 15, and 16), as close to the device as possible. A series termination resistor of 33Ω may be used to each clock output pin to reduce reflections. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS670-03. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions VDD=3.3V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 5.5 V Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = 12 mA 0.4 V Output High Voltage, CMOS level VOH IOH = -4 mA VDD-0.4 V Operating Supply Current IDD No Load 35 mA

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 4 ICS670-03 REV J 051310 VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C, unless stated otherwise Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load on CLK2. See graph on page 5 for skew vs. frequency and loading. Thermal Characteristics Short Circuit Current I OS Each output ±50 mA Internal Pull-up Resistor R PU OE, select pins 200 k Ω Input Capacitance C IN OE, select pins 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency f IN See table on page 2 5 210 MHz Output Clock Frequency 210 MHz Output Rise Time t OR 0.8 to 2.0 V, no load 1.5 ns Output Fall Time t OF 2.0 to 0.8 V, no load 1.5 ns Output Clock Duty Cycle t DC measured at VDD/2 40 50 60 % Input to Output Skew Note 1 ±100 ps Maximum Absolute Jitter short term ±45 ps Maximum Jitter one sigma 15 ps Phase Noise, relative to carrier, 125 MHz (x5)

100 Hz offset -110 dBc/Hz

Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 120 ° C/W θJA 1 m/s air flow 115 ° C/W θJA 3 m/s air flow 105 ° C/W Thermal Resistance Junction to Case θJC 58 ° C/W

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 6 ICS670-03 REV J 051310 Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 670M-03ILF 670M-03ILF Tubes 16-pin SOIC -40 to +85 ° C 670M-03ILFT 670M-03ILF Tape and Reel 16-pin SOIC -40 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 9.80 10.00 .3859 .3937 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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