ICS670-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 8

Technical content

Features

  • Packaged in 16-pin SOIC
  • Pb (lead) free package, RoHS compliant
  • Clock inputs from 5 to 160 MHz (see page 2)
  • Patented PLL with low phase noise
  • Output clocks up to 160 MHz at 3.3 V
  • 15 selectable on-chip multipliers
  • Power down mode available
  • Low phase noise: -124 dBc/Hz at 10 kHz
  • Output enable function tri-states outputs
  • Low jitter–15 ps one sigma
  • Full swing CMOS outputs with 25 mA drive capability at TTL le vels
  • Advanced, low power, sub-micron CMOS process
  • Industrial temperature version available
  • Operating voltage of 3.3 V or 5 V Block Diagram Voltage Controlled Oscillator FBCLK OE1 Phase Detector, Charge Pump, and Loop FilterFBIN S3:S0 ICLK CLK24 OE2 VDD GND External Feedback from FBCLK is recommended. ROM- Based Multipliers

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 2 ICS670-01 REV L 012315 Pin Assignment Multiplier Select Table Pin Descriptions VDD VDD VDD GND CLK2 OE2 GND FBCLK S3OE1 ICLK FBIN GND S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz)

0000 L o w ( P o w e r d o w n e n t i r e

chip) 0001 I nput x1.333 18 - 120 0010 I n p u t x 6 5 - 2 6 . 6 7 0011 I nput x1.5 16.67 - 107 0100 I nput x3.333 7.5 - 48 0101 I nput x2.50 10 - 64

0110 I n p u t x 4 6 - 4 0

0111 I n p u t x 1 2 5 - 1 6 0

1000 I nput x2.333 11 - 69 1001 I nput x2.666 10 - 60 1010 I n p u t x 1 2 5 - 1 3 . 3 3 1011 I n p u t x 3 8 - 5 3 . 3 3

1100 I n p u t x 1 0 5 - 1 6

1101 I n p u t x 5 6 - 3 2

1110 I n p u t x 8 5 - 2 0

1111 I n p u t x 2 1 2 - 8 0

1 - 3 VDD Input Power supply. Connect all pins to the same voltage (either 3.3 V or 5 V). Pins 1 and 2 supply the analog sections of the chip. 4 CLK2 Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 5 OE2 Input Output clock enable 2. Tri-states the clock 2 output when low. 6 FBCLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low. 8 FBIN Input Feedback clock input. 9 ICLK Input Clock input. Connect to a 5 - 210 MHz clock. 10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up. 11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up. 12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up. 13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up. 14 - 16 GND Power Connect to ground.

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 3 ICS670-01 REV L 012315 External Components The ICS670-01 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected from each VDD pin to the ground plane, as close to the device as possible. A series termination resistor of 33 should be used to each clock output pin. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS670-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions VDD=3.3V ±10%, Ambient temperature -40 to +85C, unless stated otherwise Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 C Ambient Operating Temperature, ICS670-01I -40 to +85 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 5.5 V Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = 12 mA 0.4 V Output High Voltage, CMOS level VOH IOH = -4 mA VDD-0.4 V Operating Supply Current IDD No Load 35 mA Short Circuit Current I OS Each output ±50 mA Internal Pull-up Resistor R PU OE, select pins 200 k  Input Capacitance C IN OE, select pins 5 pF

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 4 ICS670-01 REV L 012315 VDD = 3.3V ±10%, Ambient Temperature -40 to +85C, unless stated otherwise Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load on CLK2. See graph on page 5 for skew vs. frequency and loading. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency f IN See table on page 2 5 160 MHz Output Clock Frequency 160 MHz PLL Stabilization Time t STAB Input frequency 5 MHz to 160 MHz 4 10 µs Output Rise Time t OR 0.8 to 2.0 V, no load 1.5 ns Output Fall Time t OF 2.0 to 0.8 V, no load 1.5 ns Output Clock Duty Cycle t DC measured at VDD/2 45 50 55 % Input to Output Skew Note 1 ±100 ps Maximum Absolute Jitter short term ±45 ps Maximum Jitter one sigma 15 ps Phase Noise, relative to carrier, 125 MHz (x5)

100 Hz offset -110 dBc/Hz

Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 120 C/W JA 1 m/s air flow 115 C/W JA 3 m/s air flow 105 C/W Thermal Resistance Junction to Case JC 58 C/W

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 6 ICS670-01 REV L 012315 Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Revision History

Part / Order Number Marking Shipping Packaging Package Temperature 670M-01LF 670M-01LF Tubes 16-pin SOIC 0 to +70  C 670M-01LFT 670M-01LF Tape and Reel 16-pin SOIC 0 to +70  C 670M-01ILF 670M-01ILF Tubes 16-pin SOIC -40 to +85  C 670M-01ILFT 670M-01ILF Tape and Reel 16-pin SOIC -40 to +85  C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 9.80 10.00 .3859 .3937 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 Rev. Date Originator Description of Change L 01/23/15 RDW Updated AC characterization table with new parameter "PLL Stabilization Time".

© 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS670-01 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.