NTB65N02R_05 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Planar HD3e Process for Fast Switching Performance
  • Low R DSon to Minimize Conduction Loss
  • Low C iss to Minimize Driver Loss
  • Low Gate Charge
  • Pb−Free Packages are Available* MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip Continuous @ TC =25°C, Limited by Package Single Pulse (tp = 10 s) R JC PD ID ID IDM 2.0 62.5 160 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C R JA PD ID 1.86 °C/W W A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C R JA PD ID 120 1.04 7.6 °C/W W A Operating and Storage Temperature Range TJ and Tstg −55 to 150 Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, IL = 11 Apk, L = 1 mH, RG = 25 ) EAS 60 mJ Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in 2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. AYWW P65N02RG http://onsemi.com TO−220AB CASE 221A STYLE 5 MARKING DIAGRAMS 65N02R = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package D 2PAK CASE 418AA STYLE 2 D S G AYWW 65N02RG 1 2 3 24 V 8.4 m @ 10 V R DS(on) TYP 65 A ID MAXV(BR)DSS PIN ASSIGNMENT PIN FUNCTION Gate

2 Drain

3 Source

4 Drain

See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

NTB65N02R, NTP65N02R http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS 27.5 25.5 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS 1.5 Adc Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS − − ±100 nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS , ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 1.5 4.1 2.0 Vdc mV/°C Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 30 Adc) R DS(on) 11.2 8.4 8.2 12.5 10.5 m Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 15 Adc) gFS − 27 − Mhos DYNAMIC CHARACTERISTICS Input Capacitance C iss − 948 1330 pF Output Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) C oss − 456 640 Transfer Capacitance ( DS dc, GS ,) C rss − 160 225 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time td(on) − 7.0 − ns Rise Time (VGS = 10 Vdc, VDD = 10 Vdc, tr − 53 − Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 30 Adc, RG = 3) td(off) − 14 − Fall Time tf − 10 − Gate Charge Q T − 9.5 − nC (VGS = 4.5 Vdc, ID = 30 Adc, VDS = 10 Vdc) (Note 3) Q 1 − 3.0 −VDS = 10 Vdc) (Note 3) Q 2 − 4.4 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) VSD − 0.88 1.2 VdcForward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 30 Adc, VGS = 0 Vdc) (I 15 A V 0V T 125°C) VSD − 0.88 1.10 08 0 1.2 Vdc (S dc, GS dc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C) − 0.80 − Reverse Recovery Time trr − 29.1 − ns (IS =3 0Ad VGS =0V d ta − 13.6 − (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3) tb − 15.5 − Reverse Recovery Stored Charge S )( ) Q RR − 0.02 − C 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures.

NTB65N02R, NTP65N02R http://onsemi.com Figure 12. Thermal Response Device Package Shipping† NTB65N02R D 2PAK 50 Units / Rail NTB65N02RG D 2PAK (Pb−Free)

50 Units / Rail

NTB65N02RT4 D 2PAK 800 / Tape & Reel NTB65N02RT4G D 2PAK (Pb−Free) 800 / Tape & Reel NTP65N02R TO−220AB 50 Units / Rail NTP65N02RG TO−220AB (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

NTB65N02R, NTP65N02R http://onsemi.com PACKAGE DIMENSIONS TO−220AB CASE 221A−09 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN

NTB65N02R, NTP65N02R http://onsemi.com PACKAGE DIMENSIONS D 2PAK CASE 418AA−01 ISSUE O STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SEATING PLANE S G D −T− M0.13 (0.005) T 231 3 PL K J V E C A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.036 0.51 0.92 E 0.045 0.055 1.14 1.40 G 0.100 BSC 2.54 BSC J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79 S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40 −B− MB W W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. M F M F M F VARIABLE CONFIGURATION ZONE U VIEW W−W VIEW W−W VIEW W−W 12 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 8.38 0.33 1.016 0.04 17.02 0.67 10.66 0.42 3.05 0.12 5.08 0.20 mm inchesSCALE 3:1

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