658 CTS | Alldatasheet

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Technical content

Document No. 008-0316-0 Page 1 - 5 Rev. A ٠ ٠ ٠CTS Electronic Components, Inc. ٠171 Covington Drive ٠Bloomingdale, IL 60108 ٠ ٠ ٠ ٠ ٠ ٠www.ctscorp.com ٠ ٠ ٠ Model 658 CLOCK, HIGH FREQUENCY MULTIPLIER

FEATURES

  • Standard 7x5mm Surface Mount Footprint
  • LVCMOS, Differential LVPECL or LVDS Outputs
  • Frequency Range 38 – 750 MHz
  • Frequency Stability, ±50 ppm Standard (± 25 ppm and ± 100 ppm available)
  • +2.5Vdc or +3.3Vdc Operation
  • Operating Temperature to –40°C to +85°C
  • Output Enable Standard
  • Low Phase Jitter, PLL Multiplier
  • Tape & Reel Packaging
  • RoHS/Green Compliant

ORDERING INFORMATION

C = CMOS, Pin 1 Enable Pin 2 N.C. (standard) L = LVDS, Pin 1 Enable Pin 2 N.C. (standard) P = PECL, Pin 1 Enable Pin 2 N.C. (standard) M = CMOS, Pin1 N.C. Pin 2 Enable V = LVDS, Pin1 N.C. Pin 2 Enable E = PECL, Pin1 N.C. Pin 2 Enable 658 SUPPLY VOLTAGE 2 = 2.5 Vdc (LVDS and PECL only) 3 = 3.3 Vdc OUTPUT TYPE FREQUENCY IN MHz M - indicates MHz and decimal point. Frequency is recorded with minimum 4 significant digits to the right of the "M". M OPERATING TEMPERATURE RANGE C = 0°C to +70°C (standard) I = -40°C to +85°C FREQUENCY STABILITY 5 = ± 25 ppm 3 = ± 50 ppm (standard) 2 = ± 100 ppm Example Part Number: 658P3C3155M5200

DESCRIPTION

The Model 658 is a ceramic packaged Clock oscillator offering reduced size and enhanced stability. The small size means it is perfect for any application. The enhanced stability means it is the perfect choice for today’s communications applications that require tight frequency control.

Document No. 008-0316-0 Page 2 - 5 Rev. A ٠ ٠ ٠CTS Electronic Components, Inc. ٠171 Covington Drive ٠Bloomingdale, IL 60108 ٠ ٠ ٠ Model 658 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Maximum Supply Voltage V CC - -0.5 - 7.0 V Storage Temperature T STG - -55 - 125 °C Frequency Range LVCMOS 50 - 250 LVPECL and LVDS fO - 38 - 750 MHz Frequency Stability (See Note 1 and Ordering Information) ∆f/fO - - - 25, 50 or 100 ± ppm Operating Temperature Commercial 0 70 Absolute Maximums Industrial TA - -40 Supply Voltage (See Ordering Information) VCC ± 5 % 2.38 3.14 2.5 3.3 2.63 3.47 V Supply Current Maximum Load LVCMOS < 160 MHz ≥ 160 MHz LVPECL < 160 MHz ≥ 160 MHz 100 LVDS ICC < 160 MHz ≥ 160 MHz mA Start Up Time T S Application of V CC - - 10 ms Phase Jitter tjms Bandwidth 12 kHz - 20 MHz - 3.5 5 ps RMS Enable Function Enable Input Voltage VIH Pin 1 or Pin 2 Logic '1', Output Enabled 0.7*V CC - - V Disable Input Voltage V IL Pin 1 or Pin 2 Logic '0', Output Disabled - - 0.3*V CC Disable Current I IL Pin 1 or Pin 2 Logic '1' , Output Disabled - - 20 uA Enable Time T PLZ Pin 1 or Pin 2 Logic '1' - 5 10 ms LVCMOS WAVEFORM Output Load CL - - 15 pF Output Duty Cycle SYM @ 50% Level 45 - 55 % Output Voltage Levels Logic '1' Level VOH CMOS Load 90%V CC - - Logic '0' Level V OL CMOS Load - - 10%V CC V Rise and Fall Time T R, TF @ 20% - 80% Levels - 2 5.0 ns LVPECL WAVEFORM Output Load RL - - 50 - Ohms Output Duty Cycle SYM @ V CC - 1.3V 45 - 55 % Output Voltage Levels Logic '1' Level VOH PECL Load V CC - 1.025V - - Logic '0' Level V OL PECL Load - - V CC - 1.62V V Rise and Fall Time T R, TF @ 20% - 80% Levels 0.4 1.0 ns LVDS WAVEFORM Output Load RL - - 100 - Ohms Output Duty Cycle SYM @ 1.25V 45 - 55 % Differential Voltage V OD RL = 100 Ohms 250 350 450 mV Output Voltage Levels Logic '1' Level VOH LVDS Load - - 1.6 Logic '0' Level V OL LVDS Load 0.9 - - V Electrical and Waveform Parameters Rise and Fall Time T R, TF @ 20% - 80% Levels - 0.4 1.0 ns Notes: 1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging at an average operating temperature of +40 °C.

Document No. 008-0316-0 Page 3 - 5 Rev. A ٠ ٠ ٠CTS Electronic Components, Inc. ٠171 Covington Drive ٠Bloomingdale, IL 60108 ٠ ٠ ٠ Model 658 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock CMOS/TTL OUTPUT WAVEFORM TEST CIRCUIT, CMOS LOAD PECL/LVDS OUTPUT WAVEFORM TEST CIRCUIT, PECL LOAD TEST CIRCUIT, LVDS LOAD ENABLE TRUTH TABLE PIN 1 or 2 PIN 4 / PIN 5 Logic ‘1’ Output Open Output Logic ‘0’ High Imp. D.U.T. PIN ASSIGNMENTS PIN SYMBOL DESCRIPTION

1 EOH / NC Enable or No Connect

2 NC / EOH No Connect or Enable

3 GND Circuit & Package Ground

4 Output RF Output

5 Output / NC Complimentary RF Output

(PECL and LVDS Only)

6 V CC Supply Voltage

UPTIME (t) PERIOD (T) 90%, 80%, 2.4V 50%, 1.5V 10%, 20%, 0.5V DUTY CYCLE = t/T x 100 (%) V V OH OL POWER SUPPLY VM mA 0.01uF D.U.T. N.C. or Enable Input N.C. Including probe capacitance. C L Enable Input or N.C. Tr Tf UPTIME (t) PERIOD (T) 80% 50% 20% DUTY CYCLE = t/T x 100 (%) OUT OUT OHV OLV VOS POWER SUPPLY VM mA 0.01uF D.U.T. N.C. or Enable Input CH1 CH2 R L R L Vcc - 2.0V Vcc - 2.0V Enable Input or N.C. POWER SUPPLY VM mA 0.01uF D.U.T. N.C. or Enable Input CH1 CH2 100 R L Enable Input or N.C.

Document No. 008-0316-0 Page 4 - 5 Rev. A ٠ ٠ ٠CTS Electronic Components, Inc. ٠171 Covington Drive ٠Bloomingdale, IL 60108 ٠ ٠ ٠ Model 658 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock MECHANICAL SPECIFICATIONS PACKAGE DRAWING MARKING INFORMATION (1.27) 0.050 PIN 1 IDENTIFIER Inch (mm)Key: (3.73) 0.147 (1.4) 0.197 ±0.008 (5.0 ±0.2) 0.079 0.276 ±0.008 0.055 0.200 (5.08) (7.0 ±0.2) MAX (2.0) (2.54) 0.100 SUGGESTED SOLDER PAD GEOMETRY SUGGESTED REFLOW PROFILE .165 [4.20] .071 [1.80] Key: [mm] Inch C BYPASS .200 [5.08] .100 [2.54] .079 [2.00] CBYPASS should be ≥ 0.01 uF. 1. - Manufacturing Site Code. 2. YYWW – Date code, YY – year, WW – week. 3. Truncated CTS part number. 4. XXXMXXXX - Frequency marked with 4 significant digits after the ‘M’. NOTES 1. Termination pads (e4), barrier-plating is nickel (Ni) with gold (Au) flash plate. 2. Reflow conditions per JEDEC J-STD-020. 100 200 300 0 30 60 90 120 150 180 210 240 270 300 Time (Seconds) Temp. (°C) Maximum 260°C, 10 seconds Typical 245°C 130°C CTS YYWW 658P3C3

  • XXXMXXXX

Document No. 008-0316-0 Page 5 - 5 Rev. A ٠ ٠ ٠CTS Electronic Components, Inc. ٠171 Covington Drive ٠Bloomingdale, IL 60108 ٠ ٠ ٠ Model 658 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock QUALITY AND RELIABILITY Quality systems meet or exceed the requirements of ISO 9000:2000 standards. TAPE AND REEL INFORMATION DIMENSIONS IN MILLIMETERS DIRECTION OF FEED 5.40 7.90 8.40 5.70 16.0 8.04.0 Ø1.50 1.75 2.10 2.40 Ø23 Ø180Ø60 Ø13 120° 17.5 2.0 Device quantity is 1,000 pieces per 180mm reel. ENVIRONMENTAL SPECIFICATIONS Temperature Cycle: 400 cycles from –55°C to + 125°C, 10 minute dwell at each temperature, 1 minute transfer time between temperatures. Mechanical Shock: 1,500g’s, 0.5mS duration, ½ sinewave, 3 shocks each direction along 3 mutually perpendicular planes (18 total shocks). Sinusoidal Vibration: 0.06 inches double amplitud e, 10 to 55 Hz and 20g’s, 55 to 2,000 Hz, 3 cycles each in 3 mutually perpendicular planes (9 times total). Gross Leak: No leak shall appear while imme rsed in an FC40 or equivalent liquid at +125°C for 20 seconds. Fine Leak: Mass spectrometer leak rates less than 2x10 -8 ATM cc/sec air equivalent. Resistance to Solder Heat: Pr oduct must survive 3 reflows of +260°C peak, 10 seconds maximum. High Temperature Operating Bias: 2,000 hours at +125° C, maximum bias, disregarding frequency shift. Frequency Aging: 1,000 hours at +85°C, full bias, less than ±5 ppm shift. Moisture Sensitivity Level: Level 1 per JEDEC J-STD-020.