6549CBZ

ISL6549 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• Single 12V bias supply (no 5V supply is required)
• Provides two regulated voltages - One synchronous rectified buck PWM controller - One linear controller
• Both controllers drive low cost N-Channel MOSFETs
• Small converter size - Adjustable frequency 150kHz to 1MHz - Small external component count
• Excellent output voltage regulation - Both outputs: ±1% over temperature
• 12V down conversion
• PWM and linear output voltage range: down to 0.8V
• Simple single-loop voltage-mode PWM control design
• Fast PWM converter transient response - High-bandwidth error amplifier
• Undervoltage fault monitoring on both outputs
• Pb-free plus anneal available (RoHS compliant)

Applications

• Processor and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6549CB ISL6549CB 0 to 70 14 Ld SOIC M14.15 ISL6549CBZ (Note) 6549CBZ 0 to 70 14 Ld SOIC (Pb-free) M14.15 ISL6549CR ISL6549CR 0 to 70 16 Ld 4x4 QFN L16.4x4 ISL6549CRZ (Note) 6549CRZ 0 to 70 16 Ld 4x4 QFN (Pb-free) L16.4x4 ISL6549CA ISL6549CA 0 to 70 16 Ld QSOP M16.15A ISL6549CAZ (Note) 6549CAZ 0 to 70 16 Ld QSOP (Pb-free) M16.15A ISL6549CAZA (Note) 6549CAZ 0 to 70 16 Ld QSOP (Pb-free) M16.15A ISL6549IBZ (Note) 6549IBZ -40 to 85 14 Ld SOIC (Pb-free) M14.15 ISL6549IRZ (Note) 6549IRZ -40 to 85 16 Ld 4x4 QFN (Pb-free) L16.4x4 ISL6549IAZ (Note) 6549IAZ -40 to 85 16 Ld QSOP (Pb-free) M16.15A ISL6549LOW-EVAL1 Evaluation Board 1-5A ISL6549HI-EVAL1 Evaluation Board up to 20A Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet September 22, 2006 FN9168.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN9168.2 September 22, 2006 Block Diagram Pinouts ISL6549 (SOIC) TOP VIEW ISL6549 (QFN) TOP VIEW ISL6549 (QSOP) TOP VIEW FB COMP LDO_DR LDO_FB UGATE VCC5 PVCC5 FS_DIS GND BOOT VCC12 LGATE PGND PHASE COMP FB LDO_DR LDO_FB FS_DIS BOOT UGATE PHASE PGND LGATE PVCC5 VCC5 AGND VCC12 DGND VCC12 1516 14 13 657 8 METAL GND PAD (BOTTOM) 11 FB COMP LDO_DR LDO_FB UGATE VCC5 PVCC5 FS_DIS AGND BOOT VCC12 LGATE PGND PHASE 8DGND 9 VCC12 PHASE SOFT-START COMP EA1 VCC5 PWM UGATELDO_DR LDO_FB POWER-ON RESET (POR) OSCILLATOR FB COMP EA2 UV2 VOLTAGE REFERENCE RESTART UV1 INHIBIT SOFT-START 0.80V 0.60V LGATE BOOT GATE LOGIC PGND VCC12 FS_DIS GND PVCC5 DIS DIS REGULATOR ISL6549

3 FN9168.2 September 22, 2006 Simplified Power System Diagram Typical Application Schematic PWM VOUT1 VOUT2 LINEAR ISL6549 CONTROLLER CONTROLLER +12V +VIN2 +VIN1 GND +VIN1 VOUT1 UGATE Q1 FB COMP LDO_DRQ3 LDO_FB COUT2 COUT1 LOUT ISL6549 VOUT2 + CBP5 Q2LGATE +12V CBP12 PGND PHASE FS_DIS BOOT PVCC5 VCC5 CBP CVIN1 +VIN2 VCC12 CVIN2 CBOOT ISL6549

4 FN9168.2 September 22, 2006 ISL6549 Absolute Maximum Ratings Thermal Information BOOT - 7V to VBOOT + 0.3V ESD Classification Thermal Resistance θ JA (°C/W) θJC (°C/W) (SOIC - Lead Tips Only) Recommended Operating Conditions CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply Current VCC12 (disabled) I CC12 dis UGATE, LGATE and LDO_DR open; FS_DIS = GND 23 m A Nominal Supply Current VCC5 (disabled) I CC5 dis UGATE, LGATE and LDO_DR open; FS_DIS = GND (Note 4) 57 . 5 m A Nominal Supply Current VCC12 (includes PVCC5 current) ICC12 UGATE, LGATE and LDO_DR open; FOSC = 620kHz 12 18 mA Nominal Supply Current VCC5 I CC5 UGATE, LGATE and LDO_DR open; FOSC = 620kHz 46 m A Maximum PVCC5 Current Available (Note 5) I PVCC5 100 mA VCC12 to PVCC5 Current Limit (Note 5) I PVCC5CL 150 mA PVCC5 Voltage V PVCC5 ISL6549C; No external load 4.95 5.25 5.8 V ISL6549I; No external load 4.85 5.25 5.8 POWER-ON RESET Rising VCC5 Threshold VCC12 = 12V 3.7 4.2 4.5 V Falling VCC5 Threshold VCC12 = 12V 3.3 3.8 4.1 V Rising VCC12 Threshold VCC5 = 5V 8.8 9.5 10.0 V Falling VCC12 Threshold VCC5 = 5V 7.0 7.5 8.0 V OSCILLATOR AND SOFT-START Switching Frequency F OSC ISL6549C; RFS_DIS = 45.3kΩ 540 620 700 kHz ISL6549I; RFS_DIS = 45.3kΩ 525 620 700 kHz

5 FN9168.2 September 22, 2006 ISL6549 Sawtooth Amplitude (Note 6) DV OSC 1.5 V Soft-Start Interval T SS FOSC = 620kHz 6.8 ms REFERENCE VOLTAGE Reference Voltage V REF ISL6549C; For Error Amp 1 and 2 0.792 0.8 0.808 V ISL6549I; For Error Amp 1 and 2 0.788 0.8 0.812 V PWM CONTROLLER ERROR AMPLIFIER DC Gain (Note 6) R L = 10K, CL = 10pF 96 dB Gain-Bandwidth Product (Note 6) GBWP R L = 10K, CL = 10pF 20 MHz Slew Rate (Note 6) SR R L = 10K, CL = 10pF 8 V/µs FB Input Current ⎜II ⎜ VFB = 0.8V 0.1 1.0 µA COMP High Output Voltage V OUT High 4.8 V COMP Low Output Voltage V OUT Low 0.6 V COMP High Output, Source Current I OUT High -2.8 mA Undervoltage Level (VFB/VREF)V UV 70 75 80 % PWM CONTROLLER GATE DRIVERS UGATE Maximum Voltage V HUGATE VCC12 = 12V; PHASE = 12V 17 17.5 18 LGATE Maximum Voltage V HLGATE VCC12 = 12V; based on PVCC5 voltage 5.25 6 V UGATE and LGATE Minimum Voltage VLGATE VCC12 = 12V; PHASE = 0V 0 0.5 V UGATE Source Output Impedance R DS(ON) VCC12 = 12V; IGATE = 100mA 0.8 Ω UGATE Sink Output Impedance R DS(ON) VCC12 = 12V; IGATE = 100mA 0.7 Ω LGATE Source Output Impedance R DS(ON) VCC12 = 12V; IGATE = 100mA 0.8 Ω LGATE Sink Output Impedance R DS(ON) VCC12 = 12V; IGATE = 100mA 0.4 Ω LINEAR REGULATOR (LDO_DR) DC Gain (Note 6) Gain R L = 10K, CL = 10pF 100 dB Gain-Bandwidth Product (Note 6) GBWP R L = 10K, CL = 10pF 2 MHz Slew Rate (Note 6) SR R L = 10K, CL = 10pF 6 V /µs LDO_FB Input Current ⎜II ⎜ VLDO_FB = 0.8V 0.1 1.0 µA LDO_DR High Output Voltage V OUT High VCC12 = 12V 11.0 11.5 V LDO_DR Low Output Voltage V OUT Low 0.0 0.5 V LDO_DR High Output Source Current I OUT High V OUT = 2.0V 2.0 mA LDO_DR Low Output Sink Current I OUT Low 0.5 mA Undervoltage Level (VLDO_FB/VREF)V UV Percent of Nominal 70 75 80 % NOTES: 4. Current in VCC5 is actually higher disabled, due to extra current required to pull down against the FS_DIS pin. VCC12 current is lower disabled. 5. Guaranteed by design, not production tested . Exceeding the maximum current from PVCC5 may result in degraded performance and unsafe operation. 6. Guaranteed by design, not production tested. Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

6 FN9168.2 September 22, 2006 Functional Pin Description VCC12 This is the power supply pin for the IC; it sources the internal 5V regulator used for the gate drivers. Provide a local decoupling capacitor to GND. The voltage at this pin is monitored for Power-On Reset (POR) purposes. The

16 Ld QFN and 16 Ld QSOP have two VCC12 pins; tie them

together on the board. VCC5 This pin supplies the internal 5V bias for analog and logic functions. Provide a local decoupling capacitor to GND, and a resistor to PVCC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. See “Internal PVCC5 Regulator” on page 7 for more details. GND, AGND, DGND These pins are the signal ground for the IC. All voltage levels are measured with respect to these pins. Connect all to the ground plane via the shortest available path. PVCC5 This pin is the internal 5V linear regulator for the BOOT supply (for the UGATE driver), and the source for the LGATE. Provide a local decoupling capacitor to PGND. Do not use this pin as a voltage source for other circuits. See “Internal PVCC5 Regulator” on page 7 for more details. PGND This pin is the power ground return for the lower gate driver. (LGATE). Connect to the ground plane on the board via the shortest available path. UGATE This output pin drives the upper MOSFET gate from the internal 5V regulator. Connect it to the gate of the upper MOSFET via a short, low inductance trace. BOOT The BOOT pin, along with the external capacitor (from PHASE to BOOT), an internal diode, and the internal 5.5V regulator, creates the bootstrap voltage for the upper gate driver (UGATE). The maximum voltage is around 5.5V (above PHASE). PHASE This pin represents the return path for the upper gate drive. Connect it to the source of the upper MOSFET via a short, low inductance trace. LGATE This output pin drives the lower MOSFET gate from the internal 5V regulator. Connect it to the gate of the lower MOSFET via a short, low inductance trace. FB FB is the available external inverting input pin of the error amplifier. Connect the output of the switching regulator to this pin through a properly sized resistor divider, to set the output voltage. The voltage at this pin is regulated to the internal reference voltage. This pin is also monitored for undervoltage detection. COMP COMP is the available external output pin of the error amplifier. This pin is used to compensate the voltage-mode control feedback loop of the standard synchronous rectified buck converter. Connect an appropriate compensation network between this and the FB pin. See “PWM Controller Feedback Compensation” on page 10 for more information. FS_DIS This input pin has two functions. A resistor to GND sets the internal oscillator frequency for the switching regulator. In addition, if the pin is pulled down towards GND with a low impedance (<1kΩ, such as an external FET), it will disable both regulator outputs until released (at which time a new soft- start cycle will begin). LDO_DR This output pin provides the gate voltage for the linear regulator pass transistor. Connect this pin to the gate terminal of an external N-channel MOSFET transistor. This pin (along with the LDO_FB pin) also provides a means of compensating the error amplifier, should the application require it. LDO_FB This input pin is the FB inverting input on the linear regulator error amplifier. Connect the output of the linear regulator to this pin through a properly sized resistor divider, to set the output voltage. The voltage at this pin is regulated to the internal reference voltage. This pin is also monitored for undervoltage detection. Bottom Pad (QFN Package Only) The QFN package’s metal bottom pad is resistively tied to the internal IC GND. For best thermal and electrical performance, connect this pad to the GND pins, and to the ground plane of the PCB through 4 vias equidistantly situated inside the solder landing pad. ISL6549

-20dB/decade slope and a phase margin greater than 45°. compensation (as shown in Figure 8). approximated by Equation 10. given inductor also reduces the ripple current and voltage. current level must be supplied by the output capacitor. and slow the current load rate seen by the bulk capacitors. requirements rather than actual capacitance requirements. many ceramic capacitors in parallel; others may need only one. switching-regulator applications for the bulk capacitors. FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

13 FN9168.2 September 22, 2006 transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not always a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of sm all case size perform better than a single large case capacitor. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper FET Q1 and the source of lower FET Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately half the DC load current. Several electrolytic capacitors may be needed. Bootstrap Capacitor Selection The boot diode is internal to the ISL6549, and uses PVCC5 to charge the external boot capacitor. The size of the bootstrap capacitor can be chosen by using the equations in Equation 12. The last equation plugs in some typical values: N = 1; Q G is 33nC, VIN is 12V, VGS is 11V, ∆Vmax = 1V. In this example, CBOOT ≥ 0.113µF. This value is often rounded to 0.1µF or 0.22µF as a starting value. The bootstrap capacitors for the ISL6549 can usually be rated for 6.3V. Switcher FET Considerations The IC was designed for nominal 12V supply for VIN1 (drain of upper FET Q1). However, it will work with most any voltage (from other supplies or other regulator outputs) down to around 1V, as long as the input is above the output by a sufficient margin (based on practical duty cycle limitations and upper FET R DS(ON) constraints). For example, although the IC can function at near 100% duty cycle, the voltage drop due to the R DS(ON) of the upper FET at full load current will limit the practical duty cycle to something less than 100%. So the V IN1 range is roughly 1.0V up to 12V, with the VOUT1 range slightly below it. Therefore, the FETs need to be rated for drain-source breakdown above the V IN1 voltage; 20V and 30V ratings are common. The ISL6549 gate drivers (UGATE and LGATE) were designed to drive up to 2 upper and 2 lower 8 Ld SOIC FETs; when the FETs are properly sized, the output currents can range from under 1A to over 20A. Driving more or bigger FETs is not recommended; even if there is enough current (from the internal PVCC5 regulator), the gate driver waveforms may be degraded. DPAK FET packages can be used, but D 2PAK FETs are not recommended, due to the higher inductance of the package leads. For example, the inductance in the source of the lower FET can create large negative spikes on the PHASE node when the UGATE turns off. Both the UGATE and LGATE voltages are derived from the internal PVCC5 internal regulator, typically 5.25V. UGATE is only about 5.0V above PHASE, due to the drop in the internal BOOT diode charging the BOOT capacitor; LGATE sees the full 5.25V. So both are considered “5V” drivers; this affects the FET selection in two ways. First, the FET gate-source voltage rating can be as low as 12V (this rating is usually consistent with the 20V or 30V breakdown chosen above). Second, the FETs must have a low threshold voltage (around 1V), in order to have its R DS(ON) rating at VGS = 4.5V in the 10mΩ-20mΩ range. While some FETs are also rated with gate voltages as low as 2.7V, with typical thresholds under 1V, these can cause application problems. As LGATE shuts off the lower FET, it does not take much ringing in the LGATE signal to turn the lower FET back on, while the Upper FET is also turning on, causing some shoot-through current. So avoid FETs with thresholds below 1V. Another set of important parameters are the turn-on and turn-off times (internal propagation delays, how long before the output starts to switch) and the rise and fall times (external delay to complete the switching). The UGATE and LGATE drivers use an adaptive technique to determine the dead time (when both gate drivers signals are low). Comparators sense when each driver is getting close to GND (such that its FET is close to being off), before turning on the other. This technique minimizes the dead time to the 10ns-20ns range. So if either CBOOT QGATE NQ G VIN•• VGS CBOOT QGATE NQ G VIN•• where N is the number of upper FETs Q G is the total gate charge per upper FET VIN is the input voltage VGS is the gate-source voltage (~5V for ISL6549) ∆V is the change in boot voltage before and immediately after the transfer of charge; typically 0.7V to 1.0V and (EQ. 12) ISL6549

maximum power dissipation expected. magnitude of voltage spikes. supply critical bypass current and signal coupling. easily handle the several Amps of drive current. GND returns (from lower FET source to VIN cap GND) short. the upper MOSFET and lower MOSFET and the load. FIGURE 13. PRINTED CIRCUIT BOARD POWER PLANES

16 FN9168.2 September 22, 2006 ISL6549 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) SYMBOL MILLIMETERS NOTESMIN NOMINAL MAX A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 9 b 0.23 0.28 0.35 5, 8 D 4.00 BSC - D1 3.75 BSC 9 D2 1.95 2.10 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 2.10 2.25 7, 8 e 0.65 BSC - k0 . 2 5 - - - L 0.50 0.60 0.75 8 L1 - - 0.15 10 N1 6 2 Nd 4 3 Ne 4 3 P- -0 . 6 0 9 θ -- 1 2 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.

17 FN9168.2 September 22, 2006 ISL6549 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9168.2 September 22, 2006 ISL6549 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimen- sions are not necessarily exact. α INDEX AREA E D N 123 -B- 0.17(0.007) C AM B S e -A- B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE M16.15A

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY) SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.061 0.068 1.55 1.73 - A1 0.004 0.0098 0.102 0.249 - A2 0.055 0.061 1.40 1.55 - B 0.008 0.012 0.20 0.31 9 C 0.0075 0.0098 0.191 0.249 - D 0.189 0.196 4.80 4.98 3 E 0.150 0.157 3.81 3.99 4 e 0.025 BSC 0.635 BSC - H 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 L 0.016 0.035 0.41 0.89 6 N1 6 1 6 7 α 0° 8° 0° 8° - Rev. 2 6/04