650R-27ILFT | DigiCamel IC Datasheet

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ICS650-27 IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 7

Technical content

Features

Packaged in 20-pin (150 mil) SSOP (QSOP)
Pb (lead) free package, RoHS compliant
12.5 MHz or 25 MHz fundamental crystal or clock input
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive capability at TTL levels
Advanced, low-power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature only Block Diagram Clock Buffer/ Crystal Oscillator Clock Synthesis and Control Circuitry 25 or 12.5 MHz cyrstal or clock ACS1:0 CLKA1 CCS GND BCS1:0 X1/ICLK CLKA2 CLKB1 CLKB2 CLKC1 CLKC2 REFOUT VDD OE (all outputs)

NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ NETWORKING CLOCK SOURCE 2 ICS650-27 REV F 051310 Pin Assignment Pin Descriptions ASC1 VDD CLKC2 CLKA2 CCS CLKB2 DC CLKB1 3X1/ICLK VDD CLKA1

18 REFOUT

20 BCS1

20-pin (150 mil) SSOP Pin Number Pin Name Pin Type Pin Description 1 ACS0 Input A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. 2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. 3 X1/ICLK Input Crystal connection. Connect to a fundamental crystal or clock input. 4 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 16. 5 ACS1 Input A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull-up. 6 GND Power Connect to ground. 7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3. 8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. 9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. 10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. 11 CCS Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. 12 DC - Don’t connect. Do not connect anything to this pin. 13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. 14 GND Power Connect to ground. 15 OE Input Output enable. Tri-states all outputs when low. Internal pull-up. 16 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 4. 17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. 18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input. 19 BCS0 Input B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. 20 BCS1 Input B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull-up.

NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ NETWORKING CLOCK SOURCE 3 ICS650-27 REV F 051310 For a 25 MHz fundamental crystal or clock input, the following four tables apply: A Clocks Select Table (outputs in MHz) C Clocks Select Table (outputs in MHz) B Clocks Select Table (outputs in MHz) Reference Output Clock Frequency (in MHz) For a 12.5 MHz fundamental crystal or clock input, the following four tables apply: A Clocks Select Table (outputs in MHz) C Clocks Select Table (outputs in MHz) B Clocks Select Table (outputs in MHz) Reference Output Clock Frequency (in MHz) 0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD ASC1 ASC0 CLKA1 CLKA2 00 1 0 0 o f f ( l o w )

0 M Test Test

01 7 5 o f f ( l o w ) 1 0 33.3333 16.6667

1 M Test Test

1 1 66.6667 33.3333 CCS CLKC1 CLKC2 0 125 125 M Test Test 17 5 7 5 BSC1 BSC0 CLKB1 CLKB2 0 0 Test Test 0 M 66.6667 33.3333 01 1 0 0 5 0 1 0 83.3333 41.6667 1 1 133.3333 66.6667 REFOUT ASC1 ASC0 CLKA1 CLKA2 00 5 0 o f f ( l o w ) 0 1 37.5 off (low) 1 0 16.6667 8.3333 1 1 33.3333 16.6667 CCS CLKC1 CLKC2 0 62.5 62.5 M Test Test 1 37.5 37.5 BSC1 BSC0 CLKB1 CLKB2 0 0 Test Test 0 M 33.3333 16.6667 0 1 50 25 1 0 41.6667 20.8333 1 1 66.6667 33.3333 REFOUT 12.5

NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ NETWORKING CLOCK SOURCE 4 ICS650-27 REV F 051310 External Components The ICS650-27 requires a minimum number of external components for proper operation. Decoupling Capacitor Decoupling capacitors of 0.01µF must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (C L - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-27. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 175 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.0 +3.3 +3.6 V

NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ NETWORKING CLOCK SOURCE 5 ICS650-27 REV F 051310 Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C Unless stated otherwise, VDD = 3.3 V±10%, Ambient Temperature -40 to +85° C Note 1: Measured with 15 pF load Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 3.3 3.6 V Input High Voltage V IH X1 pin only, CLK input VDD/2+1 VDD/2 V Input Low Voltage V IL X1 pin only, CLK input VDD/2 VDD/2-1 V Input High Voltage V IH all tri-level type inputs VDD-0.5 V Input Low Voltage V IL all tri-level type inputs 0.5 V Input High Voltage V IH all other inputs 2 V Input Low Voltage V IL all other inputs 0.8 V Output High Voltage V OH IOH = -25 mA 2.4 V Output Low Voltage V OL IOL = 25mA 0.8 V Output High Voltage, CMOS level V OH IOH = -8 mA VDD-0.4 V Operating Supply Current I DD No Load 50 mA Short Circuit Current I OS Each output ±50 mA Internal pull-up resistor R PU BCS1, OE pins 510 k Ω ACSI pin 120 k Ω Nominal output impedance Z OUT 20 Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 10 12.5 or

27 MHz

Output Rise Time t OR 0.8 to 2.0 V, Note 1 1.5 ns Output Fall Time t OF 2.0 to 0.8 V, Note 1 1.5 ns Output Clock Duty Cycle At VDD/2, Note 1 40 50 60 % Frequency Error All clocks 0 ppm Absolute Jitter, short term Variation from mean, Note 1 ±150 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 135 ° C/W θJA 1 m/s air flow 93 ° C/W θJA 3 m/s air flow 78 ° C/W Thermal Resistance Junction to Case θJC 60 ° C/W

NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ NETWORKING CLOCK SOURCE 6 ICS650-27 REV F 051310 Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 650R-27ILF 650R-27ILF Tubes 20-pin SSOP -40 to +85 ° C 650R-27ILFT 650R-27ILF Tape and Reel 20-pin SSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b .10 (.004) C c L Millimeters Inches Symbol Min Max Min Max A 1 . 3 51 . 7 5. 0 5 3. 0 6 9 A1 0.10 0.25 .0040 .010 A2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 C 0 . 1 80 . 2 5. 0 0 7. 0 1 0 D 8 . 5 58 . 7 5. 3 3 7. 3 4 4 E 5 . 8 06 . 2 0. 2 2 8. 2 4 4 E1 3.80 4.00 .150 .157 e 0.635 Basic 0.025 Basic L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS650-27 NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER

Product Information

650R-27ILFT specifications and overview.

Summary

NETWORKING CLOCK SOURCE

Description

The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error.

Source title 650R-27ILFT Datasheet(PDF) - Integrated Device Technology

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