6164

UM6164_V01 UMC | Alldatasheet

Document overview

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• PDF pages: 7

Technical content

Features

• High-speed - 45/55/70ns (Max.)
• Low p'ower dissipation 300mW (Typ.) Operating 100J.l.W (Typ.) standby
• Single 5V power supply General Description The UM6164 is a 65,536-bit static random access memory organized as 8192 words by 8 bits' and operates from a single 5 volt supply. It is built with UMC's high perform­ ance twin tub CMOS process. I nputs and three-state
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three state outputs
• Data retention supply voltage: 2.0-5,5V outputs are TTL compatible and allow for direct interfacing with common system bus structures. The UM6164 is moulded in a standard 28-pin, 600 mil-DIP. Pin Configuration . Block Diagram AU CS2 CSt OE WE 2-43 ROW DECODE INPUT DATA CIRCUIT 256 x 256 MEMORY ARRAY COLUMN I/O .COLUMN DECODER --<> Vcc ~GND

*Comments Absolute Maximum Ratings* Terminal Voltage with Respect to Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Pin Names Operating Range Ao-A12 Address WE Write Enable 1/01-I/Os Data Input/Output OE Output Enable Range Ambient Vee Temperature CS 1 Chip Select One CS 2 Chip Select Two Commercial 0° C to +70°C 5V ± 10% Vee Power GND Ground D.C. Electrical Characteristics (Vee = 5V ± 10%, GND = OV, T A = 0 to 70°C) Symbol Parameter Test Conditions Min. Typ.1 Max. Units III Input leakage current VIN =GNDtoVee - - 5 p.A ILO Output Leakage Current CSl =V IH orCS2 =V IL orOE=V IH, - - 5 p.A VI/O = GND to Vee lee Operating Power Supply CS 1 = V IL, CS 2 = V IH , 11/0 =OmA Current - 50 100 mA lec1 Average Operating Current Min, Duty Cycle = 100%, CS 1 = VI L' - 60 120 mA CS 2 = V IH ISB CS 1 = V I H or CS 2 = V I L' 11/0 = 0 mA - 5 10 mA ISB12 Standby Power Supply CS 1 ~ V ee-0.2V, V IN ~ Vee-O.2V Current or VIN ~ O.2V - .02 2 mA ISB22 CS 2 ~ 0.,2V, V IN ~ V ee -O.2V or - .02 2 mA VIN ~ O.2V VOL I OL =2.1 mA - - 0.4 V Output Voltage V OH 10H = -1.0mA 2.4 - - V 1. Typical I imits are at Vee = 5.0V, T A = 25° C and specified loading. 2. VIL min = -0.3V 2-44

Recommended D.C. Operating Conditions (T A = 0 to +70°C) Symbol Parameter VCC Supply Voltage GNO Supply Voltage VIH Input High Voltage VIL Input Low Voltage Capacitance (1) (T A = 25°C, f = 1.0MHz) Symbol Parameter- Conditions Max. CIN Input Capacitance VIN =OV 6 Clio Input/Output Vila =OV 8 Capacitance Unit pF pF Note: This parameter is sampled and not 100% tested. A.C. Electrical Characteristic (over the operating range) Symbol Parameter READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS1 Chip Select Access Time tACS2 tOE Output Enable to Output Valid tCLZ1 Chip Selection to Output in Low Z tCLz2 tOLZ Output Enable to Output in Low Z l CSl I CS 2 I CSl I CS 2 tCHZ1 Chip Deselection to Output in High Z ~ CSl tCHz2 CS 2 tOHZ Output Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE twc Write Cycle Time tcw Chip Selection to End of Write tAS Address Setup Time tAW Address Valid to End of Write twp Write Pulse Width Min. 4.5 2.2 -0.5 tWR1 Write Recovery Time I CSl,WE tWR2 I CS 2 tWHZ Write to <?utput in High Z tow Data to Write Time Overlap tOH Data Hold from Write Time tOHZ OE to Output in High Z tow Output Active from End of Write Note: UM6164 Typ. Max. Unit 5.0 5.5 V 0 0 V 3.5 6.0 V 0 0.8 V A.C. Test Conditions Parameter Conditions Input Pulse Levels OV to 3.0V Input Rise and Fall Times 5 ns Input and Output 1.5V Timing Reference Level Output Load 1 TTL Gate and C L = 30pF (including scope and jig) UM6164-2 UM6164·1 UM6164 Unit 45 - 55 - 70 - - 45 - 55 - 70 ns - 45 - 55 - 70 ns - 45 - 55 - 70 ns - 30 - 35 - 50 ns 5 - 5 - 5 - ns 5 - 5 - 5 - ns 5 - 5 - 5 - ns 0 25 0 30 0 35 ns 0 25 0 30 0 35 ns 0 25 0 30 0 35 ns 5 - 5 - 5 - ns 45 - 55 - 70 - ns 35 - 40 - 45 - ns 5 - 5 - 5 - ns 40 - 50 - 65 - ns 35 - 40 - 45 - ns 5 - 5 - 5 - ns 5 - 10 - 10 - ns 0 20 0 25 0 30 ns 20 - 25 - 30 - ns 5 - 5 - 5 - ns 0 25 0 25 0 25 ns 5 - 5 - 5 - ns tCHZ I tOHZ and tWHZ are defined as the timeatwhich the outputs achieve the open circuit condition and are not referred to output voltage levels. 2-45

(l)UMC UM6164 Truth Table Mode WE CS 1 CS 2 OE I/O Operation Vee Current Notes Not Selected X H X X High Z IS8,IS81 (Poyver Down) X X L X High Z IS8' IS82 Output Disabled H L H H High Z IcC,lcC1 Read H L H L DOUT Icc,lcC1 Write L L H H DIN Icc,lcC1 Write Cycle 1 L L H L DIN Icc,lcC1 Write Cycle 2 Timing Waveforms READ CYCLE(1,2,4) tRC r tAA g ~tOHt tOH I: DOUT READ CYCLE 2(1,3,4,6) ~CHZi- READ CYCLE 3(1,4,7) C~ ~F'= tACS, gJ tCLZ S - I 2-46

READ CYCLE 4(1) ADDRESS OE 14-----tACS2 Notes: 1. WE is high for READ cycle. 2. Device is continuously selected CSl = VI Land CS 2 = VIH. 3. Address valid prior to or coincident with CSl transition low. 4. OE = VIL. UM6164 5. Transition is measured ± 500mV from steady state. This parameter is sampled and not 100% tested. 6. CS 2 is high. 7. CSl is low. WRITE CYCLE 1(1) twc ADDRESS OE WE 2-47

UM6:1.64 WRITE CYCLE 2(1,6) twc ADDRESS ~---- tCW 2 Notes: 1. WE must be high during address transitions. 2. A write occurs during the overlap (twp) of a low CSl a high CS 2 and a low WE. 3. tWR is measured from the earlier of CS, or WE. going high or CS 2 going low to the end of write cycle. 4. During this period, I/O pins are in the output state SO that the input signals of opposite phase to the outputs must not be applied. 5. If the CSl low transition or the CS 2 high transition occurs simultaneously with the WE low transitions or after the WE transition. Outputs remain in a high impedance state. 6. OE is continuously low (OE = V IL ). 7. D OUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. . 9. If CS 1 is low and CS 2 is high during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 590mV from steady state. This parameter is sampled and not 100% tested. 11. tcw is measured from the later of CS 1 going low or CS 2 going high to the end of write. 2-48

Data Retention Characteristics (T A = 0 to +70°C) Symbol Parameter Test Conditions VORl '. CSl ~ Vee -O.2V, V IN ~ V ee-0.2V or V IN ~ 0.2V Vee for Data Retention VDR2 CS 2 ~ O.2V, VIN ~ V ee-0.2V or V IN ~ O.2V leeDRl CSl ~ Vee -O.2V, Data Retention Current V IN ~ Vee-O.2V or V IN ~ O.2V leeDR2 CS2 ~ O.2V, V IN ~ Vee -D.2V or V IN ~ 0.2V teDR Ch ip Deselect to Data Retention Time See Retention Waveform tR Operation Recovery Time 1. Vee =2V, TA =+25°C 2. t Re = Read Cycle Time Low Vee Data Retention Waveform CS I CONTROLLED DATA RETENTION MODE 4.5V VOR ~2V eSI ~vee - O.2V CS 2 CONTROLLED ~--_ DATA RETENTION MODc--_-----'~ 4.5V VOR ~ 2V

Ordering Information

Part Number Access Time (Max.) Package UM6164 70 Plastic DIP UM6164-1 45 Plastic DIP UM6164-2 55 Plastic DIP 2-49 UM6J.64 Min. TypJ1) Max. Units 2.0 - - V 2.0 - - V - 2 50 JJ.A - 2 50 JJ.A 0 - - ns tRe(2) - - ns