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  • 2 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.42 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746

ORDERING INFORMATION

Package Tape & Reel Qty Part Number M 750 IR3895MTR1PBF M 4000 IR3895MTRPBF PIN DIAGRAM 5m x 6mm POWER QFN (TOP VIEW) Rt/Sync PGood S_Ctrl Fb Vref Comp Gnd PBF – Lead Free TR/TR1 – Tape and Reel M – Package Type 30 / JA JP C B CW CW  

  • 3 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.43 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 BLOCK DIAGRAM Figure 3: IR3895 Simplified Block Diagram
  • 4 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.44 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier.

2 Vref

Internal reference voltage, it can be used for margining operation also. In normal and sequencing mode operation, a 100pF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. 3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation. 4 Gnd Signal ground for internal reference and control circuitry.

5 Rt/Sync

Multi‐function pin to set switching frequency. Use an external resistor from this pin to Gnd to set the free‐running switching frequency. An external clock signal can be connected to this pin through a diode so that the device’s switching frequency is synchronized with the external clock.

6 S_Ctrl

Soft start/stop control. A high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. Pull this pin to Vcc if this function is not used. 7 PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to the voltage lower than or equal to the Vcc. 8 Vsns Sense pin for over‐voltage protection and PGood. It is optional to tie this pin to FB pin directly instead of using a resistor divider from Vout.

9 Vin

Input voltage for Internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. 10 Vcc/LDO_Out Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum 2.2µF cap from this pin to PGnd. 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. This pin is connected to the output inductor. 13 PVin Input voltage for power stage.

14 Boot Supply voltage for high side driver, a 100nF capacitor should be connected

between this pin and SW pin.

15 Enable Enable pin to turn on and off the device, if this pin is connected to PVin pin

through a resistor divider, input voltage UVLO can be implemented. 16 Vp Input to error amplifier for tracking purposes. In the normal operation, it is left floating and no external capacitor is required. In the sequencing or the tracking mode operation, an external signal can be applied as the reference. 17 Gnd Signal ground for internal reference and control circuitry.

  • 5 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.45 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin ‐0.3V to 25V Vcc/LDO_Out ‐ 0.3V to 8V (Note 2) Boot ‐0.3V to 33V SW ‐ 0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) Boot to SW ‐0.3V to VCC + 0.3V (Note 1) S_Ctrl, PGood ‐ 0.3V to VCC + 0.3V (Note 1) Other Input/Output Pins ‐0.3V to +3.9V PGnd to Gnd ‐ 0.3V to +0.3V Storage Temperature Range ‐55°C to 150°C Junction Temperature Range ‐ 40°C to 150°C (Note 2) ESD Classification (HBM JESD22‐A114) 2kV Moisture Sensitivity Level JEDEC Level 2@260°C Note 1: Must not exceed 8V Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C
  • 6 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.46 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN SYMBOL MIN MAX UNITS Input Voltage Range* PVin 1.0 21 V Input Voltage Range Vin 5 21 Supply Voltage Range* VCC 4.5 7.5 Supply Voltage Range Boot to SW 4.5 7.5 Output Voltage Range VO 0.5 0.86xVin Output Current Range IO 0 ±16 A Switching Frequency FS 300 1500 kHz Operating Junction Temperature TJ ‐ 40 125 °C *Maximum SW node voltage should not exceed 25V. For internally biased single rail operation. When Vin drops below 6.8V, the internal LDO enters dropout. Please refer to Smart LDO section and Over Current Protection for detailed application information. * Vcc/LDO_out can be connected to an external regulated supply. If so, the Vin input should be connected to Vcc/LDO_out pin.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < TJ < 125°C. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power Stage Power Losses PLOSS Vin = 12V, VO = 1.2V, IO = 16A, Fs = 600kHz, L = 0.4uH, Vcc = 6.4V (internal LDO), Note 4 3.4 W Top Switch Rds(on)_Top VBoot ‐ Vsw= 6.4V, IO = 16A, Tj =25°C 9.6 13.5 mΩ Bottom Switch Rds(on)_Bot Vcc = 6.4V, IO = 16A, Tj =25°C 4.2 6.1 Bootstrap Diode Forward Voltage I(Boot) = 15mA 200 300 500 mV SW Leakage Current ISW SW = 0V, Enable = 0V 1 µA SW = 0V, Enable = high, Vp = 0V Dead Band Time Tdb Note 4 20 ns Supply Current Vin Supply Current (standby) Iin(Standby) EN = Low, No Switching 100 µA Vin Supply Current (dynamic) Iin(Dyn) EN = High, Fs = 600kHz, Vin = PVin = 21V 20 23 mA VCC LDO Output Output Voltage Vcc Vin(min) = 6.8V, Icc = 0‐50mA, Cload = 2.2uF, DCM = 0 6.0 6.4 6.7 V Vin(min) = 6.8V, Icc = 0‐50mA, Cload = 2.2uF, DCM = 1 4.0 4.4 4.85 VCC Dropout Vcc_drop Icc=50mA,Cload=2.2uF 0.8 V Short Circuit Current Ishort 70 mA

  • 7 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.47 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Zero‐crossing Comparator Delay Tdly_zc Note 4 256/Fs s Zero‐crossing Comparator Offset Vos_zc Note 4 ‐ 4 0 4 mV Oscillator Rt Voltage Vrt 1.0 V Frequency Range Fs Rt = 80.6K 270 300 330 kHz Rt = 39.2K 540 600 660 Rt = 15.0K 1350 1500 1650 Ramp Amplitude Vramp Vin = 6.8V, Vin slew rate max = 1V/µs, Note 4 1.02 Vp‐p Vin = 12V, Vin slew rate max = 1V/µs, Note 4 1.80 Vin = 21V, Vin slew rate max = 1V/µs, Note 4 3.15 Vcc=Vin=5V,For external Vcc operation, Note 4 0.75 Ramp Offset Ramp(os) Note 4 0.16 V Min Pulse Width Tmin(ctrl) Note 4 60 ns Max Duty Cycle Dmax Fs = 300kHz, PVin = Vin = 12V 86 % Fixed Off Time Toff Note 4 200 250 ns Sync Frequency Range Fsync 270 1650 kHz Sync Pulse Duration Tsync 100 200 ns Sync Level Threshold High 3 V Low 0.6 Error Amplifier Input Offset Voltage Vos_Vref VFb – Vref, Vref = 0.5V ‐ 1.5 +1.5 Vos_Vp VFb – Vp, Vp = 0.5V,Vref=0 ‐ 1.5 +1.5 Input Bias Current IFb(E/A) ‐ 1 +1 µA Input Bias Current IVp(E/A) 0 +4 Sink Current Isink(E/A) 0.4 0.85 1.2 mA Source Current Isource(E/A) 4 7.5 11 mA Slew Rate SR Note 4 7 12 20 V/µs Gain‐Bandwidth Product GBWP Note 4 20 30 40 MHz DC Gain Gain Note 4 100 110 120 dB Maximum output Voltage Vmax(E/A) 1.7 2.0 2.3 V Minimum output Voltage Vmin(E/A) 100 mV Common Mode input Voltage 0 1.2 V Reference Voltage Feedback Voltage Vfb Vref and Vp pin floating 0.5 V
  • 8 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.48 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Accuracy 0°C < Tj < 70°C ‐ 0.5 +0.5 Vref Margining Voltage Vref_marg 0.4 1.2 V Sink Current Isink_Vref Vref = 0.6V 12.7 16.0 19.3 µA Source Current Isrc_Vref Vref = 0.4V 12.7 16.0 19.3 Vref Comparator Threshold Vref_disable Vref pin connected externally 0.15 V Vref_enable 0.4 Soft Start/Stop Soft Start Ramp Rate Ramp (SS_start) 0.16 0.2 0.24 mV/µs Soft Start Ramp Rate Ramp (SS_stop) S_Ctrl Threshold High 2.4 V Low 0.6 Power Good PGood Turn on Threshold VPG(on) Vsns Rising, 0.4V < Vref < 1.2V 85 90 95 % Vref Vsns Rising, Vref < 0.1V 85 90 95 % Vp PGood Lower Turn off Threshold VPG(lower) Vsns Falling, 0.4V < Vref < 1.2V 80 85 90 % Vref Vsns Falling, Vref < 0.1V 80 85 90 % Vp PGood Turn on Delay VPG(on)_Dly Vsns Rising, see VPG(on) 1.28 ms PGood Upper Turn off Threshold VPG(upper) Vsns Rising, 0.4V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp PGood Comparator Delay VPG(comp)_ Dly Vsns < VPG(lower) or Vsns > VPG(upper) 1 2 3.5 µs PGood Voltage Low PG(voltage) IPgood = ‐5mA 0.5 V Tracker Comparator Upper Threshold VPG(tracker _upper) Vp Rising, Vref < 0.1V 0.4 V Tracker Comparator Lower Threshold VPG(tracker _lower) Vp Falling, Vref < 0.1V 0.3 Tracker Comparator Delay Tdelay(track er) Vp Rising, Vref < 0.1V,see VPG(tracker_upper) 1.28 ms Under‐Voltage Lockout Vcc‐Start Threshold VCC_UVLO_ Start Vcc Rising Trip Level 4.0 4.2 4.4 V Vcc‐Stop Threshold VCC_UVLO_ Stop Vcc Falling Trip Level 3.7 3.9 4.1 Enable‐Start‐Threshold Enable_UVL O_Start Supply ramping up 1.14 1.2 1.26 V
  • 9 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.49 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Enable‐Stop‐Threshold Enable_UVL O_Stop Supply ramping down 0.95 1 1.05 Enable Leakage Current Ien Enable = 3.3V 1 µA Over‐Voltage Protection OVP Trip Threshold OVP_Vth Vsns Rising, 0.45V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp OVP Comparator Delay OVP_Tdly 1 2 3.5 µs Over‐Current Protection Current Limit ILIMIT Tj = 25°C, Vcc = 6.4V 18.0 20.5 24.4 A Hiccup Blanking Time Tblk_Hiccup 20.48 ms Over‐Temperature Protection Thermal Shutdown Threshold Ttsd Note 4 145 Hysteresis Ttsd_hys Note 4 20 Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note 4: Guaranteed by design but not tested in production.
  • 10 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.410 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.4 59PR9875N (Vitec) 0.29 1.2 0.4 59PR9875N (Vitec) 0.29 1.8 0.47 7443330047(Wurth Elektronik) 0.8 3.3 0.88 MPC1040LR88C(NEC/Tokin) 2.3 5 1.0 7443330100(Wurth Elektronik) 1.35
  • 11 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.411 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = External 5V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.4 59PR9875N (Vitec) 0.29 1.2 0.4 59PR9875N (Vitec) 0.29 1.8 0.47 7443330047(Wurth Elektronik) 0.8 3.3 0.88 MPC1040LR88C(NEC/Tokin) 2.3 5 1.0 7443330100(Wurth Elektronik) 1.35
  • 12 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.412 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 5.0V, Vcc = 5.0V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.3 59PR9874N (Vitec) 0.29 1.2 0.3 59PR9874N (Vitec) 0.29 1.8 0.4 59PR9875N (Vitec) 0.29
  • 13 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.413 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 THERMAL DERATING CURVES Measurement done on Evaluation board of IRDC3895.PCB is 4 layer board with 2 oz Copper, FR4 material, size 2.23"x2" PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600kHz PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600kHz
  • 14 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.414 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 RDSON OF MOSFETS OVER TEMPERATURE AT VCC=6.4V RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=5.0V
  • 15 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.415 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C)
  • 16 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.416 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) Internal LDO in regulation Internal LDO in dropout mode With an External 5V Vcc Voltage
  • 17 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.417 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C)
  • 18 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.418 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 THEORY OF OPERATION

DESCRIPTION

The IR3895 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300 kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3895 provides precisely regulated output voltage programmed via two external resistors from 0.5V to 0.86*Vin. The IR3895 operates with an internal bias supply (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The bias voltage is variable according to load condition. If the output load current is less than half of the peak‐to‐peak inductor current, a lower bias voltage, 4.4V, is used as the internal gate drive voltage; otherwise, a higher voltage, 6.4V, is used. This feature helps the converter to reduce power losses. For internal biased single‐rail operation, if the input voltage drops below 6.8V, the internal LDO starts to enter dropout mode. The IC can also be operated with an external supply from 4.5 to 7.5V, allowing an extended operating input voltage (PVin) range from 1.0V to 21V. For using the internal LDO supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_Out pin and the Vin pin should be shorted to Vcc/LDO_Out pin. The device utilizes the on‐resistance of the low side MOSFET (sync FET) for over current protection. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3895 includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. UNDER‐VOLTAGE LOCKOUT AND POR The under‐voltage lockout circuit monitors the voltage of Vcc/LDO_Out pin and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc/LDO_Out and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). ENABLE The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under‐Voltage Lockout (UVLO) circuit. Therefore, the IR3895 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3895 does not turn on until the bus voltage reaches the desired level (Fig. 4). Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold, IR3895 will be enabled. Therefore, in addition to being a logic input pin to enable the IR3895, the Enable feature, with its precise threshold, also allows the user to implement an Under‐Voltage Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want the IR3895 to be disabled at least until PVIN exceeds the desired output voltage level. Pvin (12V) Vcc Enable Intl_SS 10. 2 V Enable Threshold = 1.2V Figure 4: Normal Start up, device turns on when the bus voltage reaches 10.2V A resistor divider is used at EN pin from PVin to turn on the device at 10.2V.

  • 19 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.419 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 Pvin(12V) Vcc Intl_SS Enable >1.2V Vp>1V Figure 5a: Recommended startup for Normal operation Pvin (12V) Vcc Enable > 1. 2 V Intl_SS Vp Figure 5b: Recommended startup for sequencing operation (ratiometric or simultaneous) Pvin=Vin=12V Vp=VDDQ/2 Vcc Vref=0 Enable > 1.2V VTT VDDQ VTT Tracking Figure 5c: Recommended startup for memory tracking operation (VTT‐DDR4) Figure 5a shows the recommended start‐up sequence for the normal (non‐tracking, non‐sequencing) operation of IR3895, when Enable is used as a logic input. Figure 5b shows the recommended startup sequence for sequenced operation of IR3895 with Enable used as logic input. Figure 5c shows the recommended startup sequence for tracking operation of IR3895 with Enable used as logic input. In normal and sequencing mode operation, Vref is left floating. A 100pF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. It is recommended to apply the Enable signal after the VCC voltage has been established. If the Enable signal is present before VCC, a 50kΩ resistor can be used in series with the Enable pin to limit the current flowing into the Enable pin. PRE‐BIAS STARTUP IR3895 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 6a shows a typical Pre‐Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 6b shows the series of 16x8 startup pulses. Vo[V] [Time] Pre-Bias Voltage Figure 6a: Pre‐Bias startup

16 End of

12.5% 25% 87.5% 16 ... ... ... ... Figure 6b: Pre‐Bias startup pulses

  • 20 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.420 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 SOFT‐START IR3895 has an internal digital soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft‐start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7 shows the waveforms during soft start (also refer to Fig. 20). The normal Vout start up time is fixed, and is equal to: During the soft start the over‐current protection (OCP) and over‐voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. POR Intl_SS Vout 0.15V 0.65V t1 t2 t3 1.5V 3.0V Figure 7: Theoretical operation waveforms during soft‐start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between 300 kHz – 1500 kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. SHUTDOWN IR3895 can be shutdown by pulling the Enable pin below its 1.0V threshold. This will tri‐state both the high side and the low side driver. T ABLE 1: SWITCHING FREQUENCY (FS) VS. EXTERNAL RESISTOR (RT) Rt (KΩ) Freq (kHz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 OVER CURRENT PROTECTION The over current (OC) protection is performed by sensing current through the RDS(on) of the Synchronous Mosfet. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The current limit is pre‐set internally and is compensated according to the IC temperature. So at different ambient temperature, the over‐current trip threshold remains almost constant. Note that the over current limit is a function of the Vcc voltage. Refer to the typical performance curves of the OCP current limit with the internal LDO and the external Vcc voltage. Detailed operation of OCP is explained as follows. Over Current Protection circuit senses the inductor current flowing through the Synchronous Mosfet closer to the valley point. OCP circuit samples this current for 40nsec typically after the rising edge of the PWM set pulse which has a width of 12.5% of the switching period.The PWM pulse starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. PGood will go low and the internal soft start signal will be pulled low. The converter goes into hiccup mode with a 20.48ms (typ.) delay as shown in Figure 8. The convertor stays in this mode until the over load or short circuit is removed. The actual DC output current limit point will be greater than the valley point by an amount equal to approximately
  • 27 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.427 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 MAXIMUM DUTY RATIO A certain off‐time is specified for IR3895. This provides an upper limit on the operating duty ratio at any given switching frequency. The off‐time remains at a relatively fixed ratio to switching period in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which IR3895 can operate. Figure 21 shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feed forward. Figure 21: Maximum duty cycle vs. switching frequency.
  • 29 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.429 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: Figure 24: Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: (14) o in Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=16A and D = 0.1, the IRMS = 4.8A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 5x10uF, 25V ceramic capacitors, C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEV‐FK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: (15) in o s o in o in s iVVL t D tF VLVV Vi F Where: Vin = Maximum input voltage V0 = Output Voltage Δi = Inductor Peak‐to‐Peak Ripple Current Fs = Switching Frequency Δt = On time for Control FET D = Duty Cycle If Δi ≈ 30%*Io, then the output inductor is calculated to be 0.38μH. Select L=0.4μH, 59PR9875N, from VITEC which provides a compact, low profile inductor suitable for this application.
  • 31 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.431 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 The ESR zero of the output capacitor is expressed as follows: 1 (18) 2 ESR o VOUT VREF C POLE C3R3 Ve FZ FPOLE E/A Z f Frequency Gain(dB) H(s) dB Fb Comp Z IN Figure 26: Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vout) is given by: 1() ( 1 9 ) fe out IN ZVs R CHsVZ s R C The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by:  3 (20) 1 (21) 2* * z RHs R F RC First select the desired zero‐crossover frequency (Fo): Use the following equation to calculate R3: 3 2 ** * (23) * osc o ESR in LC Where: Vin = Maximum Input Voltage Vosc = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: 75 % * 10.75* (24) zL C z oo FF F LC Use equation 21 to calculate C3. One more capacitor is sometimes added in parallel with C3 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: 1 (25)*2* * P POLE POLE F CCR CC The pole sets to one half of the switching frequency which results in the capacitor CPOLE: 11 (26) 1POLE s s C *R *F*R *F C For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, a type III compensation network can be used, as shown in Fig. 27.
  • 32 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.432 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 VOUT VREF R5R4 C3R3 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain (dB) |H(s)| dB Fb Comp Figure 27: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: IN f out e Z ZsHV V  )( By replacing Zin and Zf, according to Fig. 27, the transfer function can be expressed as:  33 4 4 5 52 3 3 4 4 (1 ) 1 *() () 1 ( 1 ) (27) sR C sC R R CCHs sRC C s R s R C CC The compensation network has three poles and two zeros and they are expressed as follows: 3223 0 (28) 1 (29) 2* * 11 (30)2* **2* P P P F F RC F RCCCR CC 44 5 4 5 1 (31)2* * Z Z F RC F CR R C R Cross over frequency is expressed as: in o osc o o VFR C VL C  Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. TABLE 3: DIFFERENT TYPES OF COMPENSATORS Compensator Type FESR vs FO Typical Output Capacitor Type II FLC < FESR < FO < FS/2 Electrolytic Type III FLC < FO < FESR SP Cap, Ceramic The higher the crossover frequency is, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency (Fo) is selected such that: The DC gain should be large enough to provide high DC‐regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=1.2V Vosc=1.8V (This is a function of Vin, pls. see feed forward section) Vref=0.5V Lo=0.4uH Co=6x47uF, ESR≈3mΩ each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 47uf capacitor used in this design is 29uf at 1.2V dc bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation.
  • 33 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.433 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (17) to compute the small signal Co. These result in: FLC=19.1 kHz FESR=1.8 MHz Fs/2=300 kHz Select crossover frequency F0=80 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. Detailed calculation of compensation Type III: Desired Phase Boost Θ = 70° 1s i n 14.1 kHz1s i n 1s i n 454.0 kHz1s i n Select: 12 0.5* 7.1 kHz andZZFF    3 0.5* 300 kHzPsFF  Select C4 = 3.3nF. Calculate R3, C3 and C2: oo oo s c in FLCVRR CV  Select R3 = 1.78 kΩ: 33 3 1 3 1 ; 12.7 nF, Select: 10 nF2* * Z CC C FR  22 2 1 ; 298 pF, Select: 220 pF2* * P CC C FR  Calculate R4, R5 and R6: 44 4 1 ; 106 Ω, Select: 100 Ω2* * P RR R CF 54 5 RR R CF Select R5 = 4.02 kΩ: 65 6 6 * ; 2.87 k Ω Select: 2.87 k Ω- ref or e f VRR R RVV  Setting the Power Good Threshold In this design IR3895 is used in normal (non‐tracking, non‐sequencing) mode, therefore the PGood thresholds are internally set at 90% and 120% of Vref. At startup as soon as Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), and after 1.28ms delay, PGood signal is asserted. As long as the Vsns voltage is between the threshold range, Enable is high, and no fault happens, the PGood remains high. The following formula can be used to set the PGood threshold. Vout (PGood_TH) can be taken as 90% of Vout. Choose R8=2.87KΩ. (_ ) 7 ( 1)* 8 (34)0.9* 74 . 0 2 out PGood THVRR Vref R K   The PGood is an open drain output. Hence, it is necessary to use a pull up resistor, RPG, from PGood pin to Vcc. The value of the pull‐up resistor must be chosen such as to limit the current flowing into the PGood pin to be less than 5mA when the output voltage is not in regulation. A typical value used is 49.9kΩ. OVP comparator also uses Vsns signal for over Voltage dectection.With above values for R7 and R8, OVP trip point (Vout_OVP) is _ *1.2*( 7 8 )/ 8 1.44 (35 )OVPVout Vref R R R V  Vref Bypass Capacitor A minimum value of 100pF bypass capacitor is recommended to be placed between Vref and Gnd pins. This capacitor should be placed as close as possible to Vref pin
  • 34 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.434 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 APPLICATION DIAGRAM Figure 28: Application Circuit for a 12V to 1.2V, 16A Point of Load Converter Suggested bill of materials for the application circuit Part Reference Qty Value Description Manufacturer Part Number Cin 1 330uF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 5 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M C1 C5 C6 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B Cref 1 100pF 0603,50V,NP0, 5% Murata GRM1885C1H101JA01D C4 1 3300pF 0603,50V,X7R Murata GRM188R71H332KA01B C2 1 220pF 0603, 50V, NP0, 5% Murata GRM1885C1H221JA01D Co 6 47uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M CVcc 1 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 10nF 0603, 25V, X7R, 10% Murata GRM188R71E103KA01J Cvin 1 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D R3 1 1.78K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1781V R5 R7 2 4.02K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4021V R6 R8 2 2.87K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2871V R4 1 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V Rt 1 39.2K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V R1 Rpg 2 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V R2 1 7.5K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7551V U1 1 IR3895 PQFN 5x6mm IR IR3895MPBF
  • 35 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.435 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 Boot Vcc/LDO_out Fb Comp Gnd PGnd SW S_Ctrl Vo=1V PGood Enable Rt/Sync Vin= 5V Vin Vp 3.32k 3.32k Co=6X47uF Lo 0.3 uH 2.2nF 100 2.49k 15nF 180pF 0. 1 uF Cin = 6 X 10uF Rt 39.2.K RPG 49.9K IR3895 2.2uF CVcc PVin Vref 100pF Cref Vsns 3.32k 3.32k 0.1uF 0.1uF PGood Enable FIGURE 29: APPLICATION CIRCUIT FOR A 5V TO 1V, 16A POINT OF LOAD CONVERTER Suggested bill of materials for the application circuit: 5V to 1V Part Reference Qty Value Description Manufacturer Part Number Cin 1 330uF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 6 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M C1 C5 C6 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B Cref 1 100pF 0603,50V,NP0, 5% Murata GRM1885C1H101JA01D C4 1 2200pF 0603,50V,X7R, 10% Murata GRM188R71H222KA01B C2 1 180pF 0603, 50V, NP0, 5% TDK C1608C0G1H181J Co 6 47uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M CVcc 1 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 15nF 0603,50V,X7R, 10% TDK C1608X7R1H153K Cvin 1 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D R3 1 2.49k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2491V R5 R6 R7 R8 4 3.32k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V R4 1 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V Rt 1 39.2K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V Rpg 2 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V U1 1 IR3895 PQFN 5x6mm IR IR3895MPBF
  • 40 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.440 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3899 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3899. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vin, Vcc and Vref should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4‐layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figures 46a‐d illustrates the implementation of the layout guidelines outlined above, on the IRDC3899 4‐layer demo board. Figure 47a: IRDC3895 Demo board Layout Considerations – Top layer Compensation parts should be placed as close as possible to the Comp pin Resistor Rt and Vref decoupling cap should be placed as close as possible to their pins Enough copper & minimum ground length path between Input and Output All bypass caps should be placed as close as possible to their connecting pins Switch Node
  • 42 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.442 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following Figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self‐centering behavior is highly dependent on solders and processes and experiments should be run to confirm the limits of self‐centering on specific processes. For further information, please refer to “SupIRBuck™ Multi‐Chip Module (MCM) Power Quad Flat No‐Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 48: PCB Metal Pad Sizing and Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format
  • 43 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.443 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 SOLDER RESIST  IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability.  When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.)  However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined.  When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment.  Ensure that the solder resist in‐between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 49: Solder resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format
  • 44 -P JANUARY 18, 2013 | DATA SHEET| Rev 3.444 IR3895 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97746 STENCIL DESIGN  Stencils for PQFN can be used with thicknesses than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm‐0.200mm (0.005‐0.008"), with suitable reductions, give the best results.  Evaluations have shown that the best overall performance is achieved using the stencil design shown in following Figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 50: Stencil Pad Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format