5962-04204

HCPL-5120 BOARDCOM | Alldatasheet

Document overview

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Technical content

Features

 Performance guaranteed over full military temperature range: –55°C to +125°C  Manufactured and tested on a MIL-PRF-38534 certified line  Hermetically sealed packages  Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD)  HCPL-3120 function compatibility  QML-38534, Class H  2.0A minimum peak output current  0.5V maximum low level output voltage (VOL): eliminates need for negative gate drive  10 kV/μs minimum common-mode rejection (CMR) at V CM =1 0 0 0 V  ICC = 5 mA maximum supply current  Undervoltage lock-out protection (UVLO) with hysteresis  Wide operating VCC Range: 15V to 30V  500 ns maximum propagation delay  ±0.35μs maximum delay between devices

Applications

 Industrial and military environments  High reliability systems  Harsh industrial environments  Transportation, medical, and life critical systems  Uninterruptible power supplies (UPS)  Isolated IGBT/MOSFET gate drive  AC and brushless DC motor drives  Industrial inverters  Switch mode power supplies (SMPS) HCPL-5120, HCPL-5121, and 5962-04204 1

2.0 Amp Output Current IGBT Gate Drive Hermetically

• 2 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Schematic Diagram Schematic Diagram Truth Table NOTE A 0.1 μF bypass capacitor must be connected between pins 5 and 8. SHIELD N/C CATHODE ANODE N/C VCC VO VO VEE LED VCC – VEE VCC – VEE VOPositive Going (i.e., Turn-On) Negative Going (i.e., Turn-Off) OFF 0V to 30V 0V to 30V LOW ON 0V to 11V 0V to 9.5V LOW ON 11V to 13.5V 9.5V to 12V TRANSITION ON 13.5V to 30V 12V to 30V HIGH Selection Guide– Lead Configuration Options Device Marking Part Number and Options Commercial HCPL-5120 MIL-PRF-38534, Class H HCPL-5121 Standard Lead Finisha a. Gold plate lead finish: Maximum gold thickness of leads is <100 micro-inches. Typical is 60 to 90 micro-inches. Gold Plate Solder Dippedb b. Solder lead finish: Sn63/Pb37. Option - 200 Butt Cut/Gold Platea Option - 100 Gull Wing/Solderedb Option - 300 SMD Part Number Prescript for all below 5962- Gold Platea 0420401HPC Solder Dippedb 0420401HPA Butt Cut/Gold Platea 0420401HYC Butt Cut/Solderedb 0420401HYA Gull Wing/Solderedb 0420401HXA COMPLIANCE INDICATOR,[1] DATE CODE, SUFFIX (IF NEEDED) A HCPL-512x 5962-04204 01Hxx 50434 COUNTRY OF MFR. AVAGO CAGE CODE[1] AVAGO DESIGNATOR DLA SMD[1] PIN ONE/ ESD IDENT AVAGO P/N DLA SMD[1] [1] QML PARTS ONLY XXX QYYWWZ

• 3 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Outline Drawing Outline Drawing 8-Pin DIP Through Hole, 1 Channel Hermetic Optocoupler Options Option Description 100 Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial and Class H product. 200 Lead finish is solder-dipped rather than gold plated. This option is available on Commercial and Class H product. DLA Drawing (SMD) part numbers contain provisions for lead finish. 300 Surface-mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercia l and Class H product. This option has solder-dipped leads. 3.81 (0.150) MIN. 4.32 (0.170) MAX. 10.03 (0.395) 10.29 (0.405) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MIN. 1.02 (0.040) 1.52 (0.060) 8.13 (0.320) MAX. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) MAX. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MIN. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.51 (0.020) MIN. 4.57 (0.180) MAX. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5° MAX. 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013)NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 1.07 (0.042) 1.32 (0.052)

• 4 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings ESD Classification Recommended Operating Conditions Parameter Symbol Min Max Unit Notes Storage Temperature T S –65 +150 °C Operating Temperature T A –55 +125 °C Case Temperature T C — +145 °C Junction Temperature T J — +150 °C Lead Solder Temperature — 260 for 10s °C Average Input Current I F AVG —2 5 m A a a. No derating required for typical case-to-ambient thermal resistance (ΘCA = 140°C/W). See Figure 35. Peak Transient Input Current (<1-μs pulse width, 300 pps) IF PK —1 . 0 A Reverse Input Voltage V R —5 V High Peak Output Current I OH (PEAK) —2 . 5 A b b. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This va lue is intended to allow for component tolerances for designs with IO peak minimum = 2.0A. See the Application Information section for additional details on limiting IOH peak. Low Peak Output Current I OL (PEAK) —2 . 5 A b Supply Voltage (V CC – VEE)0 3 5 V Output Voltage V O (PEAK) 0V CC V Emitter Power Dissipation P E —4 5 m W a Output Power Dissipation P O —2 5 0 m W c c. Derate linearly above 102°C free air temperature at a rate of 6 mW/°C for typical case-to-ambient thermal resistance (ΘCA = 140°C/W). See Figure 36. Total Power Dissipation P T —2 9 5 m W d d. Derate linearly above 102°C free air temperature at a rate of 6 mW/°C for typical case-to-ambient thermal resistance (ΘCA = 140°C/W). See Figure 35 and Figure 36. MIL-STD-883, Method 3015 , Class 1 Parameter Symbol Min Max Unit Power Supply Voltage (V CC – VEE)1 5 3 0 V Input Current (ON) I F (ON) 10 18 mA Input Voltage (OFF) V F (OFF) –3.0 0.8 V Operating Temperature T A –55 125 °C

• 5 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Electrical Specifications (DC) Electrical Specifications (DC) Over recommended operating conditions (TA = –55°C to +125°C, IF(ON) = 10 mA to 18 mA, VF(OFF) = –3.0V to 0.8V, VCC = 15V to 30V, VEE = Ground), unless otherwise specified. Parameter Symbol Test Conditions Group A Subgroupsa a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). Limits Unit Fig Notes Min Typb b. All typical values at T A = 25°C and VCC – VEE = 30V, unless otherwise noted. Max High Level Output Current I OH VO = (VCC – 4V) 1, 2, 3 0.5 1.5 — A 2, 3, 17 c c. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%. VO = (VCC – 15V) 2.0 — — A d d. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This va lue is intended to allow for component tolerances for designs with IO peak minimum = 2.0A. See the Application Information section for additional details on limiting IOH peak. Low Level Output Current I OL VO = (VEE + 2.5V) 1, 2, 3 0.5 2.0 — A 5, 6, 18 c VO = (VEE + 15V) 2.0 — — A d High Level Output Voltage V OH IO = –100 mA 1, 2, 3 (V CC – 4) (V CC – 3) — V 1, 3, 19 e, f e. In this test, V OH is measured with a dc load current. When driving capacitive loads, VOH approaches VCC as IOH approaches zero amps. f. Maximum pulse width = 1 ms, maximum duty cycle = 20%. Low Level Output Voltage V OL IO = 100 mA 1, 2, 3 — 0.1 0.5 V 4, 6, 20 High Level Supply Current I CCH Output Open, IF = 10 mA to 18 mA 1, 2, 3 — 2.5 5.0 mA 7, 8 Low Level Supply Current I CCL Output Open, VF = –3.0V to +0.8V 1, 2, 3 — 2.5 5.0 mA Threshold Input Current Low to High I FLH IO = 0 mA, VO > 5V 1, 2, 3 — 3.5 9.0 mA 9, 15, 21 Threshold Input Voltage High to Low V FHL 1, 2, 3 0.8 — — V Input Forward Voltage V F IF = 10 mA 1, 2, 3 1.2 1.5 1.8 V 16 Temperature Coefficient of Forward Voltage ΔVF/ΔTA IF = 10 mA — –1.6 — mV/°C Input Reverse Breakdown Voltage BV R IR = 10 μA 1, 2, 3 5 — — V Input Capacitance C IN f = 1 MHz, VF = 0V — 80 — pF UVLO Threshold V UVLO+ VO > 5V, IF = 10 mA 1, 2, 3 11.0 12.3 13.5 V 22, 37 VUVLO– 1, 2, 3 9.5 10.7 12.0 UVLO Hysteresis UVLO HYS —1 . 6 —

• 6 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Switching Specifications (AC) Switching Specifications (AC) Over recommended operating conditions (TA = –55°C to +125°C, IF(ON) = 10 mA to 18 mA, VF(OFF) = –3.0V to 0.8V, VCC = 15V to 30V, VEE = Ground), unless otherwise specified. Parameter Symbol Test Conditions Group A Subgroupsa a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). Limits Unit Fig Notes Min Typb b. All typical values at T A = 25°C and VCC – VEE = 30V, unless otherwise noted. Max Propagation Delay Time to High Output Level tPLH Rg = 10Ω, Cg = 10 nF, f = 10 kHz, Duty Cycle = 50% 9, 10, 11 0.10 0.30 0.50 μs 10, 11, 12, 13, 14, 23 c c. This load condition approximates the gate load of a 1200V/75A IGBT. Propagation Delay Time to Low Output Level tPHL 9, 10, 11 0.10 0.30 0.50 μs Pulse Width Distortion PWD 9, 10, 11 — — 0.3 μs d d. Pulse Width Distortion (PWD) is defined as |tPHL – tPLH| for any given device. Propagation Delay Difference Between Any Two Parts PDD (tPHL – tPLH) 9, 10, 11 –0.35 — 0.35 μs 33, 34 e e. The difference between t PHL and tPLH between any two HCPL-512x parts under the same test condition. Rise Time t r —0 . 1 —μ s 23 Fall Time t f —0 . 1 —μ s UVLO Turn On Delay t UVLO ON VO > 5V, IF = 10 mA — 0.8 — μs 22 UVLO Turn Off Delay t UVLO OFF VO < 5V, IF = 10 mA — 0.6 — Output High Level Common-Mode Transient Immunity |CMH|I F = 10 mA, VCM = 1000V, VCC = 30V, TA = 25°C 91 0 — — k V / μ s 24 f, g, h f. Pins 1 and 4 need to be connected to LED common. g. Common-mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common-mode pulse, VCM, to assure that the output remains in the high state (i.e., VO > 15.0V). h. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. Output Low Level Common-Mode Transient Immunity |CML|V CM = 1000V, VF = 0V, VCC = 30V, TA = 25°C 91 0 — — k V / μ s f, i, h i. Common-mode transient immunity in a low state is the maximum tolerable dV CM/dt of the common-mode pulse, VCM, to assure that the output remains in a low state (i.e., VO < 1.0V).

• 7 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Package Characteristics Package Characteristics Over recommended operating conditions (TA = –55°C to +125°C) unless otherwise specified. Parameter Symbol Test Conditions Group A Subgroupsa a. Commercial parts receive 100% testing at 25°C (Subgroups 1 an d 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). Limits Unit Fig Notes Min Typb b. Typicals at T A = 25°C. Max Input-Output Leakage Current I I-O VI-O = 1500 Vdc, RH ≤ 65%, t = 5 sec., TA = 25°C 1— — 1 . 0 μ A c, d c. This is a momentary withstand test, not an operating condition. d. Device considered a two-terminal device : pins on input side shorted together and pins on output side shorted together. Resistance (Input-Output) R I-O VI-O = 500 VDC — 1010 —Ω d Capacitance (Input-Output) C I-O f = 1 MHz — 2.5 — pF d

• 12 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet Package Characteristics Figure 23 tPLH, tPHL, and tf Test Circuit and Waveforms Figure 24 CMR Test Circuit and Waveforms 0.1 μF V CC = 15 to 30 V 10 : IF = 10 to 18 mA VO

10 KHz

50% DUTY CYCLE 500 : 10 nF IF V OUT tPHLtPLH tftr 10% 50% 90% Tr = Tf < 10 ns_ 0.1 μF V CC = 30 V IF V O A B V CM = 1000 V 5 V V CM 0 V V O SWITCH AT B: IF = 0 mA V O SWITCH AT A: IF = 10 mA V OL V OH V CMGV Gt

• 13 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet

Application Information

Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-512x has a very low maximum VOL specification of 0.5V. The HCPL-512x realizes this very low VOL by using a DMOS transistor with 1Ω (typical) on resistance in its pull-down circuit. When the HCPL-512x is in the low state, the IGBT gate is shorted to the emitter by Rg + 1Ω. Minimizing Rg and the lead inductance from the HCPL-512x to the IGBT gate and emitter (possibly by mounting the HCPL-512x on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-512x input as this can result in unwanted coupling of transient signals into the HCPL-512x and degrade performance. (If the IGBT drain must be routed near the HCPL-512x input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-512x.) Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses Step 1: Calculate Rg Minimum from the IOL Peak Specification The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-512x. The VOL value of 2V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-512x is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used, V EE in the previous equation is equal to zero volts. Step 2: Check the HCPL-512x Power Dissipation and Increase Rg if Necessary The HCPL-512x total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO): PT = PE + PO PE = IF × VF × Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC × (VCC – VEE) + ESW(Rg, Qg) × f For the circuit in Figure 26 with IF (worst case) = 18 mA, Rg = 8Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz, and TA max = 125°C: PE = 18 mA × 1.8V × 0.8 = 26 mW PO = 4.25 mA × 20V + 1.0 μJ × 20 kHz = 85 mW + 20 mW = 105 mW < 112 mW (P O(MAX) at 125°C = 250 mW – 23°C × 6 mW/°C) The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at –55°C) to ICC max at 125°C. Since PO for this case is less than PO(MAX), Rg of 8Ω is appropriate. Rg VCC VEE– VOL–() IOLPEAK VCC VEE– 2V–() IOLPEAK 15V 5V 2V–+() 7.2Ω= 8Ω≈

• 18 - HCPL-5120, HCPL-5121, and 5962-04204 Data Sheet

Undervoltage Lockout Feature The HCPL-512x contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-512x supply voltage (equivalent to the fully charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-512x output is in the high state and the supply voltage drops below the HCPL-512x V UVLO– threshold (9.5 < VUVLO– < 12.0), the optocoupler output goes into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 μs. When the HCPL-512x output is in the low state and the supply voltage rises above the HCPL-512x VUVLO+ threshold (11.0 < VUVLO+ < 13.5), the optocoupler output goes into the high state (assuming LED is ON) with a typical delay, UVLO Turn On Delay, of 0.8 μs. Figure 37 Undervoltage Lockout VO - OUTPUT VOLTAGE - V (VCC - VEE) - SUPPLY VOLTAGE - V 10 15 (12.3, 10.8) (10.7, 9.2)

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