SMJ320C6414 TI | Alldatasheet
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/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Highest-Performance Fixed-Point Digital Signal Processors (DSPs) − 2-, 1.67-, 1.39-ns Instruction Cycle Time − 600-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 4800 MIPS − Fully Software-Compatible With C62x − C6414/15/16 Devices Pin-Compatible /C0068VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional Units With VelociTI.2 Extensions: − Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional /C0068Instruction Set Features − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality /C0068Viterbi Decoder Coprocessor (VCP) [C6416] − Supports Over 500 7.95-Kbps AMR − Programmable Code Parameters /C0068Turbo Decoder Coprocessor (TCP) [C6416] − Supports up to Six 2-Mbps 3GPP (6 Iterations) − Programmable Turbo Code and Decoding Parameters /C0068L1/L2 Memory Architecture − 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) − 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) − 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation) /C0068Two External Memory Interfaces (EMIFs) − One 64-Bit (EMIFA), One 16-Bit (EMIFB) − Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable External Memory Space /C0068Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) /C0068Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16-Bit) /C006832-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ] − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O − Four-Wire Serial EEPROM Interface − PCI Interrupt Request Under DSP Program Control − DSP Interrupt Via PCI I/O Cycle /C0068Three Multichannel Buffered Serial Ports − Direct Interface to T1/E1, MVIP, SCSA Framers − Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible − Serial Peripheral Interface (SPI) Compatible (Motorola) /C0068Three 32-Bit General-Purpose Timers /C0068Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416] − UTOPIA Level 2 Slave ATM Controller − 8-Bit Transmit and Receive Operations up to 50 MHz per Direction − User-Defined Cell Format up to 64 Bytes /C0068Sixteen General-Purpose I/O (GPIO) Pins /C0068Flexible PLL Clock Generator /C0068IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible /C0068570-Pin Grid Array (PGA) Package (GAD Suffix) /C00680.13-µm/6-Level Cu Metal Process (CMOS) /C00683.3-V I/Os, 1.4-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright 2004, Texas Instruments Incorporated C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 77. recommended clock and control signal transition peripheral component interconnect (PCI) timing multichannel buffered serial port (McBSP) timing 116. . . . general-purpose input/output (GPIO) port timing 128. . . .
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SMJ320C6414, SMJ320C6415, and SMJ320C6416 device-specific data sheet. Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416 devices, have been incorporated. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS All Original release 3, 81, 82, Removed pin A24, changed Cycle-to-cycle jitter to Period jitter. GAD Ceramic PGA package (bottom view) GAD CERAMIC 570-PIN GRID ARRAY (PGA) PACKAGE (BOTTOM VIEW) 531 246 91 9 1412 11 13 17 18 24 20 22 C A B U K F E D G J H N L M R T P AD Y W V AA AC AB
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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description
The TMS320C64x DSPs (including the SMJ320C6414, SMJ320C6415, and SMJ320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C64x (C64x†) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunctional applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to thirty-six 384-Kbps or six 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128K-bit direct mapped cache and the Level 1 data cache (L1D) is a 128K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB ‡), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. All trademarks are the property of their respective owners. † Throughout the remainder of this document, the SMJ320C6414, SMJ320C6415, and SMJ320C6416 shall be referred to as SMJ320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416. ‡ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.
Table 1. Characteristics of the C6414, C6415, and C6416 Processors Device Speed section of this data sheet.
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/C0068All devices are using the same peripherals. The C6415 is pin-for-pin compatible with the C6416 when they are in the same peripheral selection mode. /C0068The BEA[9:7] pins are properly pulled up/down. Table 2. Peripherals and Coprocessors Available on the C6414, C6415, and C6416 Devices † — denotes peripheral/coprocessor is not available on this device. TMS320C6416 DSPs application report (literature number SPRA718).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block and CPU (DSP core) diagram EMIF B Test C64x DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path A A Register File A31−A16 A15−A0 Power-Down Logic SDRAM FIFO SBSRAM SRAM L1P Cache Direct-Mapped 16K Bytes Total Control Registers Control Logic L1D Cache 2-Way Set-Associative 16K Bytes Total Advanced In-Circuit Emulation Interrupt Control McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs C64x Digital Signal Processor Enhanced DMA Controller (64-channel) Memory 1024K Bytes PLL (x1, x6, x12) Timer 2 EMIF A McBSP1 ‡ McBSP0 HPI‡ ZBT SRAM Timer 1 Timer 0 McBSP2 Boot Configuration Interrupt Selector ROM/FLASH I/O Devices PCI‡ or GPIO[8:0] UTOPIA ‡ or GPIO[15:9]‡ UTOPIA: Up to 400 Mbps Master ATMC † VCP and TCP decoder coprocessors are applicable to the C6416 device only. ‡ For the C6415 and C6416 devices, the UTOPIA peripheral is MUXed with McBSP1, and the PCI peripheral is MUXed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. VCP † TCP †
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include: /C0068Register file enhancements /C0068Data path extensions /C0068Quad 8-bit and dual 16-bit extensions with data flow enhancements /C0068Additional functional unit hardware /C0068Increased orthogonality of the instruction set /C0068Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically “true”). TMS320C62x is a trademark of Texas Instruments.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 CPU (DSP core) description (continued) The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718) TMS320C67x is a trademark of Texas Instruments.
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32 MSBs
32 LSBs
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1. SMJ320C64x CPU (DSP Core) Data Paths
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 memory map summary Table 3 shows the memory map address ranges of the SMJ320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA.
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Table 3. SMJ320C64x Memory Map Summary † For the C6414 device, these memory address locations are reserved. The C6414 device does not support the UTOPIA and PCI peripherals. ‡ Only the C6416 device supports the VCP/TCP Coprocessors. For the C6414 and C6415 devices, these memory address locations are reserved.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190). Table 4. EMIFA Registers Table 5. EMIFB Registers
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Table 6. L2 Cache Registers
Table 6. L2 Cache Registers (Continued)
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Table 7. EDMA Registers
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Table 8. EDMA Parameter RAM† † The C64x device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. Table 9. Quick DMA (QDMA) and Pseudo Registers
Table 10. Interrupt Selector Registers Table 11. McBSP 0 Registers
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Table 12. McBSP 1 Registers Table 13. McBSP 2 Registers
Table 14. Timer 0 Registers input clock cycles to count. Table 15. Timer 1 Registers input clock cycles to count. Table 16. Timer 2 Registers input clock cycles to count.
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Table 17. HPI Registers † Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. Table 18. GPIO Registers
Table 19. PCI Peripheral Registers (C6415 and C6416 Only)† † These PCI registers are not supported on the C6414 device.
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Table 20. UTOPIA (C6415 and C6416 Only)† † These UTOPIA registers are not supported on the C6414 device. Table 21. UTOPIA QUEUES (C6415 and C6416 Only)† † These UTOPIA registers are not supported on the C6414 device.
Table 22. VCP Registers (C6416 Only)† † These VCP registers are supported on the C6416 device only. Table 23. TCP Registers (C6416 Only)‡ ‡ These TCP registers are supported on the C6416 device only.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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EDMA channel synchronization events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 24 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
Table 24. SMJ320C64x EDMA Channel Synchronization Events†
0 DSP_INT HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 and C6416 only)‡
1 TINT0 Timer 0 interrupt
2 TINT1 Timer 1 interrupt
3 SD_INTA EMIFA SDRAM timer interrupt
4 GPINT4/EXT_INT4 GPIO event 4/External interrupt pin 4
5 GPINT5/EXT_INT5 GPIO event 5/External interrupt pin 5
6 GPINT6/EXT_INT6 GPIO event 6/External interrupt pin 6
7 GPINT7/EXT_INT7 GPIO event 7/External interrupt pin 7
8 GPINT0 GPIO event 0
9 GPINT1 GPIO event 1
10 GPINT2 GPIO event 2
11 GPINT3 GPIO event 3
12 XEVT0 McBSP0 transmit event
13 REVT0 McBSP0 receive event
14 XEVT1 McBSP1 transmit event
15 REVT1 McBSP1 receive event
17 XEVT2 McBSP2 transmit event
18 REVT2 McBSP2 receive event
19 TINT2 Timer 2 interrupt
20 SD_INTB EMIFB SDRAM timer interrupt
28 VCPREVT VCP receive event (C6416 only)§
29 VCPXEVT VCP transmit event (C6416 only)§
30 TCPREVT TCP receive event (C6416 only)§
31 TCPXEVT TCP transmit event (C6416 only)§
32 UREVT UTOPIA receive event (C6415 and C6416 only)‡
40 UXEVT UTOPIA transmit event (C6415 and C6416 only)‡
48 GPINT8 GPIO event 8
49 GPINT9 GPIO event 9
50 GPINT10 GPIO event 10
51 GPINT11 GPIO event 11
52 GPINT12 GPIO event 12
53 GPINT13 GPIO event 13
54 GPINT14 GPIO event 14
55 GPINT15 GPIO event 15
Access (EDMA) Controller Reference Guide (literature number SPRU234). ‡ The PCI and UTOPIA peripherals are not supported on the C6414 device; therefore, these EDMA synchronization events are reserved. § The VCP/TCP EDMA synchronization events are supported on the C6416 only. For the C6414 and C6415 devices, these events are reserved.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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interrupt sources and interrupt selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and default to the interrupt source specified in Table 25. The interrupt source for interrupts 4−15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 25. C64x DSP Interrupts INT_02† − − Reserved Reserved. Do not use. INT_03† − − Reserved Reserved. Do not use. − − 10101 Reserved Reserved. Do not use. − − 10110 Reserved Reserved. Do not use. − − 11000 − 11101 Reserved Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed.
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properly enabled and configured. For more details, see the Device Configurations section of this data sheet. not support the PCI peripheral. Figure 2. CPU and Peripheral Signals
in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. Figure 3. Peripheral Signals
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not MUXed; the C6414 device does not support the PCI peripheral. MUXed; the C6414 device does not support the PCI peripheral. Figure 3. Peripheral Signals (Continued)
† For the C6415 and C6416 devices, these McBSP2 and McBSP1 pins are MUXed with the PCI and UTOPIA peripherals, respectively. Configurations section of this data sheet.
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McBSP1. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 device, these McBSP1 peripheral pins are not MUXed; the C6414 does not support the UTOPIA peripheral.
general-purpose input/output pins GP[15:9], PCI and its internal EEPROM, McBSP1, Mc BSP2, and UTOPIA). GP[8:0] pins), are always available. the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 26). internal pulldown (IPD) on the BEA11 pin. Table 26. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415/C6416 Only) McBSP1 is enabled and UTOPIA is disabled [default]. and all other standalone UTOPIA pins are tied-off (Hi-Z). UTOPIA is enabled and McBSP1 is disabled. UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z). the C6415 and C6416 devices, summarized in Table 27. internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins.
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Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) † The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. device is initialized (out of reset). as GPIO, provided the GPxEN and GPxDIR bits are properly configured. − If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. as PCI pins (for more details, see Table 29). peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes). pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin.
Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) PCI default values (default). McBSP2 peripheral pin is disabled (MCBSP2_EN = 0). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. standalone UTOPIA pins are tied-off (Hi-Z). 1 − UTOPIA peripheral enabled (McBSP1 functions are disabled). standalone McBSP1 pins are tied-off (Hi-Z).
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Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) (Continued) †For proper device operation, this pin must be externally pulled up with a 1-kΩ resistor. 0 − HPI operates as an HPI16. 1 − HPI operates as an HPI32.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 39POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those MUXed pins that are configured by software can be programmed to switch functionalities at any time. Those MUXed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 29 identifies the multiplexed pins on the C6414, C6415, and C6416 devices; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. debugging considerations It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[12, 10, 6:1]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors on the C6414, C6415, and C6416 device pins, see the terminal functions table.
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Table 29. C6414, C6415, and C6416 Device Multiplexed Pins† These pins are software-configurable. [UTOPIA_EN (BEA11) = 0 or PCI_EN = 0]. are standalone peripheral functions and are not MUXed. § For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 41POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions SIGNAL TYPE † IPD/ IPU‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN H4 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP1 § Y7 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). CLKOUT6/GP2 § T10 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKMODE1 K8 I IPD Clock mode select
- Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. CLKMODE0 E3 I IPD
- Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLLV ¶ L9 A# PLL voltage supply JTAG EMULATION TMS V14 I IPU JTAG test-port mode select TDO W16 O/Z IPU JTAG test-port data out TDI AA17 I IPU JTAG test-port data in TCK Y15 I IPU JTAG test-port clock TRST Y14 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU11 V15 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected. EMU10 Y16 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected. EMU9 T14 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 U14 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 AB18 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 AA16 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 W15 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 AB17 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 W14 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 AA15 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 EMU0 T13 V13 I/O/Z IPU Emulation [1:0] pins
- Select the device functional mode of operation EMU[1:0] Operation
00 Boundary Scan/Normal Mode (see Note)
01 Reserved
10 Reserved
11 Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal mode. For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resister. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. ¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter)
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AB5 I Device reset NMI E6 I IPD Nonmaskable interrupt, edge-driven (rising edge) GP7/EXT_INT7 Y6 General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only.GP6/EXT_INT6 V8 I/O/Z IPU General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. When these pins function as External Interrupts [by selecting the corresponding interruptGP5/EXT_INT5 AA5 I/O/Z IPU • When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be GP4/EXT_INT4 U9 enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). GP15/PRST § J8 General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GP14/PCLK § G5 GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GP13/PINTA§ G4 GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GP12/PGNT § J7 GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GP11/PREQ § H6 GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GP10/PCBE3 § L7 I/O/Z GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP9/PIDSEL § K6 I/O/Z GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. GP3 AA6 IPD GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only. GP0 W8 IPD GPIO 0 pin. The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). CLKS2/GP8 §¶ W7 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro- grammed as a GPIO 8 pin (I/O/Z). CLKOUT6/GP2 §¶ T10 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKOUT4/GP1 §¶ Y7 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] PCI_EN T8 I IPD PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Con- figurations section of this data sheet). The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on this pin. HINT/PFRAME § P4 I/O/Z Host interrupt from DSP to host (O ) [default] or PCI frame (I/O/Z) HCNTL1/ PDEVSEL § N8 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). HCNTL0/ PSTOP § P5 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) HHWIL/PTRDY § N5 I/O/Z Host half-word select − first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z) HR/W /PCBE2 § N6 I/O/Z Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device. ¶ For the C6414 device, only these pins are multiplexed pins.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] (CONTINUED) HAS /PPAR § N7 I/O/Z Host address strobe (I) [default] or PCI parity (I/O/Z) HCS /PPERR § N9 I/O/Z Host chip select (I) [default] or PCI parity error (I/O/Z) HDS1 /PSERR § R5 I/O/Z Host data strobe 1 (I) [default] or PCI system error (I/O/Z) HDS2 /PCBE1 § P6 I/O/Z Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) HRDY /PIRDY§ N4 I/O/Z Host ready from DSP to host (O ) [default] or PCI initiator ready (I/O/Z). HD31/AD31 § J4 HD30/AD30 § K7 HD29/AD29 § J5 HD28/AD28 § K4 HD27/AD27 § K5 HD26/AD26 § L6 HD25/AD25 § L8 HD24/AD24 § J6 HD23/AD23 § L5 HD22/AD22 § M5 Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415 and C6416] HD21/AD21 § M6 As HPI data bus (PCI_EN pin = 0) HD20/AD20 § M8 As HPI data bus (PCI_EN pin = 0)
- Used for transfer of data, address, and control HD19/AD19 § L4
- Used for transfer of data, address, and control
- Host-Port bus width user-configurable at device reset via a 10-kΩ resistor pullup/pulldown resistor on the HD5 pin:HD18/AD18 § M4 resistor on the HD5 pin: HD17/AD17 § M9 HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are HD16/AD16 § M7 I/O/Z HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD15/AD15 § P8 I/O/Z reserved pins in the high-impedance state.) HD14/AD14 § R6 HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)HD13/AD13 § R4 HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) HD12/AD12 § P7 As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only] HD11/AD11 § R7 As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only]
- Used for transfer of data and address HD10/AD10 § T5 Used for transfer of data and address The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are HD9/AD9 § T4 The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are standalone peripheral functions, not MUXed. HD8/AD8 § P9 standalone peripheral functions, not MUXed. HD7/AD7 § T6 HD6/AD6 § R8 HD5/AD5 § U4 HD4/AD4 § U5 HD3/AD3 § T7 HD2/AD2 § U6 HD1/AD1 § V4 HD0/AD0 § V5 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] (CONTINUED) PCBE0 Y3 I/O/Z PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or ground).” XSP_CS AA3 O IPD PCI serial interface chip select (O ). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or ground).” CLKX2/ XSP_CLK § W5 I/O/Z IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O ). DR2/XSP_DI § Y4 I IPU McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. DX2/XSP_DO § R9 O/Z IPU McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O ). In PCI mode, this pin is connected to the input data pin of the serial PROM. GP15/PRST § J8 General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GP14/PCLK § G5 GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GP13/PINTA§ G4 GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GP12/PGNT § J7 I/O/Z GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GP11/PREQ § H6 I/O/Z GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GP10/PCBE3 § L7 GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP9/PIDSEL § K6 GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ||/C0107 ACE3 K20 O/Z IPU EMIFA memory space enablesACE2 L17 O/Z IPU EMIFA memory space enables
- Enabled by bits 28 through 31 of the word addressACE1 J21 O/Z IPU
- Enabled by bits 28 through 31 of the word address
- Only one pin is asserted during any external data access ACE0 K19 O/Z IPU
- Only one pin is asserted during any external data access ABE7 P19 O/Z IPU ABE6 U22 O/Z IPU ABE5 T22 O/Z IPU EMIFA byte-enable control Decoded from the low-order address bits. The number of address bits or byte enables ABE4 R21 O/Z IPU EMIFA byte-enable control
- Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory.ABE3 M17 O/Z IPU used depends on the width of external memory.
- Byte-write enables for most types of memory ABE2 M18 O/Z IPU
- Byte-write enables for most types of memory
- Can be directly connected to SDRAM read and write mask signal (SDQM) ABE1 H22 O/Z IPU Can be directly connected to SDRAM read and write mask signal (SDQM) ABE0 L19 O/Z IPU APDT L20 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device. ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 45POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFA (64-BIT) − BUS ARBITRATION||/C0107 AHOLDA M19 O IPU EMIFA hold-request-acknowledge to the host AHOLD U21 I IPU EMIFA hold request from the host ABUSREQ P21 O IPU EMIFA bus request output EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL ||/C0107 AECLKIN J19 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins. AECLKIN is the default for the EMIFA input clock. AECLKOUT2 K18 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. AECLKOUT1 H21 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. AARE / ASDCAS / ASADS /ASRE L16 O/Z IPU EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable
- For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. AAOE / ASDRAS / ASOE J20 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable AAWE / ASDWE / ASWE G22 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchro- nous interface write-enable ASDCKE K21 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
- If SDRAM is not in system, ASDCKE can be used as a general-purpose output. ASOE3 N16 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) AARDY L18 I IPU Asynchronous memory ready input EMIFA (64-BIT) − ADDRESS||/C0107 AEA22 R20 AEA21 P16 AEA20 T20 AEA19 R18 AEA18 V22 AEA17 R19 O/Z IPD EMIFA external address (doubleword address)AEA16 T21 O/Z IPD EMIFA external address (doubleword address) AEA15 P17 AEA14 N18 AEA13 P18 AEA12 P20 AEA11 N17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFA (64-BIT) − ADDRESS||/C0107 (CONTINUED) AEA10 N20 AEA9 N21 AEA8 N19 AEA7 M21 O/Z IPD EMIFA external address (doubleword address)AEA6 M20 O/Z IPD EMIFA external address (doubleword address) AEA5 L21 AEA4 M16 AEA3 J22 EMIFA (64-bit) − DATA||/C0107 AED63 AB21 AED62 W18 AED61 Y19 AED60 V17 AED59 AA20 AED58 AA19 AED57 Y18 AED56 T15 AED55 U16 AED54 AB20 AED53 AA18 AED52 V16 AED51 W17 AED50 Y17 I/O/Z IPU EMIFA external data AED49 U15 I/O/Z IPU EMIFA external data AED48 AB19 AED47 T19 AED46 U20 AED45 R17 AED44 Y22 AED43 V21 AED42 T18 AED41 U19 AED40 W21 AED39 V20 AED38 R16 AED37 T17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFA (64-bit) − DATA||/C0107 (CONTINUED) AED36 U18 AED35 Y21 AED34 V19 AED33 W20 AED32 AA22 AED31 D22 AED30 G19 AED29 F20 AED28 H18 AED27 E21 AED26 F21 AED25 G20 AED24 K16 AED23 J17 AED22 E22 AED21 G21 AED20 J18 AED19 H19 AED18 H20 I/O/Z IPU EMIFA external data AED17 K17 I/O/Z IPU EMIFA external data AED16 F22 AED15 F16 AED14 E17 AED13 H15 AED12 C20 AED11 D18 AED10 G16 AED9 F17 AED8 D19 AED7 E18 AED6 J15 AED5 H16 AED4 G17 AED3 D20 AED2 F18 AED1 E19 AED0 C21 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ||/C0107 BCE3 D11 O/Z IPU EMIFB memory space enablesBCE2 C9 O/Z IPU EMIFB memory space enables
- Enabled by bits 26 through 31 of the word addressBCE1 H12 O/Z IPU
- Enabled by bits 26 through 31 of the word address
- Only one pin is asserted during any external data access BCE0 G12 O/Z IPU
- Only one pin is asserted during any external data access BBE1 D12 O/Z IPU EMIFB byte-enable control
- Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. BBE0 E12 O/Z IPU used depends on the width of external memory.
- Byte-write enables for most types of memory
- Can be directly connected to SDRAM read and write mask signal (SDQM) BPDT E11 O/Z IPU EMIFB peripheral data transfer, allows direct transfer between external peripherals EMIFB (16-BIT) − BUS ARBITRATION||/C0107 BHOLDA F12 O IPU EMIFB hold-request-acknowledge to the host BHOLD C19 I IPU EMIFB hold request from the host BBUSREQ D14 O IPU EMIFB bus request output EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL ||/C0107 BECLKIN E10 I IPD EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins. BECLKIN is the default for the EMIFB input clock. BECLKOUT2 C8 O/Z IPD EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided by 1, 2, or 4. BECLKOUT1 J12 O/Z IPD EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. BARE / BSDCAS / BSADS /BSRE C7 O/Z IPU EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable
- For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between BSADS and BSRE: If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal. If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal. BAOE / BSDRAS / BSOE D10 O/Z IPU EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable BAWE /BSDWE / BSWE F11 O/Z IPU EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro- nous interface write-enable BSOE3 J13 O/Z IPU EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface) BARDY G11 I IPU EMIFB asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFB (16-BIT) − ADDRESS||/C0107 BEA20 E15 IPU EMIFB external address (half-word address) (O/Z)
- Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors − Device Endian mode BEA19 D17 IPU Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors − Device Endian mode BEA20: 0 – Big Endian 1 − Little Endian (default mode) BEA18 J14 1 − Little Endian (default mode) − Boot mode BEA[19:18]: 00 – No boot 01 − HPI boot BEA17 E16 BEA[19:18]: 00 – No boot 01 − HPI boot 10 − EMIFB 8-bit ROM boot with default timings (default mode) 11 − Reserved BEA16 G15 11 − Reserved − EMIF clock select BEA15 C18 − EMIF clock select BEA[17:16]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 − CPU/4 Clock Rate BEA14 F15 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate 11 − Reserved BEA13 D16 11 − Reserved BEA[15:14]: Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 – BECLKIN (default mode) BEA12 H14 BEA[15:14]: Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 – BECLKIN (default mode) 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate BEA11 F14 10 − CPU/6 Clock Rate 11 − Reserved BEA10 C17 I/O/Z IPD − PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only] BEA13: PCI auto-initialization via external EEPROM If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. BEA9 G13 I/O/Z IPD If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. 0 − PCI auto-initialization through EEPROM is disabled (default). 1 − PCI auto-initialization through EEPROM is enabled. BEA8 G14 1 − PCI auto-initialization through EEPROM is enabled. − UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only] BEA11: UTOPIA peripheral enable (functional) BEA7 E14 − UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only] BEA11: UTOPIA peripheral enable (functional) 0 − UTOPIA disabled (McBSP1 enabled) [default] 1 − UTOPIA enabled (McBSP1 disabled) BEA6 H13 1 − UTOPIA enabled (McBSP1 disabled) The C6414 device does not support the PCI and UTOPIA peripherals; for proper device do not BEA5 C16 The C6414 device does not support the PCI and UTOPIA peripherals; for proper device operation, do not oppose the internal pulldowns (IPDs) on the BEA13 and BEA11 pins. Also for proper C6414 device operation, do not oppose the IPDs on the BEA7, BEA8, BEA4 D15 Also for proper C6414 device operation, do not oppose the IPDs on the BEA7, BEA8, and BEA9 pins. BEA3 E13 For proper C6415 device operation, the BEA7 pin must be externally pulled up with a 1-kΩ resistor. BEA2 D13 1-k resistor. For proper C6416 device operation, the BEA8 and BEA9 pins must be externally pulled up with a 1-kΩ resistor. BEA1 F13 up with a 1-kΩ resistor. For more details, see the Device Configurations section of this data sheet. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION EMIFB (16-bit) − DATA||/C0107 BED15 F8 BED14 J10 BED13 D7 BED12 C5 BED11 H10 BED10 G9 BED9 C6 BED8 E8 I/O/Z IPU EMIFB external dataBED7 E9 I/O/Z IPU EMIFB external data BED6 F9 BED5 G10 BED4 J11 BED3 D9 BED2 D8 BED1 H11 BED0 F10 MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) MCBSP2_EN AB4 I IPD McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data sheet). CLKS2/GP8 § W7 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be programmed as a GPIO 8 pin (I/O/Z). CLKR2 W4 I/O/Z IPD McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. CLKX2/ XSP_CLK § W5 I/O/Z IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O ). DR2/XSP_DI § Y4 I IPU McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. DX2/XSP_DO § R9 O/Z IPU McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O ). In PCI mode, this pin is connected to the input data pin of the serial PROM. FSR2 V6 I/O/Z IPD McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. FSX2 U7 I/O/Z IPD McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins except CLKS2/GP8 are standalone peripheral functions for this device. ||These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. /C0107To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1/ URADDR3 § Y8 I McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive address 3 pin (I) CLKR1/ URADDR2 § AB7 I/O/Z McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I) CLKX1/ URADDR4 § T12 I/O/Z McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I) DR1/ UXADDR1 § V11 I McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I) DX1/ UXADDR4 § Y10 I/O/Z McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I) FSR1/ UXADDR2 § AA8 I/O/Z McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I) FSX1/ UXADDR3 § AA11 I/O/Z McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I) MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 F4 I IPD McBSP0 external clock source (as opposed to internal) CLKR0 F5 I/O/Z IPD McBSP0 receive clock CLKX0 K9 I/O/Z IPD McBSP0 transmit clock DR0 G6 I IPU McBSP0 receive data DX0 E4 O/Z IPU McBSP0 transmit data FSR0 D3 I/O/Z IPD McBSP0 receive frame sync FSX0 H7 I/O/Z IPD McBSP0 transmit frame sync TIMER 2 TOUT2 F7 O/Z IPD Timer 2 or general-purpose output TINP2 D5 I IPD Timer 2 or general-purpose input TIMER 1 TOUT1 G8 O/Z IPD Timer 1 or general-purpose output TINP1 D6 I IPD Timer 1 or general-purpose input TIMER 0 TOUT0 H9 O/Z IPD Timer 0 or general-purpose output TINP0 E7 I IPD Timer 0 or general-purpose input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE] [C6415 and C6416 devices only] UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE UXCLK /C0089 AB8 I /C0104Source clock for UTOPIA transmit driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. UXCLAV /C0089AA13 O/Z Transmit cell available status output signal from UTOPIA Slave. 0 indicates a complete cell is NOT available for transmit 1 indicates a complete cell is available for transmit When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. UXENB /C0089 U13 I ◊ UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indi- cate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and the UXSOC signal in the next clock cycle. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. UXSOC /C0089 Y12 O/Z Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. DX1/ UXADDR4 § Y10 I/O/Z ◊ McBSP1 [default] or UTOPIA transmit address pins As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
- 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System.
- UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN- NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. FSX1/ UXADDR3 § AA11 I/O/Z ◊ McBSP1 [default] or UTOPIA transmit address pins As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: FSR1/ UXADDR2 § AA8 I/O/Z ◊ As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
- 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. DR1/ UXADDR1 § V11 I ◊
- UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN-UXADDR0 /C0089Y9 I ◊ For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN - NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device. /C0104For the C6415 and C6416 devices, external pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. ◊ For the C6415 and C6416 devices, external pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary. ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [/C0104] footnote).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE (CONTINUED) UXDATA7 /C0089W10 UXDATA6 /C0089T11 UXDATA5 /C0089W9 8-bit Transmit Data Bus Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmitsUXDATA4 /C0089AB6 O/Z 8-bit Transmit Data Bus Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.UXDATA3 /C0089V10 O/Z the 8-bit ATM cells to the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied- UXDATA2 /C0089U10 When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied- off. UXDATA1 /C0089AA7 off. UXDATA0 /C0089V9 UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE URCLK /C0089 U12 I /C0104Source clock for UTOPIA receive driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URCLAV /C0089AA14 O/Z Receive cell available status output signal from UTOPIA Slave. 0 indicates NO space is available to receive a cell from Master ATM Controller 1 indicates space is available to receive a cell from Master ATM Controller When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URENB /C0089 AB16 I ◊ UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indi- cate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URSOC /C0089 W13 I /C0104 Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to the UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive Data Bus (URDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. CLKX1/ URADDR4 § T12 I/O/Z ◊ McBSP1 [default] or UTOPIA receive address pins As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: CLKS1/ URADDR3 § Y8 I ◊ As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
- 5-bit Slave receive address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. CLKR1/ URADDR2 § AB7 I/O/Z ◊ select one of the Slave devices (up to 31 possible) in the ATM System.
- URADDR1 and URADDR0 pins are tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] URADDR1 /C0089U11 I ◊ [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN- URADDR0 /C0089AA9 I ◊ For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN- NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. /C0104External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. ◊ External pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary. ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [/C0104] footnote).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Terminal Functions (Continued) SIGNAL TYPE † IPD/ ‡ DESCRIPTIONNAME NO. TYPE † IPD/ IPU‡ DESCRIPTION UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE (CONTINUED) URDATA7 /C0089AA10 URDATA6 /C0089V12 URDATA5 /C0089W12 8-bit Receive Data Bus. Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receiveURDATA4 /C0089W11 I /C0104 8-bit Receive Data Bus. Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.URDATA3 /C0089Y11 I /C0104the 8-bit ATM cell data from the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied- URDATA2 /C0089AB9 When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied- off. URDATA1 /C0089Y13 off. URDATA0 /C0089AA12 RESERVED FOR TEST RSV H3 Reserved (leave unconnected, do not connect to power or ground)RSV Reserved (leave unconnected, do not connect to power or ground) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) /C0104External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [/C0104] footnote).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS AA23 AB10 AB11 AB14 AB15 AB2 AB23 AC10 AC12 AC14 AC16 AC19 AC21 AC22 AC3 AC4 AC6 AC8 B11 B13 DV DD B15 S 3.3-V supply voltageDV DD B17 S 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet) B19 (see the Power-Supply Decoupling section of this data sheet) B21 B22 C10 C11 C14 C15 C23 D23 F23 J23 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) K22 L22 L23 N23 P22 3.3-V supply voltageDV DD R22 S 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet)DV DD R23 S (see the Power-Supply Decoupling section of this data sheet) U23 W23 A10 A12 A14 A16 A18 A20 A22 1.4 V supply voltageCV DD AA1 S 1.4 V supply voltage (see the Power-Supply Decoupling section of this data sheet)CV DD AB12 S (see the Power-Supply Decoupling section of this data sheet) AB13 AB24 AC18 AC20 AC5 AD11 AD13 AD15 AD17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) AD19 AD21 AD23 AD3 AD5 AD7 AD9 B20 B24 C12 C13 D24 E23 F24 1.4 V supply voltageCV DD G1 S 1.4 V supply voltage (see the Power-Supply Decoupling section of this data sheet)CV DD G23 S (see the Power-Supply Decoupling section of this data sheet) H24 K10 K12 K14 K24 L11 L13 L15 M10 M12 M14 M22 M24 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED N11 N13 N15 N22 P10 P12 P14 P24 1.4 V supply voltageCV DD R11 S 1.4 V supply voltage (see the Power-Supply Decoupling section of this data sheet)CV DD R13 S (see the Power-Supply Decoupling section of this data sheet) R15 T24 V24 Y23 Y24 GROUND PINS A11 A13 A15 A17 A19 A21 A23 VSS GND Ground pinsVSS AA2 GND Ground pins AA21 AA24 AA4 AB1 AB22 AB3 AC1 AC11 AC13 AC15 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 59POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS AC17 AC2 AC23 AC24 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD2 AD20 AD22 AD4 AD6 AD8 B10 B12 VSS B14 GND Ground pinsVSS B16 GND Ground pins B18 B23 C22 C24 D21 E20 E24 F19 G18 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS (CONTINUED) G24 H17 H23 J16 J24 K11 K13 K15 K23 L10 L12 L14 VSS L2 GND Ground pinsVSS L24 GND Ground pins M11 M13 M15 M23 N10 N12 N14 N24 P11 P13 P15 P23 R10 R12 R14 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 61POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS (CONTINUED) R24 T16 T23 U17 U24 VSS V1 GND Ground pinsVSS V18 GND Ground pins V23 W19 W24 Y20 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 63POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each military TMS320 DSP family member has one of three prefixes: SMX, TMP, or SMJ. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: SMX Preproduction device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SMJ Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product SMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (SMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that preproduction or prototype devices (SMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GAD), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -6E3 is 600-MHz CPU, 133-MHz EMIFA). Figure 4 provides a legend for reading the complete device name for any SMJ320C64x DSP generation member. TMS320 is a trademark of Texas Instruments.
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Table 30. SMJ320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information
† See the Recommended Operating Conditions section of this data sheet for more details. ‡ The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices. See the Recommended Operating Conditions section of this data sheet for more details. ¶ For the actual device part numbers (P/Ns) and ordering information, see Table 30 of this data sheet. Figure 4. SMJ320C64x DSP Device Nomenclature (Including the C6414, C6415, and C6416 Devices)
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C6414, TMS320C6415, and TMS320C6416 Digital Signal Processors Silicon Errata (literature number SPRZ011) describes the known exceptions to the functional specifications for the SMJ320C6414, SMJ320C6415, and SMJ320C6416 devices. The TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811) discusses the power consumption for user applications with the SMJ320C6414, SMJ320C6415, and SMJ320C6416 DSP devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718), which describes in more details the compatibility and similarities/differences among the C6414, C6415, C6416, and C6211 devices.
bypasses the PLL to become the internal CPU clock. shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. clock timing requirements, see the input and output clocks electrical section. Table 31. Compatible CLKIN External Clock Sources
342 Corning Frequency Control
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components other than the ones shown. C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
Table 32. SMJ320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡ † These clock frequency range values are applicable to a C64x−60 speed device.. modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured. (enabled). Default values are device-specific, so refer to Figure 6 for the C6414/15/16 default configuration. Figure 6. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] default, all the GPIO pins are configured as input pins. Figure 7. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 9. PWRD Field of the CSR Register first, then the program execution returns to the instruction where PD1 took effect. PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes. Table 33. Characteristics of the Power-Down Modes
000000 No power-down — —
001001 PD1 Wake by an enabled interruptCPU halted (except for the interrupt logic)
010001 PD1 Wake by an enabled or
between peripherals and internal memory.
011010 PD2 † Wake by a device reset
011100 PD3 † Wake by a device reset
PLL needs time to re-lock, just as it does following power-up. the PLL needs to be re-locked, just as it does following power-up. peripherals will not operate according to specifications.
reset will be required to get the DSP out of PD2/PD3. (>1 second) if the other supply is below the proper operating voltage. power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10). Figure 10. Schottky Diode Diagram core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. lifetime should be considered.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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IEEE 1149.1 JTAG compatibility statement The SMJ320C6414/15/16 DSP requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. For maximum reliability, the SMJ320C6414/15/16 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after power up and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. EMIF device speed The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM interface when in a system that meets the following requirements: − 1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF − up to 1 CE space of buffers connected to EMIF − EMIF trace lengths between 1 and 3 inches − 166-MHz SDRAM for 133-MHz operation (applies only to EMIFA) − 143-MHz SDRAM for 100-MHz operation Other configurations may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 75POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 bootmode The C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode. The C6414/C6415/C6416 has three types of boot modes: /C0068Host boot If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the C6414 device, the HPI peripheral is used for host boot. For the C6415/C6416 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received. /C0068EMIF boot (using default ROM timings) Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and starts running from address 0. /C0068No boot With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is undefined if invalid code is located at address 0.
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implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . ‡ Future variants of the C641x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options. incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C641x devices. § The absolute maximum ratings should not be exceeded for more than 30% of the cycle period. Figure 11. Impact of Elevated Temperature on Device Life
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 77POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT VOH High-level output voltage (except PCI)DV DD = MIN, I OH = MAX 2.4 V VOHP High-level output voltage (PCI) [C6415/C6416 only] IOHP = −0.5 mA, DV DD = 3.3 V 0.9DVDD ¶ V VOL Low-level output voltage (except PCI)DV DD = MIN, I OL = MAX 0.4 V VOLP Low-level output voltage (PCI) [C6415/C6416 only] IOLP = 1.5 mA, DV DD = 3.3 V 0.1DVDD ¶ V VI = VSS to DVDD no opposing internal resistor ±10 uA II Input current (except PCI) VI = VSS to DVDD opposing internal pullup resistor‡ 50 100 150 uA VI = VSS to DVDD opposing internal pulldown resistor‡ −150 −100 −50 uA IIP Input leakage current (PCI) [C6415/C6416 only]§ 0 < VIP < DVDD = 3.3 V ±10 uA EMIF, CLKOUT4, CLKOUT6, EMUx −16 mA IOH High-level output current Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP −8 mA PCI/HPI −0.5¶ mA EMIF, CLKOUT4, CLKOUT6, EMUx 16 mA IOL Low-level output current Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP 8 mA PCI/HPI 1.5¶ mA IOZ Off-state output current VO = DVDD or 0 V ±10 uA ICDD Core supply current# CV DD = 1.4 V, CPU clock = 600 MHz 750 mA IDDD I/O supply current# DV DD = 3.3 V, CPU clock = 600 MHz 125 mA C i Input capacitance 12 pF C o Output capacitance 12 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. § PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. ¶ These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4, respectively. # Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811). recommended clock and control signal transition behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
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must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 12. Test Load Circuit for AC Timing Measurements the maximum load the device is capable of driving. All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements Figure 14. Rise and Fall Transition Time Voltage Reference Levels All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
may be used to compensate any timing differences. but also tends to improve the input hold time margins (see Table 34 and Figure 15). board route delays and how they are perceived by the DSP and the external device. Table 34. Board-Level Timings
1 Clock route delay
2 Minimum DSP hold time
3 Minimum DSP setup time
4 External device hold time requirement
5 External device setup time requirement
6 Control signal route delay
7 External device hold time
8 External device access time
9 DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
† Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 15. Board-Level Input/Output Timings
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*This parameter is not production tested. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Figure 16. CLKIN Timing
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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. ¶ Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. 100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. Figure 19. ECLKIN Timing for EMIFA and EMIFB *This parameter is not production tested. prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. # The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ||E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. /C0107EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB. /C0104This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles for EMIFA module†‡§ (see Figure 22 and Figure 23) NO. MIN MAX UNIT 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns 6 tsu(ARDY-EKO1H) Setup time, ARDY valid before ECLKOUTx high 3 ns 7 th(EKO1H-ARDY) Hold time, ARDY valid after ECLKOUTx high 1 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFA module‡§¶# (see Figure 22 and Figure 23) NO. PARAMETER MIN MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 2 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E − 1.9 ns 5 td(EKO1H-AREV) Delay time, ECLKOUTx high to ARE valid 1 7 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 1.7 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 1.8 ns 10 td(EKO1H-AWEV) Delay time, ECLKOUTx high to AWE valid 1.3 7.1 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 85POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ASYNCHRONOUS MEMORY TIMING (CONTINUED) timing requirements for asynchronous memory cycles for EMIFB module†‡§ (see Figure 22 and Figure 23) NO. MIN MAX UNIT 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.2 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns 6 tsu(ARDY-EKO1H) Setup time, ARDY valid before ECLKOUTx high 3 ns 7 th(EKO1H-ARDY) Hold time, ARDY valid after ECLKOUTx high 1.2 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFB module‡§¶# (see Figure 22 and Figure 23) NO. PARAMETER MIN MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 2 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E − 1.7 ns 5 td(EKO1H-AREV) Delay time, ECLKOUTx high to ARE valid 0.8 6.6 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 1.9 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 1.7 ns 10 td(EKO1H-AWEV) Delay time, ECLKOUTx high to AWE valid 0.9 6.7 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
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respectively, during asynchronous memory accesses. Figure 22. Asynchronous Memory Read Timing for EMIFA and EMIFB†
respectively, during asynchronous memory accesses. Figure 23. Asynchronous Memory Write Timing for EMIFA and EMIFB†
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles for EMIFA module† (see Figure 24) NO. MIN MAX UNIT 6 tsu(EDV-EKOxH) Setup time, read EDx valid before ECLKOUTx high 2 ns 7 th(EKOxH-EDV) Hold time, read EDx valid after ECLKOUTx high 1.5 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE , ASOE, and ASWE (for EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for EMIFA module†‡ (see Figure 24−Figure 26) NO. PARAMETER MIN MAX UNIT 1 td(EKOxH-CEV) Delay time, ECLKOUTx high to CEx valid 1.3 4.9 ns 2 td(EKOxH-BEV) Delay time, ECLKOUTx high to BEx valid 5.1 ns 3 td(EKOxH-BEIV) Delay time, ECLKOUTx high to BEx invalid 1.3 ns 4 td(EKOxH-EAV) Delay time, ECLKOUTx high to EAx valid 4.9 ns 5 td(EKOxH-EAIV) Delay time, ECLKOUTx high to EAx invalid 1.3 ns 8 td(EKOxH-ADSV) Delay time, ECLKOUTx high to SADS/SRE valid 1.3 4.9 ns 9 td(EKOxH-OEV) Delay time, ECLKOUTx high to, SOE valid 1.3 4.9 ns 10 td(EKOxH-EDV) Delay time, ECLKOUTx high to EDx valid 4.9 ns 11 td(EKOxH-EDIV) Delay time, ECLKOUTx high to EDx invalid 1.3 ns 12 td(EKOxH-WEV) Delay time, ECLKOUTx high to SWE valid 1.3 4.9 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE , ASOE, and ASWE (for EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 89POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) timing requirements for programmable synchronous interface cycles for EMIFB module† (see Figure 24) NO. MIN MAX UNIT 6 tsu(EDV-EKOxH) Setup time, read EDx valid before ECLKOUTx high 3.1 ns 7 th(EKOxH-EDV) Hold time, read EDx valid after ECLKOUTx high 1.5 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE , ASOE, and ASWE (for EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for EMIFB module†‡ (see Figure 24−Figure 26) NO. PARAMETER MIN MAX UNIT 1 td(EKOxH-CEV) Delay time, ECLKOUTx high to CEx valid 1.3 6.4 ns 2 td(EKOxH-BEV) Delay time, ECLKOUTx high to BEx valid 6.4 ns 3 td(EKOxH-BEIV) Delay time, ECLKOUTx high to BEx invalid 1.3 ns 4 td(EKOxH-EAV) Delay time, ECLKOUTx high to EAx valid 6.4 ns 5 td(EKOxH-EAIV) Delay time, ECLKOUTx high to EAx invalid 1.3 ns 8 td(EKOxH-ADSV) Delay time, ECLKOUTx high to SADS/SRE valid 1.3 6.4 ns 9 td(EKOxH-OEV) Delay time, ECLKOUTx high to, SOE valid 1.3 6.4 ns 10 td(EKOxH-EDV) Delay time, ECLKOUTx high to EDx valid 6.4 ns 11 td(EKOxH-EDIV) Delay time, ECLKOUTx high to EDx invalid 1.3 ns 12 td(EKOxH-WEV) Delay time, ECLKOUTx high to SWE valid 1.3 6.4 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE , ASOE, and ASWE (for EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). programmable synchronous interface accesses. Figure 24. Programmable Synchronous Interface Read Timing for EMIFA and EMIFB
EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). programmable synchronous interface accesses. Figure 25. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB
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EMIFA) and BSADS/BSRE , BSOE, and BSWE (for EMIFB)]. Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). programmable synchronous interface accesses. Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 93POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles for EMIFA module† (see Figure 27) NO. MIN MAX UNIT 6 tsu(EDV-EKO1H) Setup time, read EDx valid before ECLKOUTx high 0.6 ns 7 th(EKO1H-EDV) Hold time, read EDx valid after ECLKOUTx high 1.8 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE , and SDRAS ) instead of ASDCAS, ASDWE , and ASDRAS (for EMIFA) and BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA module† (see Figure 27−Figure 34) NO. PARAMETER MIN MAX UNIT 1 td(EKO1H-CEV) Delay time, ECLKOUTx high to CEx valid 1.3 4.9 ns 2 td(EKO1H-BEV) Delay time, ECLKOUTx high to BEx valid 4.9 ns 3 td(EKO1H-BEIV) Delay time, ECLKOUTx high to BEx invalid 1.3 ns 4 td(EKO1H-EAV) Delay time, ECLKOUTx high to EAx valid 4.9 ns 5 td(EKO1H-EAIV) Delay time, ECLKOUTx high to EAx invalid 1.3 ns 8 td(EKO1H-CASV) Delay time, ECLKOUTx high to SDCAS valid 1.3 4.9 ns 9 td(EKO1H-EDV) Delay time, ECLKOUTx high to EDx valid 4.9 ns 10 td(EKO1H-EDIV) Delay time, ECLKOUTx high to EDx invalid 1.3 ns 11 td(EKO1H-WEV) Delay time, ECLKOUTx high to SDWE valid 1.3 4.9 ns 12 td(EKO1H-RAS) Delay time, ECLKOUTx high to SDRAS valid 1.3 4.9 ns 13 td(EKO1H-ACKEV) Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only) 1.3 4.9 ns 14 td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 4.9 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE , and SDRAS ) instead of ASDCAS, ASDWE , and ASDRAS (for EMIFA) and BSDCAS , BSDWE , and BSDRAS (for EMIFB)].
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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SYNCHRONOUS DRAM TIMING (CONTINUED) timing requirements for synchronous DRAM cycles for EMIFB module† (see Figure 27) NO. MIN MAX UNIT 6 tsu(EDV-EKO1H) Setup time, read EDx valid before ECLKOUTx high 2.1 ns 7 th(EKO1H-EDV) Hold time, read EDx valid after ECLKOUTx high 2.5 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE , and SDRAS ) instead of ASDCAS, ASDWE , and ASDRAS (for EMIFA) and BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFB module† (see Figure 27−Figure 34) NO. PARAMETER MIN MAX UNIT 1 td(EKO1H-CEV) Delay time, ECLKOUTx high to CEx valid 1.3 6.4 ns 2 td(EKO1H-BEV) Delay time, ECLKOUTx high to BEx valid 6.4 ns 3 td(EKO1H-BEIV) Delay time, ECLKOUTx high to BEx invalid 1.3 ns 4 td(EKO1H-EAV) Delay time, ECLKOUTx high to EAx valid 6.4 ns 5 td(EKO1H-EAIV) Delay time, ECLKOUTx high to EAx invalid 1.3 ns 8 td(EKO1H-CASV) Delay time, ECLKOUTx high to SDCAS valid 1.3 6.4 ns 9 td(EKO1H-EDV) Delay time, ECLKOUTx high to EDx valid 6.4 ns 10 td(EKO1H-EDIV) Delay time, ECLKOUTx high to EDx invalid 1.3 ns 11 td(EKO1H-WEV) Delay time, ECLKOUTx high to SDWE valid 1.3 6.4 ns 12 td(EKO1H-RAS) Delay time, ECLKOUTx high to SDRAS valid 1.3 6.4 ns 13 td(EKO1H-ACKEV) Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only) 1.3* 6.4* ns 14 td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 6.4 ns *This parameter is not production tested. † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE , and SDRAS ) instead of ASDCAS, ASDWE , and ASDRAS (for EMIFA) and BSDCAS , BSDWE , and BSDRAS (for EMIFB)].
BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. respectively. PDTRL equals 00 (zero latency) in Figure 27. Figure 27. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB†
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BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28. Figure 28. SDRAM Write Command for EMIFA and EMIFB†
BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. Figure 29. SDRAM ACTV Command for EMIFA and EMFB †
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BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. Figure 30. SDRAM DCAB Command for EMIFA and EMIFB†
BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. Figure 31. SDRAM DEAC Command for EMIFA and EMIFB†
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BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. Figure 32. SDRAM REFR Command for EMIFA and EMIFB†
BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. Figure 33. SDRAM MRS Command for EMIFA and EMIFB†
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BSDCAS , BSDWE , and BSDRAS (for EMIFB)]. respectively, during SDRAM accesses. Figure 34. SDRAM Self-Refresh Timing for EMIFA Only†
*This parameter is not production tested. † E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. *This parameter is not production tested. † E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. AAWE /ASDWE /ASWE , ASDCKE, ASOE3 , and APDT. BAWE /BSDWE /BSWE , BSOE3, and BPDT. ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35. time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. AAWE /ASDWE /ASWE , ASDCKE, ASOE3 , and APDT. BAWE /BSDWE /BSWE , BSOE3, and BPDT. ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35. Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB
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Figure 36. BUSREQ Timing for EMIFA and EMIFB
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 105POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RESET TIMING timing requirements for reset† (see Figure 37) NO. MIN MAX UNIT 1 tw(RST) Width of the RESET pulse (PLL stable)‡ 10P* ns 1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§ 250* µs 16 tsu(boot) Setup time, boot configuration bits valid before RESET high¶ 4P* ns 17 th(boot) Hold time, boot configuration bits valid after RESET high¶ 4P* ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable. § This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. ¶ EMIFB address pins BEA[20:13, 11, 7] are the boot configuration pins during device reset. switching characteristics over recommended operating conditions during reset†#|| (see Figure 37) NO. PARAMETER MIN MAX UNIT 2 td(RSTL-ECKI) Delay time, RESET low to ECLKIN synchronized internally 2E* 3P + 20E* ns 3 td(RSTH-ECKI) Delay time, RESET high to ECLKIN synchronized internally 2E* 8P + 20E* ns 4 td(RSTL-ECKO1HZ) Delay time, RESET low to ECLKOUT1 high impedance 2E* ns 5 td(RSTH-ECKO1V) Delay time, RESET high to ECLKOUT1 valid 8P + 20E* ns 6 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z high impedance 2E* 3P + 4E* ns 7 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z valid 16E* 8P + 20E* ns 8 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2E* ns 9 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 8P + 20E* ns 10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2E* ns 11 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 8P + 20E* ns 12 td(RSTL-LOWIV) Delay time, RESET low to low group invalid 0* ns 13 td(RSTH-LOWV) Delay time, RESET high to low group valid 11P* ns 14 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 0* ns 15 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P* 8P* ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. ||EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS /SADS /SRE, AWE /SDWE /SWE , and AOE/SDRAS /SOE , SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3 , HR/W/PCBE2 , HDS2/PCBE1 , PCBE0, GP13/PINTA, GP11/PREQ , HDS1/PSERR , HCS/PPERR , HCNTL1/PDEVSEL , HAS/PPAR, HCNTL0/PSTOP , HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME , UXDATA[7:0], UXSOC, UXCLAV, and URCLAV.
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AWE /SDWE /SWE , and AOE/SDRAS /SOE , SOE3, ASDCKE, and PDT. ¶ Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5. The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. Figure 37. Reset Timing†
*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Figure 38. External/NMI Interrupt Timing
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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HOST-PORT INTERFACE (HPI) TIMING timing requirements for host-port interface cycles†‡ (see Figure 39 through Figure 46) NO. MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 2.4 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 4P¶* ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P* ns 10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns 11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 2 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2.8 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2* ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2.1 ns *This parameter is not production tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. § Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. ¶ Select the parameter value of 4P or 12.5 ns, whichever is greater. switching characteristics over recommended operating conditions during host-port interface cycles†‡ (see Figure 39 through Figure 46) NO. PARAMETER MIN MAX UNIT 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 1.3 4P + 8 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2* ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low −3 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 12* ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only) 4P + 8 ns *This parameter is not production tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.
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† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 41. HPI16 Write Timing (HAS Not Used, Tied High) † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 42. HPI16 Write Timing (HAS Used)
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† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 45. HPI32 Write Timing (HAS Not Used, Tied High) † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 46. HPI32 Write Timing (HAS Used)
*This parameter is not production tested. † For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN. ‡ P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns. § Select the parameter value of 30 ns or 8P, whichever is greater.
0.4 DVDD V MIN
Figure 47. PCLK Timing *This parameter is not production tested. Figure 48. PCI Reset (PRST) Timing
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*This parameter is not production tested. Figure 49. PCI Input/Output Timing
*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Figure 50. PCI Serial EEPROM Interface Timing
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP† (see Figure 51) NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 6.67‡* ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1§* ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 9 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR lowCLKR ext 1.3 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 8 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.9 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 3.1 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 9 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX lowCLKX ext 1.3 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns *This parameter is not production tested. † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing requirements. § This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004 117POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 51) NO. PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 1.4 10 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 6.67§* ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1¶* C + 1¶* ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2.1 3 ns 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int −1.7 3 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 1.7 9 ns 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bitCLKX int −3.9* 4* ns12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX ext −2.1* 9* ns 13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int −3.9 + D1# 4 + D2# ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext −2.1 + D1# 9 + D2# ns 14 td(FXH-DXV) Delay time, FSX high to DX valid FSX int −2.3 5.6 ns14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 1.9 9 ns *This parameter is not production tested. † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. ¶ C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above). # Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P
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Figure 51. McBSP Timing
*This parameter is not production tested. Figure 52. FSR Timing When GSYNC = 1 † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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*This parameter is not production tested. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Figure 57. UXCLK Timing *This parameter is not production tested. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Figure 58. URCLK Timing
*This parameter is not production tested. Figure 59. UTOPIA Slave Transmit Timing†
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*This parameter is not production tested. Figure 60. UTOPIA Slave Receive Timing†
*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Figure 61. Timer Timing
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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. the GPIO register through the CFGBUS. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Figure 62. GPIO Port Timing
*This parameter is not production tested. *This parameter is not production tested. Figure 63. JTAG Test-Port Timing
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0052/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0052/C0049/C0054 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS050A − JANUARY 2004 − REVISED MARCH 2004
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GAD (S-CPGA-P570) CERAMIC PIN GRID ARRAY NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Flip chip application only D. This package is hermetically sealed with a metal lid. thermal resistance characteristics (S-CPGA package) NO °C/W 1 R ΘJA Junction-to-free air (Low K JEDEC PCB) 20.96 2 R ΘJA Junction-to-free air (High K JEDEC PCB) 16.5 3 R ΘJC Junction-to-case (High K JEDEC PCB with heat sink on lid) 10.9 4 R ΘJC Junction-to-case (High K JEDEC PCB with heat sink on body) 7.69
5 R ΘJB Junction-to-board (High K JEDEC PCB) 9
6 R ΘJB Junction-to-board (High K JEDEC PCB with thermal compound on top of the die) 2.93
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-0324501QXA ACTIVE FCPGA GAD 570 1 TBD Call TI Level-NC-NC-NC SM320C6415DGADW60 ACTIVE FCPGA GAD 570 8 TBD Call TI Level-NC-NC-NC SMJ320C6415DGADW60 ACTIVE FCPGA GAD 570 1 TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1
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