5962-0150601HXA

AD13465 AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD13465 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning FUNCTIONAL BLOCK DIAGRAM 100/H9024 OUTPUT TERMINA TORS TIMING 3 ENCENC D9A D10A D11A D0B (LSB) D1B D3BD2B D4B D5B D6B D9B D10B TIMING D11B ENC ENC B–IN D12B D13B (MSB) (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A AD13465 DROUT A 100/H9024 OUTPUT TERMINA TORS AMP-IN-B-2 AMP-IN-B-1AMP-IN-A-2 AMP-IN-A-1 AMP-OUT -A A–IN A+IN B+IN AMP-OUT -B DROUTB DROUT VREF D13A (MSB) D12A D8BD7B VREF DROUT

FEATURES

Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, /H115501% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 85 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs (/H115501 V and /H115500.5 V Ranges) Integral Two-Pole Low-Pass Nyquist Filter Two’s Complement Output Format

3.3 V Compatible Outputs

1.8 W per Channel

Industrial and Military Grade

APPLICATIONS

Optimized for I/Q Baseband Operation Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers PRODUCT DESCRIPTION The AD13465 is a complete dual channel signal processing solution including on-board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13465 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD13465 uses state-of-the-art high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching and impedance control, and provide for significant board area savings. Multiple options are provided for driving the analog input, includ- ing single-ended, differential, and optional series filtering. The AD13465 also offers the user a choice of analog input signal ranges to further minimize additional external signal condition- ing, while remaining general-purpose. The AD13465 operates with ± 5.0 V for the analog signal conditioning, 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent, allow- ing operation with independent Encode and Analog Inputs, while maintaining minimal crosstalk and interference. The AD13465 is packaged in a 68-lead ceramic gull wing package. Manufacturing is done on Analog Devices’ MIL-

38534 Qualified Manufacturers Line (QML) and components

are ava ilable up to Class-H (–40°C to +85°C). The components are manufactured using Analog Devices’ high-speed comple- mentary bipolar process (XFCB). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input signal conditioning included; gain and impedance matching. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance 5. Pin compatible with 12-bit AD13280 product family.

REV. 0–2– AD13465–TARGET SPECIFICATIONS (AVCC = 5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC with Front End Amplifier unless otherwise noted.) Test Mil Sub- AD13465AZ/BZ Parameter Temp Level Group Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY No Missing Codes Full IV 12 Guaranteed Offset Error 25 °C I 1 –2.2 ± 0.2 +2.2 % FS Full VI 2, 3 –2.2 ± 1.0 +2.2 % FS Offset Error Channel Match Full VI 1, 2, 3 –1.0 ± 0.1 +1.0 % FS Gain Error Full VI 2, 3 –5.0 ± 2.0 +5.0 % FS Gain Error Channel Match 25 °C I 1 +1.5 ± 0.5 +1.5 % FS Max VI 2 –3.0 ± 1.0 +3.0 % FS Min VI 3 –5.0 ± 1.0 +5.0 % FS SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 Full V ± 0.5 V AMP-IN-X-2 Full V ± 1.0 V Input Resistance AMP-IN-X-1 Full IV 12 99 100 101 Ω AMP-IN-X-2 Full IV 12 198 200 202 Ω Input Capacitance 2 4.0 7.0 pF Analog Input Bandwidth 3 Full V 100 MHz DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A–IN and B+IN to B–IN 4 Full V ± 1.0 V Input Impedance Full V 618 Ω Analog Input Bandwidth 3 Full V 50 MHz ENCODE INPUT (ENC, ENC) 5 Differential Input Voltage Full IV 12 0.4 V p-p Differential Input Resistance 25 °CV 1 0 k Ω Differential Input Capacitance 25 °C V 2.5 pF SWITCHING PERFORMANCE Maximum Conversion Rate 6 Full VI 4, 5, 6 65 MSPS Minimum Conversion Rate 6 Full IV 12 20 MSPS Aperture Delay (t A)2 5 °C V 1.5 ns Aperture Delay Matching 25 °C IV 12 250 500 ps Aperture Uncertainty (Jitter) 25 °C V 0.3 ps rms ENCODE Pulse with High 25 °C IV 12 5.0 7.7 9.5 ns ENCODE Pulse with Low 25 °C IV 12 5.0 7.7 9.5 ns Output Delay (t OD) Full IV 12 7.5 ns Encode, Rising to Data Ready, Full V 11.5 ns Rising Delay SNR7 Analog Input @ 4.98 MHz 25 °C V 72 dBFS Analog Input @ 9.9 MHz 25 °C I 4 70 72 dBFS Full II 5, 6 69 71 dBFS Analog Input @ 21 MHz 25 °C I 4 69 71 dBFS Full II 5, 6 68 70 dBFS Analog Input @ 32 MHz 25 °C V 70 dBFS Full V 69 dBFS SINAD8 Analog Input @ 4.98 MHz 25 °C V 72 dBFS Analog Input @ 9.9 MHz 25 °C I 4 69 72 dBFS Full II 5, 6 68.5 70.5 dBFS Analog Input @ 21 MHz 25 °C I 4 66.5 70 dBFS Full II 5, 6 66 69 dBFS Analog Input @ 32 MHz 25 °C V 63 dBFS Full V 61 dBFS

REV. 0 –3– AD13465 Test Mil Sub- AD13465AZ/BZ Parameter Temp Level Group Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 4.98 MHz 25 °C V 85 dBFS Analog Input @ 9.9 MHz 25 °C I 4 80 86 dBFS Full II 5, 6 78 84 dBFS Analog Input @ 21 MHz 25 °C I 4 70 76 dBFS Full II 5, 6 69 74 dBFS Analog Input @ 32 MHz 25 °C V 63 dBFS Full V 62 dBFS SINGLE-ENDED ANALOG INPUT Pass Band Ripple to 10 MHz 25 °C V 0.05 dB Pass Band Ripple to 25 MHz 25 °C V 0.1 dB DIFFERENTIAL ANALOG INPUT Pass Band Ripple to 10 MHz 25 °C V 0.3 dB Pass Band Ripple to 25 MHz 25 °C V 0.82 dB TWO-TONE IMD REJECTION 10 fIN = 9.1 MHz and 10.1 MHz 25 °C I 4 77.5 82 dBc f1 and f2 are –7 dB Full II 5, 6 76.5 80 fIN = 19.1 MHz and 20.7 MHz 25 °C V 72 dBc f1 and f2 are –7 dB CHANNEL-TO-CHANNEL ISOLATION 11 25°CI V 1 2 9 0 d B TRANSIENT RESPONSE 25 °C V 15.3 ns DIGITAL OUTPUTS 12 Logic Compatibility CMOS DVCC = 3.3 V Logic 1 Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V Logic 0 Voltage Full I 1, 2, 3 0.2 0.5 V DVCC = 5 V Logic 1 Voltage Full V DVCC – 0.3 V Logic 0 Voltage Full V 0.35 V Output Coding Two’s Complement POWER SUPPLY AVCC Supply Voltage 13 Full VI 4.85 5.0 5.25 V I (AVCC) Current Full V 270 308 mA AVEE Supply Voltage 13 Full VI –5.25 –5.0 –4.75 V I (AVEE) Current Full V 38 49 mA DVCC Supply Voltage 13 Full VI 3.135 3.3 3.465 V I (DVCC) Current Full V 34 46 mA (Total) Supply Current per Channel Full I 1, 2, 3 369 403 mA Power Dissipation (Total) Full I 1, 2, 3 3.57 3.9 W Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/ % VS NOTES 1Gain tests are performed on AMP-IN-X-1 input voltage range. 2Input capacitance spec. combines AD8037 capacitance and ceramic package capacitance. 3Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180 ° out of phase). For single ended input: +IN = 2 V p-p and –IN = GND. 5All AC specifications tested by driving ENCODE and ENCODE differentially. AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 6Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmo nics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. 8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harm onics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 9Analog Input signal power at –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 11Channel-to-channel isolation tested with A Channel grounded and a full-scale signal applied to B Channel. 12Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice.

REV. 0 AD13465 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 ELECTRICAL CC ENVIRONMENTAL2 Storage Temperature Range (Ambient) . . –65 °C to +150°C NOTES

1 Absolute maximum ratings are limiting values applied individually, and beyond

which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for “ES” package: θJC, 2.2°C/W; θJA, 24.3°C/W. TEST LEVEL I 100% Production Tested. II 100% Production Tested at 25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample Tested Only. IV Parameter is guaranteed by design and characteriza- tion testing. V Parameter is a typical value only. VI 100% production tested at temperature at 25 °C: sample tested at temperature extremes. ORDERING GUIDE Model Temperature Range (Case) Package Description Package Option AD13465AZ –25 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C AD13465AF –25 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C with Nonconductive Tie-Bar 5962-0150601HXA –40 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C AD13465/PCB 25 °C Evaluation Board with AD13465AZ

REV. 0 AD13465 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1, 35 SHIELD Internal Ground Shield Between Channels. 2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 4 A–IN Inverting Differential Input (Gain = 1). 5 A+IN Noninverting Differential Input (Gain = 1). 6 AMP-OUT-A Single-Ended Amplifier Output (Gain = 2). 7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ± 0.5 V). 8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ± 1.0 V). 11 AV EEA A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 12 AV CCA A Channel Analog Positive Supply Voltage (Nominally 5.0 V). 14 ENCA Complement of Encode; Differential Input. 15 ENCA Encode Input; Conversion Initiated on Rising Edge. 17 DV CCA A Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). 18–25, 28–33 D0A–D13A Digital Outputs for ADC A. D0 (LSB). 26, 27 DGNDA A Channel Digital Ground. 34 DROUTA Data Ready A Output. 36 DROUTB Data Ready B Output. 37–42, 45–52 D0B–D13B Digital Outputs for ADC B. D0 (LSB). 43, 44 DGNDB B Channel Digital Ground. 53 DV CCB B Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). 54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. 55 ENCB Encode Input; Conversion Initiated on Rising Edge. 56 ENCB Complement of Encode; Differential Input. 58 AV CCB B Channel Analog Positive Supply Voltage (Nominally 5.0 V). 59 AV EEB B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ± 1.0 V). 63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ± 0.5 V). 64 AMP-OUT-B Single-Ended Amplifier Output (Gain = 2). 65 B+IN Noninverting Differential Input (Gain = 1). 66 B–IN Inverting Differential Input (Gain = 1). PIN CONFIGURATION 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18765 6 8 6 7 6 6 6 5 6 4 6 3 6 24321 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD13465 AGNDB AGNDB D12A DROUTB AGNDA D0A(LSB) D3A D4A D5A D6A D7A AGNDB ENCB ENCB D0B(LSB) AGNDA AGNDA AMP-OUT-A A+IN A–IN AGNDA AMP-IN-A-2 AMP-IN-A-1 AGNDB SHIELD D3B D4B D5B DGNDA D13B(MSB) D12B D11B DGNDB AGNDB B–IN B+IN AGNDB AMP-IN-B-2 AMP-OUT-B AMP-IN-B-1 D10B D9B D8B D7B D6B DGNDB SHIELD DROUTA D13A(MSB) D10A D11A D9A D8A DGNDA ENCA ENCA AGNDA AGNDA D1B D2B D1A D2A AVEEA AVCCA DVCCA AVEEB AVCCB DVCCB

REV. 0 AD13465 –6– –Typical Performance Characteristics –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 5MHz(–1dBFS) SNR = 72.12dBFS SFDR = 86.05dBc dB TPC 1. Single Tone @ 5 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 21MHz(–1dBFS) SNR = 71.74dBFS SFDR = 73.07dBc dB TPC 2. Single Tone @ 21 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 9.1MHz AND 10.1MHz(–1dBFS) SFDR = 85.01dBc dB TPC 3. Two-Tone @ 9.1 MHz/10.1 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 9.9MHz(–1dBFS) SNR = 72.09dBFS SFDR = 84.04dBc dB TPC 4. Single Tone @ 9.9 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 32MHz(–1dBFS) SNR = 70.8dBFS SFDR = 62.57dBc dB TPC 5. Single Tone @ 32 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 65MSPS AIN = 19MHz AND 20.7MHz(–1dBFS) SNR = 70.8dBFS SFDR = 75.40dBc dB TPC 6. Two-Tone @ 19 MHz/20.7 MHz

REV. 0 AD13465 –7– 3.0 2.5 2.0 1.5 1.0 0.5 –0.5 –1.0 0 14336 12288 10240819261444096 2048 ENCODE = 65MSPS DNL MAX = 0.632 CODES DNL MIN = –0.52 CODES 16384 LSB TPC 7. Differential Nonlinearity –10 FREQUENCY – MHz dBFS ENCODE = 65MSPS ROLLOFF = –0.18dB TPC 8. Passband Ripple to 25 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 40MSPS AIN = 9.1MHz AND 10.1MHz(–1dBFS) SFDR = 84.16dBc dB TPC 9. Two-Tone @ 9.1 MHz/10.1 MHz 3.0 2.0 1.0 –1.0 –2.0 –3.0 0 14336 12288 10240819261444096 2048 ENCODE = 65MSPS INL MAX = 1.18 CODES INL MIN = –1.06 CODES 16384 LSB TPC 10. Integral Nonlinearity –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 40MSPS AIN = 5MHz(–1dBFS) SNR = 72dBFS SFDR = 87.57dBc dB TPC 11. Single Tone @ 5 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY – MHz ENCODE = 40MSPS AIN = 18MHz(–1dBFS) SNR = 71.5dBFS SFDR = 78.7dBc dB TPC 12. Single Tone @ 18 MHz

The sample-to-sample variation in aperture delay. between both peak measurements. The deviation of any code from an ideal 1 LSB step. specs define an acceptable encode duty cycle. determined by a least square curve fit. frequency drops by no more than 3 dB below the guaranteed limit. The encode rate at which parametric testing is performed. percentage of full scale is reduced to midscale. (always related back to converter full scale). related back to converter full scale). nent may or may not be a harmonic. of the worst third order intermodulation product; reported in dBc. Figure 1. Timing Diagram

Figure 2. Single-Ended Input Stage Figure 3. ENCODE Inputs Figure 4. Digital Output Stage Figure 5. Digital Output Stage

2 V p-p, and input impedance configurations of 50 Ω, 100 Ω,

to fully integrate a complete 14-bit analog-to-digital converter. AD6644 maximizing the performance of the device. midsupply level for the ADC. word, coded as two’s complement. input impedance. The standard inputs are ± 0.5 V and ± 1.0 V. available at each input location. AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open. AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND. AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open.

have radiated components that may be received by the AD13465. the package as possible, using 0.1 µF chip capacitors. The AD13465 has separate digital and analog power supply pins. can couple switching current back into the analog supplies. put timing is guaranteed with 10 pF loads. Figure 9. Evaluation Board Mechanical Layout Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. the need to externally isolate the device from the receiving gate. clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required.

REV. 0 AD13465 –12– Bill of Materials List for Evaluation Board Qty Component Name Ref/Des Value Description Manufacturing Part No. 2 74CLX16373MTD U7, U8 Latch 74LCX1673MTD (Fairchild)

1 AD13465AZ U1 AD13465AZ AD13465AZ

2 ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7

10 BJACK BJ1-BJ10 Banana Jacks 108-0740-001 (Johnson Components)

2 BRES0805 R41, R53 25 Ω 0805 SM Resistor EFJ-6GEYJ240V

4 BRES0805 R38, R39, R55, R56 33 k Ω 0805 SM Resistor EFJ-6GEYJ333V

6 RES2 R1, R2, R5, R7, R8 50 Ω 0805 SM Resistor EFJ-6GEYJ333V

36 RES2 R3, R4, R6, R9 100 Ω 0805 SM Resistor EFJ-6GEYJ333V

R12–R15, R19–R28, R31–R36, R37, R42–R46, R51, R52 28 CAP2 C1, C2, C5 –C10, 0.1 µF 0805 SM Resistor GRM 40X7R104K025BL C12, C16–C18 C20–C26, C28 C30–C38 2 CAP2 C13, C27 0.47 µF 0805 SM Resistor VJ1206U474MFXMB

2 H40DM J1, J2 2 × 20 40-Pin Male Connector TSW -120-08-G-D

6 IND2 L1 –L6 47 Ω SM Inductor 2743019447

4 MC10EL16 U2, U3, U9, U11 Clock Drivers MC1016EP16D

2 MC100ELT23 U4, U10 ECL/TTL Clock Drivers SY100ELT23L

8 POLCAP2 C3, C4, C11, C14, 10 µF Tantalum Polar Caps T491C106M016A57280

C15, C19, C29, C30

4 RES2 R47 –R50 0 Ω 0805 SM Resistor ERJ-6GEY OR 00V

12 SMA J3 –J14 SMA Connectors 142-0701-201

4 Stand-Off Stand-Off 313-2477-016 ( Johnson Components)

4 Screws Screws (Stand-Off) MPMS 004 0005 PH (Building Fasteners)

1 PCB AD13465 Eval Board (Rev B) GS03361

REV. 0 AD13465 –13– AGNDA AGNDA –5VAA +5VAA D2A D3A D4A D5A D6A D7A DGNDA AGNDB AGNDB ENCBB ENCB +3.3VDB D13B(MSB) D9B D8B D7B D6B DGNDB AGNDA AMP IN A 2 A+IN A–IN AGNDA SHIELD AGNDB AGNDB D12A D13A(MSBA) SHIELD DRBOUT D3B D4B D5B DGNDB AD13465 D3A D4A D5A D6A D7A D2A DGNDA AGNDA AGNDA ENCAB D0A(LSB) D1A ENCA AGNDA +3VDA D0A D1A AGNDA ENCA ENCA –5VAA 0.1/H9262F C10 0.1/H9262F C36 0.1/H9262F OUT 3.3VDA C34 0.1/H9262F +5VAA AGNDA AGNDA C35 0.1/H9262F AGNDA AMP IN A 1 AMP OUT A AGNDA AGNDB B–IN B+IN AMP OUT B AMP IN B 1 AMP IN B 2 –5.2VAB +5VAB DGNDA AGNDB D10B D11B D12B D0B(LSBB) DRAOUT D11A D10A D9A D8A DGNDA D12A D13A DRBOUT D3B D4B D5B DGNDB D0B DRAOUT D11A D10A D9A D8A DGNDA E56 E55 LIDB E65 E48 E40DGNDA DGNDB E69 E70 E49 AGNDA E51 E50 E72 E74 E77 E75 E73 E71 SMA AGNDA SMA E76 E78 E83 E81 E79AGNDA SMA AGNDA J13 SMA AGNDA E68 E66 AGNDB E54 E53 J7 SMA AGNDB E86E85 E52 AGNDB AGNDB J14 SMA AGNDB SMA AGNDB SMA DGNDB –5VAB C33 0.1/H9262F C18 0.1/H9262F C37 0.1/H9262F OUT 3.3VDB C17 0.1/H9262F +5VAB AGNDB AGNDB C38 0.1/H9262F AGNDB AGNDB ENCB ENCB D13B D9B D8B D7B D6B DGNDB AGNDB D10B D11B D12B E67 LIDA E80 E82 E84 L1C29 10/H9262F +3VDA C62 0.1/H9262F 47/H9024 /H1155020% @100MHz DGNDA DUT 3.3VDA BJ10 L2C30 10/H9262F +3VDB C16 0.1/H9262F 47/H9024 /H1155020% @100MHz DGNDB DUT 3.3VDB BJ9 10/H9262F +3VAA C20 0.1/H9262F 47/H9024 /H1155020% @100MHz AGNDA +5VAA BJ6 AGNDA L4C4 10/H9262F +5VAB C21 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDB +5VAB BJ5 AGNDB L5C11 10/H9262F –5VAA C32 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDA –5VAA BJ2 AGNDA L6C19 10/H9262F –5VAB C31 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDB –5VAB BJ1 AGNDB D1BD1B D2BD2B Figure 10a. Evaluation Board

REV. 0 AD13465 –14– (MSB) B13B B12B B11B B10B B9B B8B F1B DGNDB (LSB) B0B B1B B2B B3B DGNDB B7B B6B C14 10/H9262F BUFLA TB 50/H9024E64 E63 E62 DRAOUT 3.3VDB DGNDB H40DN F0B R11, DNI25 113 112 VCC 111 110 GND GND GND VCC LE2 115 114 GND O13 O12 VCC O11 O10 GND GND GND VCC OE2 O15 O14 GND DUT 3.3VDB DGNDB DGNDB DGNDB DUT 3.3VDB DGNDB DGNDB R10, DNI R30, DNI R29, DNI R28, 100/H9024 R27, 100/H9024 R26, 100/H9024 R12, 100/H9024 R9, 100/H9024 R35, 100/H9024 R34, 100/H9024 R33, 100/H9024 R32, 100/H9024 R31, 100/H9024 R25, 100/H9024 LE1 OE1 DUT 3.3VDB DGNDB DGNDB DGNDB DUT 3.3VDB DGNDB R49 0/H9024 R50 0/H9024 DGNDB 50/H9024 LA TCHB E57 (LSB) D0B D1B D4B D5B D6B D7B D8B D9B D10B D11B D12B (MSB) D13B F0B F1B B0B (LSB) B1B B2B B3B B4B B5B B6B B7B B8B B9B B10B B13B (MSB) B11B B12B DGNDB 74LCX16374 R36, 100/H9024 (MSB) B13A B12A B11A B10A B9A B8A F1A DGNDA (LSB) B0A B1A B2A B3A DGNDA B7A B6A C15 10/H9262F BUFLA T A 50/H9024E61 E60 E59DRAOUT 3.3VDA DGNDA H40DM F0A R18, DNI25 113 112 VCC 111 110 GND GND GND VCC LE2 115 114 GND O13 O12 VCC O11 O10 GND GND GND VCC OE2 O15 O14 GND DUT 3.3VDA DGNDA DGNDA DGNDA DUT 3.3VDA DGNDA DGNDA R17, DNI R40, DNI R44, DNI R45, 100/H9024 R46, 100/H9024 R15, 100/H9024 R14, 100/H9024 R13, 100/H9024 R24, 100/H9024 R23, 100/H9024 R22, 100/H9024 R21, 100/H9024 R20, 100/H9024 R19, 100/H9024 R12, 100/H9024 LE1 OE1 DUT 3.3VDA DGNDA DGNDA DGNDA DUT 3.3VDA DGNDA R47 0/H9024 R48 0/H9024 DGNDA 50/H9024 LA TCHA E58 (LSB) D0A D1A D4A D5A D6A D7A D8A D9A D10A D11A D12A (MSB) D13A DGNDA 74LCX16374 D2A D3A B4A B5A D2B D3B B4B B5B F0A F1A B0A (LSB) B1A B2A B3A B4A B5A B6A B7A B8A B9A B10A B13A (MSB) B11A B12A Figure 10b. Evaluation Board

REV. 0 AD13465 –15– NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 AGNDA OUT NR IN SD 1ERR GND ADP3330 AGNDA DB QB C13 0.47/H9262F 3.3VA C7 0.1/H9262F 0.1/H9262F ENCA ENCA AGNDA R42 100/H9024 R43 100/H9024 AGNDAR56 33k/H9024 NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 DB QB NC = NO CONNECT VCC VEE NC D VBB MC100EPT23 DB Q1 3.3VDA 0.47/H9262F R55 33k/H9024 DGNDA 0.1/H9262F R41 25/H9024 J12 SMA ENCODE SMA 50/H9024 0.1/H9262F AGNDA AGNDA AGNDA DGNDA DGNDA AGNDA 100/H9024 100/H9024 DGNDA DGNDC5 0.47/H9262F +3.3VDA LA TCHA BUFLA T A E23 E19 +5VAA E17 E27 E25 E21 E32 E44 E42 E10 E33 E18 E28 E26 E20 E31 E43 E41 E34 DGNDA AGNDA E38 E29 E36 E14 E37 E30 E35 E13 DGNDB AGNDB SO1 SO2 SO3 SO4 SO5 SO6 E45 E46 E15 E16 E12 DGNDA DGNDB E11 E39 E47 DGNDA DGNDB AGNDB1 BJ3 AGNDA1 BJ4 DGNDB BJ7 DGNDB DGNDA BJ8 DGNDA NC = NO CONNECT VCC Q VEE NC D VBB U11 MC10EL16 AGNDB OUT NR IN SD 1ERR GND ADP3330 AGNDB DB QB C27 0.47/H9262F 3.3VB C24 0.1/H9262F C28 0.1/H9262F ENCB ENCB AGNDB R52 100/H9024 R51 100/H9024 AGNDA R38 33k/H9024 NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 DB QB NC = NO CONNECT VCC VEE NC D VBB U10 MC100EPT23 DB Q1 3.3VDB C25 0.47/H9262F R39 33k/H9024 DGNDB C23 0.1/H9262F R53 25/H9024 J11 SMA J10 ENCODE SMA R54 50/H9024 C22 0.1/H9262F AGNDB AGNDB AGNDB DGNDB DGNDB DGNDB R37 100/H9024 100/H9024 DGNDB DGNDBC26 0.1/H9262F 3.3VDA LA TCHB BUFLA TB E24 E22 +5VAB Figure 10c. Evaluation Board

REV. 0 AD13465 –19– 68-Lead Ceramic Leaded Chip Carrier (ES-68C) TOE DOWN ANGLE 0–8 DEGREES 0.010 (0.254) 30/H11543 0.050 (1.27) 0.020 (0.508) DETAIL A ROTATED 90/H11543 CCW 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) PIN 1 10 26 TOP VIEW (PINS DOWN) 0.800 (20.32) BSC 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) MAX 0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 1.070 (27.18) MIN OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

REV. 0–20– C01973–2.5–4/01(0) PRINTED IN U.S.A. AD13465 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar (ES-68C) DETAIL A 0.010 (0.254) 30/H11543 0.050 (1.27) 0.020 (0.508) 0.175 (4.45) MAX0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) PIN 1 TOP VIEW (PINS DOWN) 0.800 (20.32) BSC 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) /H11547 45/H11543 0.015 (0.3) /H11547 45/H11543

3 PLS

0.040 (1.02) R TYP 0.350 (8.89) TYP 2.000 (8.89) TYP