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SM320VC33 TI | Alldatasheet

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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 /C0068High-Performance Floating-Point Digital Signal Processor (DSP): - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS) - 75 Million Instructions Per Second (MIPS) /C006834K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal Performance /C0068x5 Phase-Locked Loop (PLL) Clock Generator /C0068Very Low Power: < 200 mW @ 150 MFLOPS /C006832-Bit High-Performance CPU /C006816-/32-Bit Integer and 32-/40-Bit Floating-Point Operations /C0068Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices /C0068Boot-Program Loader /C0068EDGEMODE Selectable External Interrupts /C006832-Bit Instruction Word, 24-Bit Addresses /C0068Eight Extended-Precision Registers /C0068Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImeline Technology by Texas Instruments (TI) /C0068On-Chip Memory-Mapped Peripherals: - One Serial Port - Two 32-Bit Timers - Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation /C0068164-Pin Low-Profile Quad Flatpack (HFG Suffix) /C0068144-Pin Non-hermetic Ceramic Ball Grid Array (CBGA) (GNM Suffix) /C0068Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) /C0068Two Low-Power Modes /C0068Two- and Three-Operand Instructions /C0068Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle /C0068Block-Repeat Capability /C0068Zero-Overhead Loops With Single-Cycle Branches /C0068Conditional Calls and Returns /C0068Interlocked Instructions for Multiprocessing Support /C0068Bus-Control Registers Configure Strobe-Control Wait-State Generation /C00681.8-V (Core) and 3.3-V (I/O) Supply Voltages

description

The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18- µm four-level-metal CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3x generation of DSPs from Texas Instruments. The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.Please be aware that an important notice concerning availability, standard warrant y, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TImeline and SM320C3x are trademarks of Texas Instruments. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL−PRF−38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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machine-cycle time. High performance and ease of use are the results of these features. The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. tests to be performed through that JTAG domain. Table 1. Boundary-Scan Instruction Code † Use of Private opcodes could cause the device to operate in an unexpected manner.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 pinout 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 135 136 30 94 127 128 129 130 131 132 133 134 125 126 40 84 NC NC NC NC NC NC NC NC - No internal connection 83 124 NC NC NC NC A20 VSS A19 A18 A17 DVDD A16 A15 V SS A14 A13 CV DD A12 A11 DVDD A10 VSS DV DD VSS CV DD DVDD PAGE3 PAGE2 VSS PAGE1 PAGE0 NC NC NC NC NC DVDD CLKR FSR0 VSS DR0 TRST TMS CV DD TDI TDO TCK V SS EMU0 EMU1 DV DD V SS DVDD CV DD V SS D10 D11 DVDD D12 D13 D14 D15 NC NC HFG PACKAGE†‡ (TOP VIEW) STRB R/W IACK RDY HOLD HOLDA D25 D24 D23 D22 D21 D20 D19 D17 D27 D30 D16 DDDV DDDV DDDV DDDV DDDV DDCV DDCV D31 SSV SSV SSV SSV D29 D26 D18 SSV D28 NC NC MCBL/MP RESET A22 RSV0 RSV1 CLKMD0 CLKMD1 XIN XOUT EXTCLK EDGEMODE INT0 INT1 INT2 INT3 XF1 TCLK0 TCLK1 DX CLKX0 XF0 FSX SHZ A23 A21 DDDV DDPLLV DDDV DDCV DDCV SSV SSPLLV SSV DDDV SSV SSV † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CV DD and VSS, respectively. The SM/SMJ320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG Suffix) and in 144-ball fine pitch ball grid arrays (GNL and GNM Suffix).

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

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GNM Terminal Assignments† (Sorted by Signal Name) SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER A0 J2 D0 G12 M1 R/W L4 A1 K2 D1 G10 N1 RDY M5 A2 K1 D2 F13 N4 RESET B7 A3 J4 D3 G11 N7 RSV0 B4 A4 H4 D4 H10 M8 RSV1 D5 A5 H3 D5 H13 N12 SHZ D7 A6 H1 D6 H12 DVDD L13 STRB M4 A7 G4 D7 J10 DVDD H11 TCK F10 A8 G1 D8 J11 F11 TCLK0 C10 A9 G2 D9 J12 B12 TCLK1 A11 A10 F3 D10 K13 A10 TDI E11 A11 F4 D11 K12 A6 TDO D13 A12 F2 D12 K10 A1 TMS E10 A13 E1 D13 M13 DX0 A12 TRST C13 A14 E2 D14 L11 EDGEMODE A7 B1 A15 E4 D15 L12 EMU0 F12 D1 A16 C1 D16 M12 EMU1 E12 G3 A17 C2 D17 L10 EXTCLK C6 J1 A18 D3 D18 K9 FSR0 C12 L2 A19 C3 D19 N11 FSX D10 M3 A20 B2 D20 M11 H1 L3 M6 A21 D4 D21 M10 H3 N2 L7 A22 A2 D22 K8 HOLD N5 V N10 A23 B3 D23 N9 HOLDA K5 VSS N13 CLKMD0 C5 D24 M9 IACK K4 K11 CLKMD1 B5 D25 L8 INT0 C8 G13 CLKR0 B13 D26 N8 INT1 B9 E13 CLKX0 B11 D27 M7 INT2 D8 A13 E3 D28 K7 INT3 A9 C11 J3 D29 L6 MCBL/MP B8 C9 L5 D30 N6 PAGE0 M2 C7 CV L9 D31 K6 PAGE1 N3 C4 CVDD J13 DR0 D11 PAGE2 L1 XF0 B10 D12 D2 PAGE3 K3 XF1 D9 A8 DVDD F1 PLLVDD‡ A5 XIN B6 DVDD H2 PLLVSS‡ A4 XOUT D6 † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CV DD and VSS, respectively.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 GNM Terminal Assignments† (Sorted by Pin Number) PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME A1 DVDD C11 VSS G10 D1 L4 R/W A2 A22 C12 FSR0 G11 D3 L5 CVDD A3 CVDD C13 TRST G12 D0 L6 D29 A4 PLLVSS D1 VSS G13 VSS L7 VSS A5 PLLVDD D2 DVDD H1 A6 L8 D25 A6 DVDD D3 A18 H2 DVDD L9 CVDD A7 EDGEMODE D4 A21 H3 A5 L10 D17 A8 CVDD D5 RSV1 H4 A4 L11 D14 A9 INT3 D6 XOUT H10 D4 L12 D15 A10 DVDD D7 SHZ H11 DVDD L13 DVDD A11 TCLK1 D8 INT2 H12 D6 M1 DVDD A12 DX D9 XF1 H13 D5 M2 PAGE0 A13 VSS D10 FSX J1 VSS M3 VSS B1 VSS D11 DR0 J2 A0 M4 STRB B2 A20 D12 CVDD J3 CVDD M5 RDY B3 A23 D13 TDO J4 A3 M6 VSS B4 RSV0 E1 A13 J10 D7 M7 D27 B5 CLKMD1 E2 A14 J11 D8 M8 DVDD B6 XIN E3 CVDD J12 D9 M9 D24 B7 RESET E4 A15 J13 CVDD M10 D21 B8 MCBL/MP E10 TMS K1 A2 M11 D20 B9 INT1 E11 TDI K2 A1 M12 D16 B10 XF0 E12 EMU1 K3 PAGE3 M13 D13 B11 CLKX0 E13 VSS K4 IACK N1 DVDD B12 DVDD F1 DVDD K5 HOLDA N2 H3 B13 CLKR F2 A12 K6 D31 N3 PAGE1 C1 A16 F3 A10 K7 D28 N4 DVDD C2 A17 F4 A11 K8 D22 N5 HOLD C3 A19 F10 TCK K9 D18 N6 D30 C4 VSS F11 DVDD K10 D12 N7 DVDD C5 CLKMD0 F12 EMU0 K11 VSS N8 D26 C6 EXTCLK F13 D2 K12 D11 N9 D23 C7 VSS G1 A8 K13 D10 N10 VSS C8 INT0 G2 A9 L1 PAGE2 N11 D19 C9 VSS G3 VSS L2 VSS N12 DVDD C10 TCLK0 G4 A7 L3 H1 N13 VSS † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CV DD and VSS, respectively.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

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TYPE† DESCRIPTION CONDITIONS WHEN NAME QTY TYPE† DESCRIPTION WHEN SIGNAL IS Z TYPE‡ PRIMARY-BUS INTERFACE D31 D0 32 I/O/Z 32-bit data port S H R D31- D0 32 I/O/Z Data port bus keepers. (See Figure 9) S A23- A0 24 O/Z 24-bit address port S H R R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is performed over the parallel interface. S H R STRB 1 O/Z Strobe. For all external-accesses S H PAGE0 - PAGE3 1 O/Z Page strobes. Four decoded page strobes for external access S H R RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction completion. HOLD 1 I Hold. When HOLD is a logic low, any ongoing transaction is completed. A23- A0, D31-D0, STRB , and R/W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set. HOLDA 1 O/Z Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD . HOLDA indicates that A23-A0, D31-D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set. S CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vec- tor. EDGEMODE 1 I Edge mode. Enables interrupt edge mode detection. INT3- INT0 4 I External interrupts IACK 1 O/Z Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate when a section of code is being executed. S MCBL/MP 1 I Microcomputer Bootloader/microprocessor mode-select SHZ 1 I Shutdown high impedance. When active, SHZ places all pins in the high-impedance state. SHZ can be used for board-level testing or to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instruction. S R SERIAL PORT 0 SIGNALS CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.S R CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive process using DR0. S R FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit process using DX0. S R † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION CONDITIONS WHEN NAME QTY TYPE† DESCRIPTION WHEN SIGNAL IS Z TYPE‡ TIMER SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R SUPPLY AND OSCILLATOR SIGNALS H1 1 O/Z External H1 clock S H3 1 O/Z External H3 clock S CVDD 8 I +VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to a common supply plane.§ DVDD 16 I +VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a common supply plane.§ VSS 18 I Ground. All grounds must be connected to a common ground plane. PLLVDD 1 I Internally isolated PLL supply. Connect to CVDD (1.8 V) PLLVSS 1 I Internally isolated PLL ground. Connect to VSS EXTCLK 1 I External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is used, tie this pin to ground. XOUT 1 O Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT should be left unconnected. XIN 1 I Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to ground. CLKMD0, CLKMD1

2 I Clock mode select pins

RSV0 - RSV1 2 I Reserved. Use individual pullups to DVDD. JTAG EMULATION EMU1- EMU0 2 I/O Emulation pins 0 and 1, use individual pullups to DV DD TDI 1 I Test data input TDO 1 O Test data output TCK 1 I Test clock TMS 1 I Test mode select TRST 1 I Test reset † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

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ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Boot Loader Cache (64 × 32) RAM Block 0 (1K × 32) RAM Block 1 (1K × 32) RDY HOLD HOLDA STRB R/W D31- D0 A23- A0 RESET CPU1 REG1 REG2 MUX BKARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R7-R0) Auxiliary Registers (AR0- AR7) Other Registers (12) Multiplier 32-Bit Barrel Shifter ALU DMA Controller Global-Control Register Source-Address Register Destination- Address Register Serial Port 0 Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 Port Control STRB-Control Register Transfer- Counter Register PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 32 32 24 24 32 INT(3- 0) IACK MCBL/MP XF(1,0) 32 24 24 24 2432 32 32 CPU2 32 32 40 40 Peripheral Data Bus CPU1 REG1 REG2 RAM Block 2 (16K × 32) 24 32 RAM Block 3 (16K × 32) 24 32 MUX Peripheral Address Bus XOUT XIN PAGE0 PAGE1 PAGE2 PAGE3 Peripheral Data Bus TDI TDO TCK EMU0 EMU1 TMS TRST MUX EDGEMODE ControllerPLL CLK JTAG Emulation IR PCRSV(0,1) SHZ CLKMD(0,1) EXTCLK

63 Words

Figure 1. SM/SMJ320VC33 Memory Maps

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Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

NOTE A: Shading denotes reserved address locations. Figure 3. Peripheral Bus Memory-Mapped Registers synchronized, locks onto and tracks an input clock signal.

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control clock divide ratios, oscillator, and PLL power (see Table 2). is left unconnected and XIN is grounded. is a simple x5 reference multiplier with bypass and power control. clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state. relative to the present H1/H3 state. Figure 4. Clock Generation Table 2. Clock Mode Select Pins

signal, resulting in a XIN signal that is 75-85% of the oscillator supply voltage. internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals. NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5. Table 3. Typical Crystal Circuit Loading † CL and RL are typical internal series load capacitance and resistance of the crystal. Figure 5. Self-Oscillation Mode

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Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CVDD and VSS Figure 6. PLL Isolation Circuit Diagram the device will synchronously terminate any external activity. for the PLL to output to clear this counter. The setup and behavior that is seen is as follows. output cycles. The PLL/CPU clock then switches to x5 mode. cleared and subsequent resets will not exhibit this condition. up first, DVDD will follow by one diode drop even when the DVDD supply is not active. becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.

logic-low and logic-high states is sufficient. (ISR), effectively lengthening the maximum ISR width. Figure 7. EDGEMODE and Interrupt Flag CIrcuit an inactive or high-impedance state. controlled by a single bus control register. Table 4. PAGE0 - PAGE3 Ranges

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to Figure 8 for the following examples. the tied back address is high, the bus will be controlled by the internal wait-state counter. to affect the feedback path. no faster than the WTCNT counter and will be extended as long as READY is held high. Figure 8. Internal Ready Logic, Simplified Diagram

Table 5. MUX Select (Bus Control Register Bits 4 and 3) External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes. since the bus acts like it has a one-level-deep write FIFO. driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low. Figure 9. Bus Keeper Circuit

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pin low, which the boot-load software then detects, causing a particular routine to be executed (see Table 6). Table 6. INT0 - INT3 Sources locations. The simplest solution is to begin a program stack or uninitialized data section at 0x809800. Guide (literature number SPRU031). A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete. internal RAM, no special provisions are needed. Figure 10. Changing Bootload Select Pin

JTAG/MPSD Emulation Technical Reference (literature number SPDU079). describes the emulation signals. schematics and wiring diagrams in this document. Figure 11. 14-Pin Header Signals and Header Dimensions Table 7. 14-Pin Header Signal Descriptions TCK Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod. ‡ Use 1-50K pullups for TMS, EMU0 and EMU1.

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default, these signals are not terminated. can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used. /C0068Signals TMS and TDI are series-terminated to reduce signal reflections. /C0068A 10.368-MHz test clock source is provided. Another test clock can be used for greater flexibility.

10.368 MHz

Figure 12. JTAG Emulator Cable Pod Interface

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP family devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX, TMP , or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SM/SMJ Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability of the device has been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, HFG, GNM, or GNL) and temperature range (for example, M). Figure 13 provides a legend for reading the complete device name for any TMS320 DSP family member. TMS320 is a trademark of Texas Instruments.

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Figure 13. TMS320 DSP Device Nomenclature

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 absolute maximum ratings over specified temperature range (unless otherwise noted) † † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. § Absolute dc input level should not exceed the DV DD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA, and < 1 V amplitude is permissable. ¶ Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the SM/SMJ320VC33, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (I CC) current specification in the electrical characteristics table and also read TMS320C3x General-Purpose Applications (literature number SPRU194). recommended operating conditions‡#|| MIN NOM MAX UNIT CVDD Supply voltage for the core CPU/C0107 1.71 1.8 1.89 V DVDD Supply voltage for the I/O pins/C0104 3.14 3.3 3.46 V VSS Supply ground 0 V VIH High-level input voltage 0.7 x DVDD DVDD + 0.3§ V VIL Low-level input voltage -0.3 § 0.3 x DVDD V IOH High-level output current 4 mA IOL Low-level output current 4 mA TC Operating case temperature -55 125 °C CL Capacitive load per output pin 30 pF ‡ All voltage values are with respect to VSS. § Absolute dc input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA, and < 1 V amplitude is permissable. # All inputs and I/O pins are configured as inputs. || All input and I/O pins use a Schmidt hysteresis inputs except SHZ and D0-D31. Hysteresis is approximately 10% of DV DD and is centered at 0.5 x DVDD. /C0107CVDD should not exceed DVDD by more than 0.7 V. (Use a Schottky clamp diode between these supplies.) /C0104DVDD should not exceed CVDD by more than 2.5 V.

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† All voltage values are with respect to VSS. ‡ For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions tabl e. § For VC33, all typical values are at DVDD = 3.3, CVDD = 1.8 V, TC (case temperature) = 25°C. ¶ Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST . # Pins D0-D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 9). maximum rate possible. See TMS320C3x General-Purpose Applications (literature number SPRU194). /C0107fx is the PLL output clock frequency. Where: I OL = 4 mA (all outputs) for dc levels test. Figure 14. Test Load Circuit

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 25POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows, unless otherwise noted: Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High Impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) x unknown, changing, or don’t care level Additional symbols and their meaning A Address lines (A23- A0) H H1 and H3 ASYNCH Asynchronous reset signals (XF0, XF1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, TCLK0, and TCLK1) HOLD HOLD CLKX CLKX0 HOLDA HOLDA CLKR CLKR0 IACK IACK CONTROL Control signals INT INT3 - INT0 D Data lines (D31- D0) PAGE PAGE0 - PAGE3 DR DR RDY RDY DX DX RW R/W EXTCLK EXTCLK RW R/W FS FSX/R RESET RESET FSX FSX0 S STRB FSR FSR0 SCK CLKX/R GPI General-purpose input SHZ SHZ GPIO General-purpose input/output; peripheral pin (CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0, and TCLK1) TCLK TCLK0, TCLK1, or TCLKx GPO General-purpose output XF XF0, XF1, or XFx H1 H1 XF0 XF0 H3 H3 XF1 XF1 XIN XIN

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

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phase-locked loop (PLL) circuit timing phase-locked loop characteristics using EXTCLK or on-chip crystal oscillator† PARAMETER MIN MAX UNIT Fpllin Frequency range, PLL input 5* 15* MHz Fpllout Frequency range, PLL output 25* 75* MHz Ipll PLL current, CVDD supply 2* mA Ppll PLL power, CVDD supply 5* mW PLLdc PLL output duty cycle at H1 45* 55* % PLLJ PLL output jitter, Fpllout = 25 MHz 400* ps PLLLOCK PLL lock time in input cycles 1000 cycles * Not production tested † Duty cycle is defined as 100*t1/(t1+t2)% To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation.

The following table defines the timing parameters for the clock circuit signals. † This circuit is intended for series resonant fundamental mode operation. ‡ Signal amplitude is dependent on the crystal and load used. NOTE A: See Table 3 for value of Rd. Figure 15. On-Chip Oscillator Circuit

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

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clock circuit timing (continued) The following tables define the timing requirements and switching characteristics for EXTCLK. timing requirements for EXTCLK, all modes (see Figure 16 and Figure 17) MIN MAX UNIT t Rise time EXTCLK F = Fmax, x0.5 and x1 modes 1* nstr(EXTCLK) Rise time, EXTCLK F < Fmax 4* ns t Fall time EXTCLK F = Fmax, x0.5 and x1 modes 1* nstf(EXTCLK) Fall time, EXTCLK F < Fmax 4* ns x5 mode 21* tw(EXTCLKL) Pulse duration, EXTCLK low x1 mode 6* nstw(EXTCLKL) Pulse duration, EXTCLK low x0.5 mode 4* ns x5 mode 21* tw(EXTCLKH) Pulse duration, EXTCLK high x1 mode 5* nstw(EXTCLKH) Pulse duration, EXTCLK high x0.5 mode 4* ns x5 PLL mode 40* 60* tdc(EXTCLK) Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)] x1 and x0.5 modes, F = max 45 55 %tdc(EXTCLK) Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)] x1 and x0.5 modes, F = 0 Hz 0* 100* x5 mode 66.7* 200* tc(EXTCLK) Cycle time, EXTCLK x1 mode 13.3 nstc(EXTCLK) Cycle time, EXTCLK x0.5 mode 10* ns x5 mode 5* 15* Fext Frequency range, 1/tc(EXTCLK) x1 mode 0 75 MHzFext Frequency range, 1/tc(EXTCLK) x0.5 mode 0* 100* MHz * Not production tested switching characteristics for EXTCLK over recommended operating conditions, all modes (see Figure 16 and Figure 17) PARAMETER MIN TYP MAX UNIT Vmid Mid-level, used to measure duty cycle 0.5 x DVDD V t Delay time, EXTCLK to H1 and x1 mode 2* 4.5 7* nstd(EXTCLK-H) Delay time, EXTCLK to H1 and H3 x0.5 mode 2* 4.5 7* ns tr(H) Rise time, H1 and H3 3* ns tf(H) Fall time, H1 and H3 3* ns td(HL-HH) Delay time, from H1 low to H3 high or from H3 low to H1 high -1.5* 2* ns x5 PLL mode 1/(5 x fext) tc(H) Cycle time, H1 and H3 x1 mode 1/fext nstc(H) Cycle time, H1 and H3 x0.5 mode 2/fext ns * Not production tested

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The following tables define memory read/write timing parameters for STRB. † These timings assume a similar loading of 30 pF on all pins. ‡ P = tc(H)/2 (when duty cycle equals 50%). † These timings assume a similar loading of 30 pF on all pins. Output load characteristics for high-speed and low-speed (low-noise) output buffers are shown in Figure 18. low-speed, (low-noise) output buffer. Figure 18. Output Load Characteristics, Buffer Only

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The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII. Figure 21. Timing for XF0 and XF1 When Executing LDFI or LDII

The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. from executing, the address of the store will not be driven until the store can execute. Figure 22. Timing for XF0 When Executing an STFI or STII

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The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI. Figure 23. Timing for XF0 and XF1 When Executing SIGI

NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 24. Timing for Loading XF Register When Configured as an Output Pin

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The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin. NOTE A: I /OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 25. Timing for Changing XFx From Output to Input Mode

The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin. NOTE A: I /OxFx represents either bit 1 or bit 5 of the IOF register. Figure 26. Timing for Changing XFx From Input to Output Mode

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RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is possible. The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. Resetting the device initializes the bus control register to seven software wait states and therefore results in slow external accesses until these registers are initialized. HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA is granted. The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 27 correspond with those in the NO. column of the following table. timing requirements for RESET (see Figure 27) MIN MAX UNIT tsu(RESET-EXTCLKL) Setup time, RESET before EXTCLK low 5* P - 7 *† ns tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 5 ns * Not production tested † P = tc(EXTCLK) switching characteristics over recommended operating conditions for RESET (see Figure 27) PARAMETER MIN* MAX* UNIT td(EXTCLKH-H1H) Delay time, EXTCLK high to H1 high 2 7 ns td(EXTCLKH-H1L) Delay time, EXTCLK high to H1 low 2 7 ns td(EXTCLKH-H3L) Delay time, EXTCLK high to H3 low 2 7 ns td(EXTCLKH-H3H) Delay time, EXTCLK high to H3 high 2 7 ns tdis(H1H-DZ) Disable time, Data (high impedance) from H1 high‡ 6 ns tdis(H3H-AZ) Disable time, Address (high impedance) from H3 high 6 ns td(H3H-CONTROLH) Delay time, H3 high to control signals high 3 ns td(H1H-RWH) Delay time, H1 high to R/W high 3 ns td(H1H-IACKH) Delay time, H1 high to IACK high 3 ns tdis(RESETL-ASYNCH) Disable time, Asynchronous reset signals disabled (high impedance) from RESET low§ 6 ns * Not production tested ‡ High impedance for Dbus is limited to nominal bus keeper Z OUT = 15 kΩ. § Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

NOTES: A. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3. B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. sequence shown occurs; otherwise, an additional delay of one clock cycle is possible. reset vector is fetched twice, with no software wait states. E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10-22 kΩ pullup. If not, undesirable spurious reads can occur when these outputs are not driven. Figure 27. RESET Timing

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The following table defines the timing parameters for the INTx signals. timing requirements for INT3-INT0 response (see Figure 28) MIN NOM MAX UNIT tsu(INT-H1L) Setup time, INT3- INT0 before H1 low 4* ns th(H1L-INT) Hold time, INT3- INT0 after H1 low 0 ns tw(INT) Pulse duration, interrupt to ensure only one interrupt P + 5*† 1.5P 2P - 5* † ns * Not production tested † P = tc(H) The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The CPU and DMA respond to detected interrupts on instruction-fetch boundaries only. For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set up and held such that a logic-low condition occurs for: /C0068A minimum of one H1 falling edge /C0068No more than two H1 falling edges /C0068Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must be further restriced in pulse width as defined by tw(INT) (parameter 51) in the table above. When EDGEMODE=1, the falling edge of the INT0 -INT3 pins are detected using synchronous logic (see Figure 7). The pulse low and high time should be two CPU clocks or greater. The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has been cleared. If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible.

† Falling edge of H1 just detects INTx falling edge. ‡ Falling edge of H1 detects second INTx low, however flag clear takes precedence. ¶ Falling edge of H1 misses previous INTx low as INTx rises. Figure 28. INT3-INT0 Response Timing

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goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction. correspond with those in the NO. column of the table below. interrupt routine to signal which interrupt has occurred. Figure 29. Interrupt Acknowledge (IACK) Timing

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 serial-port timing parameters The following tables define the timing parameters for the serial port. timing requirements (see Figure 30 and Figure 31) MIN MAX UNIT t Cycle time CLKX/R CLKX/R ext tc(H) x 2.6* nstc(SCK) Cycle time, CLKX/R CLKX/R int tc(H) x 4*† tc(H) x 216* ns t Pulse duration CLKX/R high/low CLKX/R ext tc(H) + 5 nstw(SCK) Pulse duration, CLKX/R high/low CLKX/R int [tc(SCK)/2] - 4* [tc(SCK)/2] + 4* ns tr(SCK) Rise time, CLKX/R 3* ns tf(SCK) Fall time, CLKX/R 3* ns t Setup time DR before CLKR low CLKR ext 4* nstsu(DR-CLKRL) Setup time, DR before CLKR low CLKR int 5* ns t Hold time DR after CLKR low CLKR ext 3* nsth(CLKRL-DR) Hold time, DR after CLKR low CLKR int 0* ns t Setup time FSR before CLKR low CLKR ext 4* nstsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR int 5* ns t Hold time FSX/R input after CLKX/R low CLKX/R ext 3* nsth(SCKL-FS) Hold time, FSX/R input after CLKX/R low CLKX/R int 0* ns t Setup time external FSX before CLKX CLKX ext -[t c(H) - 6] [tc(SCK)/2] - 6* nstsu(FSX-CLKX) Setup time, external FSX before CLKX CLKX int -[t c(H) - 10]* tc(SCK)/2* ns * Not production tested † A cycle time of tc(H)*2 is possible when the device is operated at lower CPU frequencies. See the TMS320VC33 Silicon Update (literature number SPRZ176) for further details. switching characteristics over recommended operating conditions (see Figure 30 and Figure 31) PARAMETER MIN MAX UNIT td(H1H-SCK) Delay time, H1 high to internal CLKX/R 4* ns t Delay time CLKX to DX valid CLKX ext 6 nstd(CLKX-DX) Delay time, CLKX to DX valid CLKX int 5* ns t Delay time CLKX to internal FSX high/low CLKX ext 5 nstd(CLKX-FSX) Delay time, CLKX to internal FSX high/low CLKX int 4* ns t Delay time, CLKX to first DX bit, FSX precedes CLKX CLKX ext 4 nstd(CLKX-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX int 5* ns td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 6 ns tdis(CLKX-DXZ) Disable time, DX high impedance following last data bit from CLKX high 6 ns * Not production tested

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Guide (literature number SPRU031). numbers shown in Figure 30 and Figure 31 correspond with those in the NO. column of each table. NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 30. Fixed Data-Rate Mode Timing NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 31. Variable Data-Rate Mode Timing

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 45POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 HOLD timing HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 32 and Figure 33 occurs; otherwise, an additional delay of one clock cycle is possible. The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in Figure 32 and Figure 33 correspond with those in the NO. column of the table. The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents future hold cycles. Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue (internally) until a second external write is encountered. Figure 32, Figure 33, and the accompaning timings are for a zero wait-state bus configuration. Since HOLD is internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted before HOLDA has been active for at least one cycle. timing requirements for HOLD/HOLDA (see Figure 32 and Figure 33) MIN MAX UNIT tsu(HOLD-H1L) Setup time, HOLD before H1 low 3 ns tw(HOLD) Pulse duration, HOLD low 3tc(H)* ns *Not production tested. switching characteristics over recommended operating conditions for HOLD /HOLDA (see Figure 32 and Figure 33) PARAMETER MIN MAX UNIT tv(H1L-HOLDA) Valid time, HOLDA after H1 low -1* 3* ns tw(HOLDA) Pulse duration, HOLDA low 2tc(H) - 4* ns td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD -1 3 ns tdis(H1L-S) Disable time, STRB to the high-impedance state from H1 low 4 ns ten(H1L-S) Enable time, STRB enabled (active) from H1 low 4 ns tdis(H1L-RW) Disable time, R/W to the high-impedance state from H1 low 5* ns ten(H1L-RW) Enable time, R/W enabled (active) from H1 low 4 ns tdis(H1L-A) Disable time, Address to the high-impedance state from H1 low 4* ns ten(H1L-A) Enable time, Address enabled (valid) from H1 low 5 ns tdis(H1H-D) Disable time, Data to the high-impedance state from H1 high 4* ns * Not production tested

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Figure 32. Timing for HOLD/HOLDA (After Write) Figure 33. Timing for HOLD/HOLDA (After Read)

control registers associated with each peripheral define the modes for these pins. pin to a general-purpose input pin and vice versa. of internal-control registers associated with each peripheral. of internal-control registers associated with each peripheral. NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 34. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing

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NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 35. Change of Peripheral Pin From General-Purpose Input to Output Mode Timing

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The following table defines the timing parameter for the SHZ pin. NOTE A: Enabling SHZ destroys SM/SMJ320VC33 register and memory contents. Figure 38. Timing for SHZ The following table defines the timing parameter for the test access port. Figure 39. IEEE-1149.1 Test Access Port Timings

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 MECHANICAL DATA GNM (S-CBGA-N144) CERAMIC BALL GRID ARRAY M∅ 0,10 0,80 0,12 0,80 4201017/B 05/01 0,56 0,34 12,15 11,85 SQ 2,40 MAX 0,45 0,55 0,50 0,35 Seating Plane 9,60 TYP G A D B C E F H J L K M N 513 2 4 6 7 8 9 1 01 11 21 3 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.

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HFG (S-CQFP-F164) CERAMIC QUAD FLATPACK WITH NCTB Á Á Á Á Á Á Á Á Tie Bar Width 2.485 (63,12) 2.505 (63,63) ”B” 0.014 (0,36) 0.002 (0,05) 0.105 (2,67) MAX DETAIL ”C” 0.004 (0,10) 0.009 (0,23) 0.018 (0,46) MAX 4040231-9/J 01/99 0.130 (3,30) MAX ”C” 1.140 (28,96) 164 124 123 BSC 1.120 (28,45) 1.000 (25,40) SQ ”A” 0.020 (0,51) MAX DETAIL ”B” BRAZE DIA 4 Places BSC 8 Places 0.006 (0,15) 0.010 (0,25) 0.061 (1,55) 0.059 (1,50) 164 X DETAIL ”A” 1.150 (29,21) 0.325 (8,26) 0.275 (6,99) 1.480 (37,59) 1.520 (38,61) 0.030 (0,76) 0.040 (1,02) 0,025 (0,64) NOTES: C. All linear dimensions are in inches (millimeters). D. This drawing is subject to change without notice. E. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier F. This package is hermetically sealed with a metal lid. G. The leads are gold-plated and can be solder-dipped. H. Leads not shown for clarity purposes I. Falls within JEDEC MO-113AA (REV D)

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-0053901QYA ACTIVE CFP HFG 164 1 None Call TI Level-NC-NC-NC 5962-0053901QYC ACTIVE CFP HFG 164 1 None Call TI Level-NC-NC-NC 5962-0053902QYA ACTIVE CFP HFG 164 1 None Call TI Level-NC-NC-NC 5962-0053902QYC ACTIVE CFP HFG 164 4 None Call TI Level-NC-NC-NC SM320VC33GNMM150 ACTIVE CBGA GNM 144 1 None Call TI Level-1-235C-UNLIM SMJ320VC33HFGM150 ACTIVE CFP HFG 164 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 Addendum-Page 1

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