5962-0053001HXA

AD13280 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD13280 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

FEATURES

Dual, 80 MSPS Minimum Sample Rate Channel-to-Channel Matching, /H115501% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 80 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs ( /H115501 V and /H115500.5 V Ranges) Integral Single-Pole Low-Pass Nyquist Filter Two’s Complement Output Format

3.3 V Compatible Outputs

1.85 W per Channel

Industrial and Military Grade

APPLICATIONS

Radar Processing (Optimized for I/Q Baseband Operation) Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning PRODUCT DESCRIPTION The AD13280 is a complete dual channel signal processing solution including on board amplifiers, references, ADCs, and output termination components to provide optimized s ystem performance. The AD13280 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 12-bit, 80 MSPS performance. The AD13280 uses innovative high- density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, and performance while still maintaining excellent isolation, and providing for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general purpose. The AD13280 operates with ± 5.0 V for the analog signal condi- tioning with a separate 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent allowing operation with independent encode and analog inputs, and maintaining mini- mal crosstalk and interference. The AD13280 is packaged in a 68-lead ceramic gull wing package. Manufacturing is done on Analog Devices, Inc. M IL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–40 °C to +85°C). The components are manufactured using Analog Devices, Inc. high-speed comple- mentary bipolar process (XFCB). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 80 MSPS. 2. Input signal conditioning included; gain and impedance match. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance. 5. Compatible with 14-bit (up to) 65 MSPS family. FUNCTIONAL BLOCK DIAGRAM 100/H9024 OUTPUT TERMINA TORS TIMING 3 9 12 VREF DROUT ENCENC D9A D10A D11A (MSB) D0B (LSB) D1B D3BD2B D4B D5B D6B D7B D8B TIMING D9B ENC ENC B–IN D10B D11B (MSB) (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A AD13280 DROUT A 100/H9024 OUTPUT TERMINA TORS AMP-IN-B-2 AMP-IN-B-1AMP-IN-A-2 AMP-IN-A-1 AMP-OUT -A A–IN A+IN B+IN AMP-OUT -B DROUTB DROUT VREF

REV. 0–2– AD13280–SPECIFICATIONS (AVCC = +5 V, AVEE = –5 V, DV CC = +3.3 V; applies to each ADC with Front-End Amplifier unless otherwise noted.) Test Mil AD13280AZ/BZ Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY1 No Missing Codes Full IV 12 Guaranteed Offset Error 25 °C I 1 –2.2 ± 1.0 +2.2 % FS Full VI 2, 3 –2.2 ± 1.0 +2.2 % FS Offset Error Channel Match Full VI 1, 2, 3 –1.0 ± 0.1 +1.0 % Gain Error2 25°C I 1 –3 –1.0 +1 % FS Full VI 2, 3 –5.0 ± 2.0 +5.0 % FS Gain Error Channel Match 25 °C I 1 –1.5 ± 0.5 +1.5 % Min VI 3 –5 ± 1.0 +5 % SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 Full V ± 0.5 V AMP-IN-X-2 Full V ± 1.0 V Input Resistance AMP-IN-X-1 Full IV 12 99 100 101 Ω AMP-IN-X-2 Full IV 12 198 200 202 Ω Capacitance 25 °C V 4.0 7.0 pF Analog Input Bandwidth 3 Full V 100 MHz DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A–IN and B+IN to B–IN 4 Full V ± 1V Input Impedance 25 °C V 618 Ω Analog Input Bandwidth Full V 50 MHz ENCODE INPUT (ENC, ENC)1 Differential Input Voltage Full IV 12 0.4 V p-p Differential Input Resistance 25 °CV 1 0 k Ω Differential Input Capacitance 25 °C V 2.5 pF SWITCHING PERFORMANCE Maximum Conversion Rate 5 Full VI 4, 5, 6 80 MSPS Minimum Conversion Rate 5 Full IV 12 20 MSPS Aperture Delay (t A)2 5 °C V 1.5 ns Aperture Delay Matching 25 °C IV 12 250 500 ps Aperture Uncertainty (Jitter) 25 °C V 0.3 ps rms ENCODE Pulsewidth High at Max Conversion Rate 25 °C IV 12 4.75 6.25 8 ns ENCODE Pulsewidth Low at Max Conversion Rate 25 °C IV 12 4.75 6.25 8 ns Output Delay (t OD) Full V 5 ns Encode, Rising to Data Ready, Rising Delay Full V 8.5 ns SNR1, 6 Analog Input @ 10 MHz 25 °C I 4 67.5 70 dBFS Min II 6 64.5 dBFS Max II 5 67.5 dBFS Analog Input @ 21 MHz 25 °C I 4 67.5 70 dBFS Min II 6 64 dBFS Max II 5 67.5 dBFS Analog Input @ 37 MHz 25 °C I 4 63.5 65 dBFS Min II 6 61.5 dBFS Max II 5 63.5 dBFS SINAD1, 7 Analog Input @ 10 MHz 25 °C I 4 67 69 dBFS Min II 6 63.5 dBFS Max II 5 67 dBFS Analog Input @ 21 MHz 25 °C I 4 65 68.5 dBFS Min II 6 63 dBFS Max II 5 65 dBFS Analog Input @ 37 MHz 25 °C I 4 54.5 59 dBFS Min II 6 53 dBFS Max II 5 54.5 dBFS

REV. 0 –3– AD13280 Test Mil AD13280AZ/BZ Parameter Temp Level Subgroup Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE 1, 8 Analog Input @ 10 MHz 25 °C I 4 75 80 dBFS Min II 6 70 Max II 5 75 Analog Input @ 21 MHz 25 °C I 4 68 75 dBFS Min II 6 67 Max II 5 68 Analog Input @ 37 MHz 25 °C I 4 56 62 dBFS Min II 6 55 Max II 5 56 SINGLE-ENDED ANALOG INPUT Passband Ripple to 10 MHz 25 °C V 0.05 dB Passband Ripple to 25 MHz 25 °C V 0.1 dB DIFFERENTIAL ANALOG INPUT Passband Ripple to 10 MHz 25 °C V 0.3 dB Passband Ripple to 25 MHz 25 °C V 0.82 dB TWO-TONE IMD REJECTION 9 fIN = 9.1 MHz and 10.1 MHz 25 °C I 4 75 80 dBc f1 and f2 are –7 dB Min II 6 71 Max II 5 75 fIN = 19.1 MHz and 20.7 MHz 25 °C V 4 77 dBc f1 and f2 are –7 dB fIN = 36 MHz and 37 MHz 25 °C V 4 60 dBc f1 and f2 are –7 dB CHANNEL-TO-CHANNEL ISOLATION 10 25°CI V 1 2 9 0 d B TRANSIENT RESPONSE 25 °CV 2 5 n s DIGITAL OUTPUTS 11 Logic Compatibility CMOS DVCC = 3.3 V Logic “1” Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V DVCC = 5 V Logic “1” Voltage Full V DVCC – 0.3 V Logic “0” Voltage Full V 0.35 V Output Coding Two’s Complement POWER SUPPLY AVCC Supply Voltage 12 Full IV 4.85 5.0 5.25 V I (AVCC) Current Full I 1, 2, 3 310 338 mA AVEE Supply Voltage 12 Full IV –5.25 –5.0 –4.75 V I (AVEE) Current Full I 1, 2, 3 38 49 mA DVCC Supply Voltage 12 Full IV 3.135 3.3 3.465 V I (DVCC) Current Full I 1, 2, 3 34 46 mA ICC (Total) Supply Current per Channel Full I 1, 2, 3 369 433 mA Power Dissipation (Total) Full I 1, 2, 3 3.72 4.05 W Power Supply Rejection Ratio (PSRR) Full V 0.01 % FSR/% V S NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 2 Gain tests are performed on AMP-IN-X-1 input voltage range. 3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180 ° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmo nics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 7 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harm onics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 8 Analog Input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel. 11 Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 12 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice.

REV. 0 AD13280 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS ELECTRICAL1 CC ENVIRONMENTAL2 Storage Temperature Range (Ambient) . . –65 °C to +150°C NOTES 1Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedance for “ES” package: θJC 2.2°C/W; θJA 24.3°C/W. TEST LEVEL I 100% Production Tested. II 100% Production Tested at 25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample Tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested with temperature at 25 °C: sample tested at temperature extremes. PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier (ES-68C) 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18765 6 8 6 7 6 6 6 5 6 4 6 3 6 24321 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD13280 AGNDB AVEEB AVCCB AGNDB D10A DROUTB AGNDA AVEEA D0A(LSB) D1A D2A D3A D4A D5A AGNDB ENCODEB ENCODEB DV CCB D0B(LSB) AGNDA AGNDA AMP-OUT-A A+IN A–IN AGNDA AMP-IN-A-2 AMP-IN-A-1 AGNDB SHIELD D1B D2B D3B DGNDA D11B(MSB) D10B D9B DGNDB AVCCA AGNDB B–IN B+IN AGNDB AMP-IN-B-2 AMP-OUT-B AMP-IN-B-1 D8B D7B D6B D5B D4B DGNDB NC SHIELD DROUTA D11A(MSB) D8A D9A D7A D6A DGNDA ENCODEA ENCODEA AGNDA AGNDA DVCCA NC NC NC = NO CONNECT NC ORDERING GUIDE Model Temperature Range (Case) Package Description Package Option AD13280AZ –25 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C AD13280AF –25 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C with Nonconductive Tie-Bar 5962-0053001HXA –40 °C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C AD13280/PCB 25 °C Evaluation Board with AD13280AZ

REV. 0 AD13280 –5– PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 35 SHIELD Internal Ground Shield between Channels 2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 4 A–IN Inverting Differential Input (Gain = 1). 5 A+IN Noninverting Differential Input (Gain = 1). 6 AMP-OUT-A Single-Ended Amplifier Output (Gain = 2). 7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ± 0.5 V). 8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ± 1.0 V). 11 AV EEA A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 12 AV CCA A Channel Analog Positive Supply Voltage (Nominally 5.0 V). 14 ENCODEA Complement of Encode; Differential Input. 15 ENCODEA Encode Input; Conversion Initiated on Rising Edge. 17 DV CCA A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). 18, 19, 37, 38 NC No Connect. 20–25, 28–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB). 26, 27 DGNDA A Channel Digital Ground. 34 DROUTA Data Ready A Output. 36 DROUTB Data Ready B Output. 39–42, 45–52 D0B–D11B Digital Outputs for ADC B. D0 (LSB). 43, 44 DGNDB B Channel Digital Ground. 53 DV CCB B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). 54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 55 ENCODEB Encode Input; Conversion Initiated on Rising Edge. 56 ENCODEB Complement of Encode; Differential Input. 58 AV CCB B Channel Analog Positive Supply Voltage (Nominally 5.0 V). 59 AV EEB B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ± 1.0 V). 63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ± 0.5 V). 64 AMP-OUT-B Single-Ended Amplifier Output (Gain = 2). 65 B+IN Noninverting Differential Input (Gain = 1). 66 B–IN Inverting Differential Input (Gain = 1).

REV. 0 AD13280 –6– FREQUENCY – MHz –130 ENCODE = 80MSPS AIN = 5MHz (–1dBFS) SNR = 69.4dBFS SFDR = 81.9dBc 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 4 5 dB TPC 1. Single Tone @ 5 MHz FREQUENCY – MHz –130 ENCODE = 80MSPS AIN = 18MHz (–1dBFS) SNR = 69.79dBFS SFDR = 76.81dBc 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 dB TPC 2. Single Tone @ 18 MHz FREQUENCY – MHz –130 0 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 ENCODE = 80MSPS AIN = 9MHz AND 10MHz (–7dBFS) SFDR = 82.77dBc dB TPC 3. Two Tone @ 9 MHz/10 MHz ENCODE = 80MSPS AIN = 10MHz (–1dBFS) SNR = 69.19dBFS SFDR = 79.55dBc FREQUENCY – MHz –130 0 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 dB TPC 4. Single Tone @ 10 MHz ENCODE = 80MSPS AIN = 37MHz (–1dBFS) SNR = 68.38dBFS SFDR = 57.81dBc FREQUENCY – MHz –130 0 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 dB TPC 5. Single Tone @ 37 MHz ENCODE = 80MSPS AIN = 19MHz AND 20MHz (–7dBFS) SFDR = 74.41dBc FREQUENCY – MHz –130 0 51 0 1 5 2 02 5 3 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 35 40 dB TPC 6. Two Tone @ 19 MHz/20 MHz –Typical Performance Characteristics

REV. 0 AD13280 –7– –1.0 0 512 ENCODE = 80MSPS DNL MAX = 0.688 CODES DNL MIN = 0.385 CODES –0.5 0.5 1.0 1.5 2.0 2.5 3.0 1024 1536 2048 2560 3072 3584 4096 LSB TPC 7. Differential Nonlinearity FREQUENCY – MHz 1.0 3.5 dBFS –10 ENCODE = 80MSPS ROLL-OFF = 0.0459dB TPC 8. Passband Ripple to 25 MHz ENCODE = 80MSPS INL MAX = 0.562 CODES INL MIN = 0.703 CODES 0 512 1024 1536 2048 2560 3072 3584 4096 LSB TPC 9. Integral Nonlinearity

The sample-to-sample variation in aperture delay. between both peak measurements. The deviation of any code from an ideal 1 LSB step. rate, these specs define an acceptable Encode duty cycle. determined by a least square curve fit. frequency drops by no more than 3 dB below the guaranteed limit. The encode rate at which parametric testing is performed. percentage of full scale is reduced to midscale. (always related back to converter full scale). (always related back to converter full scale). nent may or may not be a harmonic. of the worst third order intermodulation product; reported in dBc. Figure 1. Timing Diagram

radiated components that may be “received” by the AD13280. possible to the package, using 0.1 µF chip capacitors. can couple switching current back into the analog supplies.

1 V ÷ 1 ns) of dynamic current per bit will flow in or out of the

10 mA/bit) of transient current through the output stages. will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. the need to externally isolate the device from the receiving gate. clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required. Figure 9. Evaluation Board Mechanical Layout

REV. 0 AD13280 –12– Bill of Materials List for Evaluation Board Qty. Component Name Ref/Des Value Description Manufacturing Part No. 2 74LCX16373MTD U7, U8 Latch 74LCX16373MTD (Fairchild)

1 AD13280AZ U1 AD13280 AD13280AZ

2 ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7

10 BJACK BJ1 –BJ10 Banana Jacks 108-0740-001 (Johnson Components)

2 BRES0805 R41, R53 25 Ω 0805 SM Resistor ERJ-6GEYJ 240V

4 BRES0805 R38, R39, R55, R56 33 k Ω 0805 SM Resistor ERJ-6GEYJ 333V

28 CAP2 C1, C2, C5 –C10, 0.1 µF 0805 SM Capacitor GRM 40X7R104K025BL C12, C16–C18, C20–C26, C28, C30–C38 2 CAP2 C13, C27 0.47 µF 0805 SM Capacitor VJ1206U474MFXMB

2 H40DM J1, J2 2 × 20 40 Pin Male Connector TSW-120-08-G-D

6 IND2 L1 –L6 47 Ω SM Inductor 2743019447

4 MC10EL16 U2, U4, U9, U11 Clock Drivers MC1016EP16D

2 MC100ELT23 U4, U10 ECL/TTL Clock Drivers SY100ELT23L

8 POLCAP2 C3, C4, C11, C14, 10 µF Tantalum Polar Caps T491C106M016A57280

C15, C19, C29, C30

4 RES2 R47 –R50 0 Ω 0805 SM Resistor ERJ-6GEY OR 00V

6 RES2 R1, R2, R5, R7, R8, R54 50 Ω 0805 SM Resistor ERJ-6GEYJ 510V

36 RES2 R3, R4, R6, R9, R12 –R15, 100 Ω 0805 SM Resistor ERJ-6GEYJ 101V

R19–R28, R31–R36, R37, R42, R43, R44 –R46 R51, R52

12 SMA J3 –J14 SMA Connectors 142-0701-201

4 Standoff Standoff 313- 2477-016 (Johnson Components)

4 Screws Screws (Standoff) MPMS 004 0005 PH (Building Fasteners)

1 PCB AD13280 Eval Board (Rev. B) GS03361

REV. 0 AD13280 –13– AGNDA AGNDA –5VAA +5VAA D0A(LSB) D1A D2A D3A D4A D5A DGNDA AGNDB AGNDB ENCBB ENCB +3.3VDB D11B(MSB) D7B D6B D5B D4B DGNDB AGNDA AMP IN A 2 A+IN A–IN AGNDA SHIELD AGNDB AGNDB D10A D11A(MSBA) SHIELD DRBOUT NC NC D1B D2B D3B DGNDB AD13280 D1A D2A D3A D4A D5A D0A DGNDA AGNDA AGNDA ENCAB NC NC ENCA AGNDA +3VDA NC0A NC1A AGNDA ENCA ENCAB –5VAA 0.1/H9262F C10 0.1/H9262F C36 0.1/H9262F OUT 3.3VDA C34 0.1/H9262F +5VAA AGNDA AGNDA C35 0.1/H9262F AGNDA AMP IN A 1 AMP OUT A AGNDA AGNDB B–IN B+IN AMP OUT B AMP IN B 1 AMP IN B 2 –5.2VAB +5VAB DGNDA AGNDB D8B D9B D10B D0B(LSBB) DRAOUT D9A D8A D7A D6A DGNDA D10A D11A DRBOUTNC0B NC1B D1B D2B D3B DGNDB D0B DRAOUT D9A D8A D7A D6A DGNDA E56 E55 LIDB E65 E48 E40DGNDA DGNDB E69 E70 E49 AGNDA E51 E50 E72 E74 E77 E75 E73 E71 SMA AGNDA SMA E76 E78 E83 E81 E79AGNDA SMA AGNDA J13 SMA AGNDA E68 E66 AGNDB E54 E53 J7 SMA AGNDB E86E85 E52 AGNDB AGNDB J14 SMA AGNDB SMA AGNDB SMA DGNDB –5VAB C33 0.1/H9262F C18 0.1/H9262F C37 0.1/H9262F OUT 3.3VDB C17 0.1/H9262F +5VAB AGNDB AGNDB C38 0.1/H9262F AGNDB AGNDB ENCBB ENCB D11B D7B D6B D5B D4B DGNDB AGNDB D8B D9B D10B E67 LIDA E80 E82 E84 NC = NO CONNECT L1C29 10/H9262F +3VDA C62 0.1/H9262F 47/H9024 /H1155020% @100MHz DGNDA DUT 3.3VDA BJ10 L2C30 10/H9262F +3VDB C16 0.1/H9262F 47/H9024 /H1155020% @100MHz DGNDB DUT 3.3VDB BJ9 10/H9262F +3VAA C20 0.1/H9262F 47/H9024 /H1155020% @100MHz AGNDA +5VAA BJ6 AGNDA L4C4 10/H9262F +5VAB C21 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDB +5VAB BJ5 AGNDB L5C11 10/H9262F –5VAA C32 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDA –5VAA BJ2 AGNDA L6C19 10/H9262F –5VAB C31 0.1/H9262F 47/H9024 /H1155020%@100MHz AGNDB –5VAB BJ1 AGNDB Figure 10a. Evaluation Board

REV. 0 AD13280 –14– MSB B11B B10B B9B B8B B7B B6B F1B DGNDB F2B LSB B0B B1B B2B B3B DGNDB B5B B4B C14 10/H9262F BUFLA TB 50/H9024E64 E63 E62 DRAOUT 3.3VDB DGNDB H40DN F3B F0B R11, DNI25 113 112 VCC 111 110 GND GND GND VCC LE2 115 114 GND O13 O12 VCC O11 O10 GND GND GND VCC OE2 O15 O14 GND DUT 3.3VDB DGNDB DGNDB DGNDB DUT 3.3VDB DGNDB DGNDB R10, DNI R30, DNI R29, DNI R28, 100/H9024 R27, 100/H9024 R26, 100/H9024 R12, 100/H9024 R9, 100/H9024 R35, 100/H9024 R34, 100/H9024 R33, 100/H9024 R32, 100/H9024 R31, 100/H9024 R25, 100/H9024 LE1 OE1 DUT 3.3VDB DGNDB DGNDB DGNDB DUT 3.3VDB DGNDB R49 0/H9024 R50 0/H9024 DGNDB 50/H9024 LA TCHB E57 NC0B NC1B LSB D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B MSB D11B F0B F1B F2B F3B B0B (LSB) B1B B2B B3B B4B B5B B6B B7B B8B B9B B10B B11B (MSB) DGNDB 74LCX16374 R36, 100/H9024 MSB B11A B10A B9A B8A B7A B6A F1A DGNDA F2A LSB B0A B1A B2A B3A DGNDA B5A B4A C15 10/H9262F BUFLA T A 50/H9024E61 E60 E59DRAOUT 3.3VDA DGNDA H40DM F3A F0A R18, DNI25 113 112 VCC 111 110 GND GND GND VCC LE2 115 114 GND O13 O12 VCC O11 O10 GND GND GND VCC OE2 O15 O14 GND DUT 3.3VDA DGNDA DGNDA DGNDA DUT 3.3VDA DGNDA DGNDA R17, DNI R40, DNI R44, DNI R45, 100/H9024 R46, 100/H9024 R15, 100/H9024 R14, 100/H9024 R13, 100/H9024 R24, 100/H9024 R23, 100/H9024 R22, 100/H9024 R21, 100/H9024 R20, 100/H9024 R19, 100/H9024 R15, 100/H9024 LE1 OE1 DUT 3.3VDA DGNDA DGNDA DGNDA DUT 3.3VDA DGNDA R47 0/H9024 R48 0/H9024 DGNDA 50/H9024 LA TCHA E58 NC0A NC1A LSB D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A MSB D11A F0A F1A F2A F3A B0A (LSB) B1A B2A B3A B4A B5A B6A B7A B8A B9A B10A B11A (MSB) DGNDA 74LCX16374 Figure 10b. Evaluation Board

REV. 0 AD13280 –15– NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 AGNDA OUT NR IN SD 1ERR GND ADP3330 AGNDA DB QB C13 0.47/H9262F +3.3VA C7 0.1/H9262F 0.1/H9262F ENCAB ENCA AGNDA R43 100/H9024 AGNDA R56 33k/H9024 NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 DB QB NC = NO CONNECT VCC VEE NC D VBB MC100EPT23 DB Q1 +3.3VDA 0.47/H9262F R55 33k/H9024 DGNDAC2 0.1/H9262F R41 25/H9024 J12 SMA ENCODE SMA 50/H9024 0.1/H9262F AGNDA AGNDA AGNDA DGNDA DGNDA AGNDA 100/H9024 100/H9024 DGNDA DGNDC5 0.47/H9262F +3.3VDA LA TCHA BUFLA T A E23 E19 +5VAA R42 100/H9024 E17 E27 E25 E21 E32 E44 E42 E10 E33 E18 E28 E26 E20 E31 E43 E41 E34 DGNDA AGNDA E38 E29 E36 E14 E37 E30 E35 E13 DGNDB AGNDB SO1 SO2 SO4 SO5 SO6 E45 E46 SO3 E15 E16 E12 DGNDA DGNDB E11 E39 E47 DGNDA DGNDB AGNDB1 BJ3 AGNDA1 BJ4 DGNDB BJ7 DGNDB DGNDA BJ8 DGNDA NC = NO CONNECT VCC Q VEE NC D VBB U11 MC10EL16 AGNDB OUT NR IN SD 1ERR GND ADP3330 AGNDB DB QB C27 0.47/H9262F +3.3VB C24 0.1/H9262F C28 0.1/H9262F ENCBB ENCB AGNDB R52 100/H9024 AGNDA R38 33k/H9024 NC = NO CONNECT VCC Q VEE NC D VBB MC10EL16 DB QB NC = NO CONNECT VCC VEE NC D VBB U10 MC100EPT23 DB Q1 +3.3VDB C25 0.47/H9262F R39 33k/H9024 DGNDB C23 0.1/H9262F R53 25/H9024 J11 SMA J10 ENCODE SMA R54 50/H9024 C22 0.1/H9262F AGNDB AGNDB AGNDB DGNDB DGNDB DGNDB R37 100/H9024 DGNDB DGNDBC26 0.1/H9262F +3.3VDA LA TCHB BUFLA TB E24 E22 +5VAB R51 100/H9024 100/H9024 Figure 10c. Evaluation Board

REV. 0 AD13280 –19– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier (ES-68C) 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) PIN 1 10 26 TOP VIEW (PINS DOWN) 0.800 (20.32) BSC 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) MAX 0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 1.070 (27.18) MIN

REV. 0–20– C02386–2.5–4/01(0) PRINTED IN U.S.A. AD13280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier With Non-Conductive Tie-Bar (ES-68C) DETAIL A 0.010 (0.254) 30/H11543 0.050 (1.27) 0.020 (0.508) 0.175 (4.45) MAX0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) PIN 1 TOP VIEW (PINS DOWN) 0.800 (20.32) BSC 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) /H11547 45/H11543 0.015 (0.3) /H11547 45/H11543

3 PLS

0.040 (1.02) R TYP 0.350 (8.89) TYP 2.000 (8.89) TYP