Complementary Switch FET Drivers .

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SLUSAU8,*]
  • PDF pages: 14

Technical content

(TOP VIEW) UC1715-SP www.ti.com SLUSAU8 –MAY 2013 COMPLIMENTARYSWITCHFETDRIVERS Check forSamples: UC1715-SP 1FEATURES

  • SingleInput(PWM and TTL Compatible)
  • High CurrentPower FET Driver, 1-A Source/2-ASink
  • AuxiliaryOutput FET Driver, 0.5-ASource/1-ASink
  • Time Delays Between Power and Auxiliary Outputs IndependentlyProgrammable from 50 ns to700 ns
  • Time Delay or True Zero-VoltageOperation IndependentlyConfigurableforEach Output
  • SwitchingFrequency to1 MHz
  • Typical50-nsPropagationDelays
  • ENBL Pin Activates220-μA Sleep Mode
  • Power Output isActiveLow inSleep Mode
  • Synchronous RectifierDriver XXX XXX

DESCRIPTION

The UC1715 is a high speed driverdesigned to providedrivewaveforms for complementary switches. Complementary switchconfigurationsare commonly used in synchronous rectificationcircuitsand active clamp/resetcircuits,whichcan providezerovoltageswitching.Inordertofacilitatethesoftswitchingtransitions, independentlyprogrammable delaysbetween thetwo outputwaveforms are providedon thisdriver.The delay pinsalsohave truezerovoltagesensingcapabilitywhichallowsimmediateactivationofthecorrespondingswitch when zero voltageisapplied.Thisdevicerequiresa PWM-type inputto operateand can be interfacedwith commonly availablePWM controllers. ORDERING INFORMATION (1) TJ PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to125°C CFP (W) 5962-0052102VFA 5962-0052102VFA (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLUSAU8 –MAY 2013 www.ti.com DEVICE INFORMATION PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. 1,7,8, N/C 9,10, - N/C pinsarenotbonded out.Externalconnectionswillnotaffectdevicefunctionality. 12,13 The VCC inputrangeisfrom7 V to20 V.Thispinshouldbe bypassedwitha capacitortoGND consistentwithVCC 2 I peak loadcurrentdemands. The PWR outputwaitsfortheT1 delayaftertheINPUT ’s risingedge beforeswitchingon,butswitchesoff immediatelyatINPUT ’s fallingedge (neglectingpropagationdelays).Thisoutputiscapableofsourcing1-APWR 3 O and sinking2-A ofpeak gatedrivecurrent.PWR outputincludesa passive,self-biasedcircuitwhichholdsthis pinactivelow,when ENBL ≥ 0.8V regardlessofVCC ’s voltage. Thisisthereferencepinforallinputvoltagesand thereturnpointforalldevicecurrents.Itcarriesthefull GND 4,5 - peak sinkingcurrentfromtheoutputs.Any tendencyfortheoutputstoringbelowGND voltagemust be damped orclamped such thatGND remainsthemost negativepotential. The AUX switchesimmediatelyatINPUT ’s risingedge butwaitsthroughtheT2 delayafterINPUT ’s falling AUX 6 edge beforeswitching.AUX iscapableofsourcing0.5-Aand sinking1-A ofdrivecurrent.Duringsleepmode, AUX isinactivewitha highimpedance. Thispinfunctionsinthesame way as T1 butcontrolsthetimedelaybetween PWR turn-offand activationof theAUX switch. The resistoron thispinsetsthechargingcurrenton internaltimingcapacitorstoprovideindependenttime control.The nominalvoltagelevelatthispinis3 V and thecurrentisinternallylimitedto1 mA. The totaldelayT2 11 fromINPUT tooutputincludesa propagationdelayinadditiontotheprogrammabletimerbutsincethe propagationdelaysareapproximatelyequal,therelativetimedelaybetween thetwo outputscan be assumed tobe solelya functionoftheprogrammed delays.The relationshipofthetimedelayvs.RT isshown inthe TypicalCharacteristicscurves. The inputswitchesatTTL logiclevels(approximately1.4V) buttheallowablerangeisfrom0 V to20 V, allowingdirectconnectiontomost common IC PWM controlleroutputs.The risingedge immediatelyswitches theAUX output,and initiatesa timingdelay,T1,beforeswitchingon thePWR output.Similarly,theINPUT fallingedge immediatelyturnsoffthePWR outputand initiatesa timingdelay,T2,beforeswitchingtheAUXINPUT 14 I output. Itshouldbe notedthatiftheinputsignalcomes froma controllerwithFET drivecapability,thissignalprovides anotheroption.INPUT and PWR providea delayonlyattheleadingedge whileINPUT and AUX providethe delayatthetrailingedge. A resistortogroundprogramsthetimedelaybetween AUX switchturn-offand PWR turn-on. The resistoron thispinsetsthechargingcurrenton internaltimingcapacitorstoprovideindependenttime control.The nominalvoltagelevelatthispinis3 V and thecurrentisinternallylimitedto1 mA. The totaldelay T1 15 fromINPUT tooutputincludesa propagationdelayinadditiontotheprogrammabletimerbutsincethe propagationdelaysareapproximatelyequal,therelativetimedelaybetween thetwo outputscan be assumed tobe solelya functionoftheprogrammed delays.The relationshipofthetimedelayvs.RT isshown inthe TypicalCharacteristicscurves. The ENBL inputswitchesatTTL logiclevels(approximately1.2V),and itsinputrangeisfrom0 V to20 V. ENBL 16 I The ENBL inputwillplacethedeviceintosleepmode when itisa logicallow.The currentintoVCC duringthe sleepmode istypically220 μA.

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S Q R TIMER VREF S Q R TIMER VREF 50ns –700ns 50ns –700ns ENBL VCC GND BIAS 1.4V ENABLE

6 AUX

3 PWR

2 VCC

5 GND

www.ti.com SLUSAU8 –MAY 2013 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS (1)(2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VCC Supplyvoltage 20 V Continuous -100mA Power driver Peak (3) -1A IOH Continuous -100mA Auxiliarydriver Peak(3) -500mA Continuous 100 mA Power driver Peak(3) 2 A IOL Continuous 100 mA Auxiliarydriver Peak(3) 1 A VI Inputvoltagerange(INPUT,ENBL) –0.3V to20 V TJ Maximum operatingjunctiontemperature 150°C Tstg Storagetemperaturerange –65°C to150°C Tlead Maximum leadtemperature(soldering,10 seconds) 300°C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagesarewithrespecttoground.Currentsarepositiveinto,negativeoutofthespecifiedterminal. (3) RMS drivecurrenton any pintobe restrictedto672 mA. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UC1715-SP

SLUSAU8 –MAY 2013 www.ti.com THERMAL INFORMATION UC1715-SP THERMAL METRIC (1) W UNITS

16 PINS

θJA Junction-to-ambientthermalresistance(2) 72.9 θJC Junction-to-casethermalresistance(3) 8.25 °C/W θJB Junction-to-boardthermalresistance(4) 43.4 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specificJEDEC- standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (4) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8.

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ELECTRICAL CHARACTERISTICS

VCC = 15 V,ENBL ≥ 2 V,R T1 = 100 kΩ fromT1 toGND, R T2 = 100 kΩ fromT2 toGND, TA = TJ = –55°C to125°C (unless otherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overall VCC 7 18 V ICC ,nominal ENBL = 3 V 25 mA ICC ,sleepmode ENBL = 0.8V 300 µA Power Driver(PWR) Pre turn-onPWR output,low VCC = 0 V,IOUT = 10 mA, ENBL ≤ 0.8V 2 V INPUT = 0.8V,IOUT = 40 mA 1 PWR outputlow,sat.(VPWR ) V INPUT = 0.8V,IOUT = 100 mA 1.5 INPUT = 3 V,IOUT = −40 mA 3 PWR outputhigh,sat.(VCC − VPWR ) V INPUT = 3 V,IOUT = −100 mA 3 Risetime C L = 2200 pF 60 ns Falltime C L = 2200 pF 60 ns T1 delay,AUX toPWR (1) INPUT risingedge,R T1 = 10 kΩ,see (2) 45 200 ns T1 delay,AUX toPWR (1) INPUT risingedge,R T1 = 100 kΩ,see (2) 250 1300 ns PWR propdelay INPUT fallingedge,50%, see (3) 300 ns AuxiliaryDriver(AUX) AUX preturn-onAUX outputlow(VPAUX ) VCC = 0 V,ENBL ≤ 0.8V,IOUT = 10 mA 2 V VIN = 3 V,IOUT = 40 mA 1 AUX outputlow,sat.(VAUX ) V VIN = 3 V,IOUT = 100 mA 1.5 VIN = 0.8V,IOUT = -40mA 3 AUX outputhigh,sat.(VCC – VAUX ) V VIN = 0.8V,IOUT = -100mA 3 Risetime C L = 2200 pF 60 ns Falltime C L = 2200 pF 60 ns T2 delay,PWR toAUX (1) INPUT fallingedge,R T2 = 10 kΩ,see (2) 45 130 ns T2 delay,PWR toAUX (1) INPUT fallingedge,R T2 = 100 kΩ,see (2) 200 700 ns AUX propdelay INPUT risingedge,50%, see (3) 185 ns Enable (ENBL) Inputthreshold 2.8 V Inputcurrent,IIH ENBL = 15 V -10 10 µA Inputcurrent,IIL ENBL = 0 V -15 15 µA Currentlimit T1 = 0 V -2 -0.5 mA NominalvoltageatT1 2.7 3.3 V Minimum T1 delay T1 = 2.5V,see (2) 80 ns Currentlimit T2 = 0 V -2 -0.5 mA NominalvoltageatT12 2.7 3.3 V Minimum T2 delay T2 = 2.5V,see (2) 80 ns Input(INPUT) Inputthreshold 2.8 V Inputcurrent,IIH ENBL = 15 V -10 10 µA Inputcurrent,IIL ENBL = 0 V -20 20 µA (1) The parameterisguaranteedtothelimitspecifiedby characterization,butnotproductiontested. (2) T1 and T2 delayisdefinedas thetimebetween the50% transitionpointofAUX (PWR) and the50% transitionpointofPWR (AUX) with no capacitiveloadon eitheroutput. (3) Propagationdelaysaremeasured fromthe50% pointoftheinputsignaltothe50% pointoftheoutputsignal’s transitionwithno loadon outputs. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UC1715-SP

0 100 200 300 400 500 600 700 800 9001000 Switching Frequency (kHz) Icc (mA) 100 200 300 400 500 0 10 20 30 40 50 60 70 80 90 100 RT (k )/c87 DELA Y (ns) T1 vs RT1 T2 vs RT2 PROP AGA TION DELA YS INPUT PWR OUTPUT T1 DELA Y T2 DELA Y UC1715 AUX OUTPUT UC1715-SP SLUSAU8 –MAY 2013 www.ti.com TYPICAL CHARACTERISTICS A. T1 delayisdefinedfromthe50% pointofthetransitionedge ofAUX tothe10% oftherisingedge ofPWR. T2 delay isdefinedfromthe90% ofthefallingedge ofPWR tothe50% pointofthetransitionedge ofAUX. B. Propagationdelaytimesaremeasured fromthe50% pointoftheinputsignaltothe10% pointoftheoutputsignal’s transitionwithno loadon outputs. Figure1. Time Relationships Figure2.T1 Delay,T2 Delay vs.R T Figure3.ICC vs SwitchingFrequency With No Load and 50% Duty Cycle R T1 = R T2 = 50 kΩ

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-75 -50 -25 0 25 50 75 100 125 T emperature (°C) Deadband Delay (ns) RT2 = 100k RT2 = 50k RT2 = 10k RT2 < 6k 0 10 20 30 40 50 60 70 80 90 100 RT (kΩ) Icc (mA) 100 200 300 400 500 600 -75 -50 -25 0 25 50 75 100 125 T emperature (°C) Deadband Delay (ns) RT1 = 100k RT1 = 50k RT1 = 10k RT1 < 6k UC1715-SP www.ti.com SLUSAU8 –MAY 2013 TYPICAL CHARACTERISTICS (continued) Figure4.ICC vs R T With Opposite R T = 50 kΩ Figure5.T1 Deadband vs.Temperature AUX toPWR Figure6.T2 Deadband vs.Temperature PWR toAUX Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UC1715-SP

SLUSAU8 –MAY 2013 www.ti.com TYPICAL APPLICATIONS Figure7.TypicalApplicationWith Timed Delays Figure8.Using theTimer InputforZero-VoltageSensing Figure9.Self-ActuatedSleep Mode With Absence ofInputPWM Signal.Wake Up Occurs With FirstPulse While Turn-Offis Determined by the(RTO CTO) Time Constant

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www.ti.com SLUSAU8 –MAY 2013 TYPICAL APPLICATIONS (continued) Figure10.Using theUC1715 as a Complementary Synchronous RectifierSwitch DriverWith N-Channel FETs Figure11.Synchronous RectifierApplicationWith Charge Pump toDriveHigh-SideN-Channel Buck Switch.VIN isLimitedto

10 V as VCC WillRise toApproximately2VIN

Figure12.TypicalForward ConverterTopology With ActiveReset Providedby theUC1714 DrivingN-channelswitch(Q1)and P-Channel AuxilliarySwitch (Q2) Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UC1715-SP

SLUSAU8 –MAY 2013 www.ti.com TYPICAL APPLICATIONS (continued) Figure13.Using N-Channel ActiveReset Switch With FloatingDriveCommand

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www.ti.com 7-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples 5962-0052102VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-0052102VF A UC1715W-SP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1715-SP :

  • Catalog: UC1715

www.ti.com 7-May-2013 Addendum-Page 2 NOTE: Qualified Version Definitions:

  • Catalog - TI's standard catalog product

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