5962-0051901NXD

THS12082_09 TI1 | Alldatasheet

Document overview

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Technical content

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

/C0068 Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal /C0068 Integrated 16 Word FIFO /C0068 Signal-to-Noise and Distortion Ratio: 66 dB at f I = 2 MHz /C0068 Differential Nonlinearity Error: ±1 LSB /C0068 Integral Nonlinearity Error: ±1.5 LSB /C0068 Auto-Scan Mode for 2 Inputs /C0068 3-V or 5-V Digital Interface Compatible /C0068 Low Power: 216 mW Max /C0068 5-V Analog Single Supply Operation /C0068 Internal Voltage References. . . 50 PPM/°C and ±5% Accuracy /C0068 Parallel µC/DSP Interface

applications

/C0068 Radar Applications /C0068 Communications /C0068 Control Applications /C0068 High-Speed DSP Front-End /C0068 Automotive Applications

description

The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In the single conversion mode, a single and simultaneous conversion can be initiated by using the single conversion start signal (CONVST ). The conversion clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal clock oscillator is switched off in the continuous conversion mode. The THS12082C is characterized for operation from 0°C to 70°C, and the THS12082I is characterized for operation from –40°C to 85°C. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BV DD BGND RA0/D10 RA1/D11 CONV_CLK (CONVST ) DATA_AV OV_FL RESET AINP AINM REFIN REFOUT REFP REFM AGND AV DD CS0 CS1 WR (R/W) RD DV DD DGND DA PACKAGE (TOP VIEW)

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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(DA) 0°C to 70°C THS12082CDA –40°C to 85°C THS12082IDA functional block diagram Logic and Control Control Register S/H S/H Single-Ended and/or Differential MUX 12-Bit Pipeline ADC REFP REFM 1.225 V REF 2.5 V FIFO 16 × 12 12 12 Buffers REFOUT DATA_AV OV_FL BV DD D10/RA0 D11/RA1 BGND AGND DGND 3.5 V 1.5 V AV DD DV DD REFP REFM AINP AINM CONV_CLK (CONVST ) CS0 CS1 RD WR (R/W) RESET REFIN

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AINP 30 I Analog input, single-ended or positive input of differential channel A AINM 29 I Analog input, single-ended or negative input of differential channel A AV DD 23 I Analog supply voltage AGND 24 I Analog ground BV DD 7 I Digital supply voltage for buffer BGND 8 I Digital ground for buffer CONV_CLK (CONVST ) 15 I Digital input. This input is used to apply an external conversion clock in the continuous conversion mode. In the single conversion mode, this input functions as the conversion start (CONVST ) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14. DGND 17 I Digital ground. Ground reference for digital circuitry. DV DD 18 I Digital supply voltage D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB RA0/D10 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. RA1/D11 14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. OV_FL 32 O Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO. REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. RESET 31 I Hardware reset of the THS12082. Sets the control register to default values. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires a capacitor of 10 µF to AGND for filtering and stability. RD † 19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. WR (R/W)† 20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input (WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section. † The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions power supply MIN NOM MAX UNIT AV DD 4.75 5 5.25 Supply voltage DV DD 3 3.3 5.25 V BV DD 3 3.3 5.25 analog and reference inputs MIN NOM MAX UNIT Analog input voltage in single-ended configuration VREFM VREFP V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,VREFP (optional) 3.5 AV DD –1.2 V External reference voltage, VREFM (optional) 1.4 1.5 V Input voltage difference, REFP – REFM 2 V digital inputs MIN NOM MAX UNIT High level input voltage VIH BV DD = 3 V 2 V High-level input voltage, VIH BV DD = 5.25 V 2.6 V Low level input voltage VIL BV DD = 3 V 0.6 V Low -level input voltage, VIL BV DD = 5.25 V 0.6 V Input CONV_CLK frequency DV DD = 3 V to 5.25 V 0.1 8 MHz CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DV DD = 3 V to 5.25 V 62 83 5000 ns CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DV DD = 3 V to 5.25 V 62 83 5000 ns O perating free air temperature TA THS12082CDA 0 70 °COperating free-air temperature, TA THS12082IDA –40 85

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions, VREFP = 3.5 V, VREFM = 1.5 V (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital inputs IIH High-level input current DV DD = digital inputs –50 50 µA IIL Low-level input current Digital input = 0 V –50 50 µA C i Input capacitance 5 pF Digital outputs VOH High-level output voltage IOH = –50 µA, BV DD = 3.3 V, 5 VBV DD –0.5 V VOL Low-level output voltage IOL = 50 µA, BV DD = 3.3 V, 5 V 0.4 V IOZ High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA C O Output capacitance 5 pF C L Load capacitance at databus D0–D11 30 pF electrical characteristics over recommended operating conditions, AVDD = 5 V, DV DD = BVDD = 3.3-V, fs = 8 MSPS, VREF = internal (unless otherwise noted) dc specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bits Accuracy Integral nonlinearity, INL ±1.5 LSB Differential nonlinearity, DNL ±1 LSB Offset error After calibration in single-ended mode 20 LSB Offset error After calibration in differential mode –20 20 LSB Gain error –20 20 LSB Analog input Input capacitance 15 pF Input leakage current VAIN = VREFM to VREFP ±10 µA Internal voltage reference Accuracy, VREFP 3.3 3.5 3.7 V Accuracy, VREFM 1.4 1.5 1.6 V Temperature coefficient 50 PPM/ °C Reference noise 100 µV Accuracy, REFOUT 2.475 2.5 2.525 V Power supply IDDA Analog supply current AV DD =5 V, BV DD = DVDD = 3.3 V 36 40 mA IDDD Digital supply current AV DD = 5 V BV DD = DVDD = 3.3 V 0.5 1 mA IDDB Buffer supply current AV DD = 5 V, BV DD = DVDD = 3.3 V 1.5 4 mA IDD_AP Analog supply current in power-down modeAV DD = 5 V, BV DD = DVDD = 3.3 V 8 mA Power dissipation AV DD = 5 V, DV DD = BVDD = 3.3 V 186 216 mW Power dissipation in power down AV DD = 5 V, DV DD = BVDD = 3.3 V 30 mW

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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electrical characteristics over recommended operating conditions, VREF = internal, fs = 8 MSPS, fI = 2 MHz at –1dBFS (unless otherwise noted) ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SINAD Signal to noise ratio + distortion Differential mode 63 65 dB SINAD Signal-to-noise ratio + distortion Single-ended mode (see Note 1) 64 dB SNR Signal to noise ratio Differential mode 64 69 dB SNR Signal-to-noise ratio Single-ended mode (see Note 1) 68 dB THD Total harmonic distortion Differential mode –70 –67 dB THD Total harmonic distortion Single-ended mode –68 dB ENOB Effective number of bits Differential mode 10.17 10.5 Bits (SNR) Effective number of bits Single-ended mode (see Note 1) 10.34 Bits SFDR Spurious free dynamic range Differential mode 67 71 dB SFDR Spurious free dynamic range Single-ended mode 69 dB Analog Input Full-power bandwidth with a source impedance of 150 Ω in differential configuration. Full scale sinewave, –3 dB 96 MHz Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration. Full scale sinewave, –3 dB 54 MHz Small-signal bandwidth with a source impedance of 150 Ω in differential configuration. 100 mVpp sinewave, –3 dB 96 MHz Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration. 100 mVpp sinewave, –3 dB 54 MHz NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock.

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing specifications (AVDD = BVDD = DVDD = 5 V, VREFP = 3.5 V, VREFM = 1.5 V, CL < 30 pF )† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA_AV) Delay time 5 ns td(o) Delay time 5 ns td(pipe) Latency 5 CONV CLK † Refer to Figure 2 timing specification of the single conversion mode‡ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tc Clock cycle of the internal clock oscillator 117 125 133 ns t1 Pulse duration CONVST 1 analog input 1.5×tc nst1 Pulse duration, CONVST 2 analog inputs 2.5×tc ns tdA Aperture time 1 ns Time between consecutive start of single 1 analog input 2×tc nst2 g conversion 2 analog inputs 3×tc ns 1 analog input, TL = 1 6.5×tc+15 ns 2 analog inputs, TL = 2 7.5×tc+15 ns 1 analog input, TL = 4 3×t2 +6.5×tc+15 ns td(DATA AV) Delay time, DATA_AV becomes active for the2 analog inputs, TL = 4 t2 +7.5×tc+15 ns td(DATA_AV) y, _ trigger level condition: TRIG0 = 1, TRIG1 = 11 analog input, TL = 8 7×t2 +6.5×tc+15 ns 2 analog inputs, TL = 8 3×t2 +7.5×tc+15 ns 1 analog input, TL = 14 13×t2 +6.5×tc+15 ns 2 analog inputs, TL = 12 5×t2 +7.5×tc+15 ns ‡ Refer to Figure 1

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the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. operate on the seven preceding samples. FIFO reset command. This is due to the latency of the pipeline architecture of the THS12082. conversion is started with every falling edge of the applied clock signal. The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations. Table 1. Maximum Conversion Rate Table 2 shows the maximum conversion rate in the single conversion mode.

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The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. of a trigger level set to 1 or 4. Figure 2. Timing of Continuous Conversion Mode (1-channel operation) Figure 3. Timing of Continuous Conversion Mode (2-channel operation)

The digital output data format of the THS12082 can be in either binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 3. Binary Output Format for Single-Ended Configuration Table 4. Twos Complement Output Format for Single-Ended Configuration Table 5. Binary Output Format for Differential Configuration Table 6. Twos Complement Output Format for Differential Configuration

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integrated FIFO enables a problem-free processing of data. The FIFO is provided as a flexible circular buffer. of interrupts to be served by a processor can be reduced significantly. Figure 4. Circular Buffer location which will be read next. The write pointer indicates the location which contains the last written sample. condition is satisfied when as many values as selected for the trigger level where written into the FIFO. therefore always maintained.

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desired mode. The bit definitions of both control registers are shown in Table 7. Table 7. Bit Definitions of Control Register CR0 and CR1 to D9 contain the desired control register value. Table 8 shows the addressing of each control register. Table 8. Control Register Addressing

The initialization of the THS12082 should be done according to the configuration flow shown in Figure 9. Figure 9. THS12082 Configuration Flow

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Table 9. Control Register 0 Bit Functions Bit 0 = 0 → The internal reference is selected. Bit 0 = 1 → The external reference voltage is selected. Bit 1 = 0 → Continuous conversion mode is selected. CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 → Single conversion mode is selected. Bit 2 = 0 → The ADC is active. Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10. Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10. Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10. feedback allows the check of all hardware connections and the ADC operation. Refer to Table 11 for selection of the three different test voltages.

than one input channel is selected. Table 10 shows the possible selections. Table 10. Analog Input Channel Configurations Table 11. Test Mode

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Table 12. Control Register 1 Bit Functions value is converted and written into the FIFO. Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 → no overflow occurred. Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor. By writing a 1 into this bit, the FIFO is reset. indicates to the processor that the ADC values can be read. Refer to Table 13. DATA_AV is active low. Refer to Table 14. control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6. control register 0. The second read after bit 9 is set to 1 contains the value of control register 1.

Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). the signal DATA_AV to indicate to the processor that the ADC values can be read. and is able to distinguish between the channels. Table 13. FIFO Trigger Level (R/W). The two chip select inputs can be used to interface easily to a processor. to its inactive state will then deactivate RDint again. Figure 10. Logical Combination of CS0, CS1, RD, and WR

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determines the polarity of DATA_AV. This is shown in Table 14. Table 14. DATA_AV Type the DATA_T selection (pulse or level). type should be programmed to active level mode (set bit 4 of CR1 to zero). processor, the next DATA_AV pulse (when the trigger condition is satisfied) is sent out first.

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because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid. Figure 12. Write Timing Diagram Using R/W (CS0-controlled)

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing and signal description of the THS12082 (continued) interfacing the THS12082 to the TMS320C30/31/33 DSP The following application circuit shows an interface of the THS12082 to the TMS320C30/31/33 DSPs. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. CS0 CS1 R/W DATA_AV CONV_CLK DATA RD DV DD THS12082 TMS320C30/31/33 STRB A23 R/W INTX TOUT DATA interfacing the THS12082 to the TMS320C54x using I/O strobe The following application circuit shows an interface of the THS12082 to the TMS320C54x. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. CS0 CS1 R/W DATA_AV CONV_CLK DATA RD DV DD THS12082 TMS320C54x I/O STRB A15 R/W INTX BCLK DATA

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external signal of CS0, CS1, and RD that becomes valid. Figure 13. Read Timing Diagram Using RD (RD-controlled)

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Figure 15. Single-Ended Input Stage

which are discussed in the following paragraphs. Figure 16. Differential Input Stage is common to both analog inputs. See also Figure 18. of the THS12082 must be driven from an operational amplifier that does not degrade the ADC performance. example is shown for dc-coupled level shifting in the following section, dc-coupling.

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amplifier specified for 5-V single supply can be used as shown in Figure 17. input is derived from the 2.5-V output reference REFOUT of the THS12082 by using a resistor divider. minimizes gain and offset errors. Figure 17. Level-Shift for DC-Coupled Input performance is achieved in differential mode. Figure 18. Transformer Coupled Input

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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SAMPLING FREQUENCY (DIFFERENTIAL) AV DD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dBFS fs – Sampling Frequency – MHz THD – Total Harmonic Distortion – dB Figure 24 0123456789 SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) fs – Sampling Frequency – MHz SINAD – Signal-to-Noise and Distortion – dB AV DD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dBFS Figure 25 100 0123456789 SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (DIFFERENTIAL) fs – Sampling Frequency – MHz SFDR – Spurious Free Dynamic Range – dB AV DD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dBFS Figure 26 SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (DIFFERENTIAL) fs – Sampling Frequency – MHz SNR – Signal-to-Noise – dB 0123456789 AV DD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dBFS

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) AV DD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fi – Input Frequency – MHz THD – Total Harmonic Distortion – dB Figure 32 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) SINAD – Signal-to-Noise and Distortion – dB AV DD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fi – Input Frequency – MHz Figure 33 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 95.00 100.00 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (DIFFERENTIAL) SFDR – Spurious Free Dynamic Range – dB AV DD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fi – Input Frequency – MHz 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 Figure 34 AV DD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fi – Input Frequency – MHz SIGNAL-TO-NOISE vs INPUT FREQUENCY (DIFFERENTIAL) SNR – Signal-to-Noise – dB

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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–0.80 –0.60 –0.40 –0.20 –0.00 0.20 0.40 0.60 0.80 1.00 0 500 1000 1500 2000 2500 3000 3500 4000 DNL – Differential Nonlinearity – LSB ADC Code DIFFERENTIAL NONLINEARITY vs ADC CODE AV DD = 5 V DV DD = BVDD = 3 V fs = 8 MSPS Figure 40 –0.80 –0.60 –0.40 –0.20 –0.00 0.20 0.40 0.60 0.80 1.00 0 500 1000 1500 2000 2500 3000 3500 4000 INL – Integral Nonlinearity – LSB ADC Code INTEGRAL NONLINEARITY vs ADC CODE AV DD = 5 V DV DD = BVDD = 3 V fs = 8 MSPS

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002

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definitions of specifications and terminology integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. zero offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. gain error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N /C0043 (SINAD /C0042 1.76) 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,25 0,75 0,50 0,15 NOM Gage Plane 6,20 NOM 8,40 7,80 11,1011,10 Seating Plane 10,9010,90 0,19 A 0,30 PINS ** A MAX A MIN DIM 1,20 MAX 9,60 9,80 M0,13 0°–8° 0,10 0,65 12,60 12,40 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-153

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-0051901NXD PREVIEW TSSOP DA 32 TBD Call TI Call TI THS12082CDA ACTIVE TSSOP DA 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082CDAG4 ACTIVE TSSOP DA 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082CDAR ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082CDARG4 ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082IDA ACTIVE TSSOP DA 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082IDAG4 ACTIVE TSSOP DA 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082IDAR ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082IDARG4 ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS12082QDA PREVIEW TSSOP DA 32 TBD Call TI Call TI THS12082QDAR PREVIEW TSSOP DA 32 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS12082CDAR TSSOP DA 32 2000 346.0 346.0 41.0 THS12082IDAR TSSOP DA 32 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

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