80C32E_03 AIMTEC | Alldatasheet
Document overview
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Technical content
Features
8032 Pin and Instruction Compatible Four 8-bit I/O Ports Three 16-bit Timer/Counters 256 bytes RAM Full-duplex UART Asynchronous Port Reset 6 Sources, 2 Level Interrupt Structure 64 Kbytes Program Memory Space 64 Kbytes Data Memory Space Power Control Modes Idle Mode Power-down Mode On-chip Oscillator Operating Frequency: 30 MHz Power Supply: 4.5V to 5.5V Temperature Range: Military (-55oC to 125oC) Packages: Side Brazed 40-pin, MQFPJ 44-pin QML Q and V with SMD 5962-00518 SCC C an B with Specification SCC9521002
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit microcontroller. The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6- source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters. The fully static design of the 80C32E reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C32E has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. Rad. Tolerant 8-bit ROMless Microcontroller 80C32E
4149M –AERO –06/03 Block Diagram Pin Configuration Note: NIC: No Internal Connection Timer 0INT RAM 256x8 RxD TxD WR RD EA PSEN ALE XTAL2 XTAL1 UART CPU INT1 CtrlINT0 C51 CORE Port 0 Port 1Port 2Port 3 Parallel I/O Ports & Ext. Bus IB-bus RST Timer 1 Timer 2 T2EX 5 4 3 2 1 6 44 43 42 41 40 P1.4 P1.0 P1.1 P1.3 P1.2 NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* MQFPJ44 18 19 20 21 22 23 24 25 26 27 28 P1.7 RST P3.0/RxD P3.1/TxD P1.3 P1.5 P3.2/INT0 P3.3/INT1 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P0.4/A4 P0.6/A6 P0.5/A5 P0.7/A7 ALE PSEN EA/VPP P2.7/A15 P2.5/A13 P2.6/A14 P1.0/T2 P1.1/T2EX VCC P0.0/A0 P0.1/A1 P0.2/A2 P0.3/A3 SB40 P1.6 P1.4 P1.2 P3.4/T0
4149M –AERO –06/03 Pin Description Mnemonic Type Name and Function VSS I Ground: 0V reference VCC I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. P1.0-P1.7 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. P2.0-P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. P3.0-P3.7 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. I RXD (P3.0): Serial input port O TXD (P3.1): Serial output port I INT0 (P3.2): External interrupt 0 I INT1 (P3.3): External interrupt 1 I T0 (P3.4): Timer 0 external input I T1 (P3.5): Timer 1 external input O WR (P3.6): External data memory write strobe O RD (P3.7): External data memory read strobe RST I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC.
4149M –AERO –06/03 ALE O (I) Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations. XTAL1 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 O Crystal 2: Output from the inverting oscillator amplifier Mnemonic Type Name and Function
the clock of the CPU is gated off. Power-down mode stops the oscillator. Table 1. PCON Register Set to select double baud rate in mode 1, 2 or 3. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Cleared by user for General-purpose usage. Set by user for General-purpose usage. Cleared by user for General-purpose usage. Set by user for General-purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.
states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. the instruction that put the device into idle. service routine can examine the flag bits. machine cycles (24 oscillator periods) to complete the reset. Power-down Mode To save maximum power, a power-down mode can be invoked by software. long enough for the oscillator to restart and stabilize. interrupt must be enabled and configured as level or edge sensitive interrupt input. one following the instruction that put 80C32E into power-down mode. Figure 1. Power-down Exit Waveform interrupt does no affect the SFRs.
Table 2. State of Ports During Idle and Power-down Modes
4149M –AERO –06/03 Hardware Refer to the C51 8-bit Microcontroller Hardware description manual for details on 80C32E functionality.
Electrical Characteristics
Absolute Maximum Ratings(2) Ambient Temperature Under Bias. M = Military-55°C to 125°C Notes: 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
- Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC ; EA = RST = VSS (see Figure 4).
- Power-down ICC is measured with all output pins disconnected; EA = VSS , PORT 0 = VCC ; XTAL2 NC.; RST = VSS (see Fig-
- Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL s of ALE and Ports 1
OL peak 0.6V. The use of a Schmitt Trigger is not necessary.
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Table 3. DC Parameters in Standard VoltageTA = -55°C to +125°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 30 MHz.
0.75 VCC
0.9 VCC
AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. Table 4. External Program Memory Characteristics (ns) Figure 7. External Program Memory Read Cycle
30 MHz
12 TCLCL
Table 5. External Data Memory Characteristics (ns) Figure 8. External Data Memory Write Cycle
Figure 9. External Data Memory Read Cycle Table 6. Serial Port Timing – Shift Register Mode (ns) Figure 10. Shift Register Timing Waveforms
Figure 14. Clock Waveforms
4149M –AERO –06/03
Ordering Information
Note: 1. Please contact Atmel for availability. Table 8. Possible Order Entries MC-80C32E-30 30 -55 °C to +125°C Side Brazed 40 pin (.6) Standard Mil. MJ-80C32E-30 30 -55 °C to +125°C MQFPJ 44-pin Standard Mil.
4149M –AERO –06/03 Package Drawings 40-pin Side Braze (600 mils)
4149M –AERO –06/03 44-pin Multilayer Quad Flat Pack
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