5962-0051401V2A

UC1708_08 TI | Alldatasheet

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Logic□Gnd 5.6□V Reg Thermal Shutdown Internal Bias Input A Shutdown Input□B Output A Pwr□Gnd□B Pwr□Gnd A VIN Output□B UC1708 UC2708 UC3708 SLUS171C MARCH 1997 REVISED SEPTEMBER 2007 www.ti.com DUAL NON-INVERTING POWER DRIVER High-Speed, Power MOSFET Compatible 3.0A Peak Current Totem Pole Output Efficient High Frequency Operation to 35V Operation Low Cross-Conduction Current Spike 25ns Rise and Fall Times Enable and Shutdown Functions 25ns Propagation Delays Wide Input Voltage Range Thermal Shutdown and Under-Voltage ESD Protection to 2kV Protection The UC1708 family of power drivers is made with a high-speed, high-voltage, Schottky process to interface control functions and high-power switching devices particularly power MOSFETs. Operating over a V to V supply range, these devices contain two independent channels. The A and B inputs are compatible with TTL and CMOS logic families, but can withstand input voltages as high as V IN Each output can source or sink up to A as long as power dissipation limits are not exceeded. Although each output can be activated independently with its own inputs, they can be forced low in common through the action of either a digital high signal at the Shutdown terminal or by forcing the Enable terminal low. The Shutdown terminal will only force the outputs low, it will not effect the behavior of the rest of the device. The Enable terminal effectively places the device in under-voltage lockout, reducing power consumption by as much as 90%. During under-voltage and disable (Enable terminal forced low) conditions, the outputs are held in a self-biasing, low-voltage, state. The UC3708 and UC2708 are available in plastic 8-pin MINI DIP and 16-pin bat-wing DIP packages for commercial operation over a C to C temperature range and industrial temperature range of C to C respectively. For operation over a C to 125 C temperature range, the UC1708 is available in hermetically sealed 8-pin MINI CDIP, pin CDIP and pin CLCC packages. Surface mount devices are also available. BLOCK DIAGRAM NOTE: Shutdown feature is not available in J or N packages only. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 1997 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com CONNECTION DIAGRAMS Enable Input A Gnd Input□B NC Output A VIN Output□B DIL-8□(Top□View) J□Or□N□Package SOIC-16□(Top□View) DW□Package NC Input A Enable Logic□Gnd NC Shutdown Input□B NC Pwr□Gnd A Output A NC NC V IN Output□□B VIN Pwr□Gnd□B DIL-16□(Top□View) JE□Or□NE□Package NC Input A Enable Logic□Gnd Logic□Gnd Shutdown Input□B NC Pwr□Gnd A Output A V IN Logic□Gnd Logic□Gnd V IN Output□B Pwr□Gnd□B CLCC-20□(Top□View) L Package PWR□GND ANC NCINPUT A OUTPUT A ENABLE LOGIC□GND NC NC SHUTDOWN 9 10 11 12 13 INPUT B NC NC PWR□GND□BOUTPUT B 1920123 VIN NC NC NC V IN Note:□In□JE□package,□Pin□4□is□Logic□Ground. UC1708 UC2708 UC3708 SLUS171C MARCH 1997 REVISED SEPTEMBER 2007 Submit Documentation Feedback Copyright 1997 2007, Texas Instruments Incorporated Product Folder Link(s): UC1708 UC2708 UC3708

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) ELECTRICAL CHARACTERISTICS UC1708 UC2708 UC3708 SLUS171C MARCH 1997 REVISED SEPTEMBER 2007 VALUE UNIT Supply Voltage, V IN V Steady-State 0.5 A Output Current (Each Output, Source or Sink) Peak Transient A Ouput Voltage 0.3 to IN 0.3) V Enable and Shutdown Inputs 0.3 to 6.2 V A and B Inputs 0.3 to IN 0.3) V Operating Junction Temperature (2) 150 C Storage Temperature Range to 150 C Lead Temperature (Soldering, Seconds) 300 C (1) All voltages are with respect to Logic Gnd pin. All currents are positive into, negative out of, device terminals.r (2) Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages. Unless otherwise stated, V IN =10V to 35V, and these specifications apply for: C A <125 C for the UC1708, C A <85 C for the UC2708, and C A <70 C for the UC3708, T A T J PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputs low V IN Supply current Outputs high mA Enable V B and shutdown inputs low level 0.8 V B and shutdown inputs high level 2.0 V B Input current low V A,B 0.4V 0.6 mA B Input current high V A,B 2.4V 200 A B Input leakage current high V A,B 35.3V 200 A Shutdown input current low V SHUTDOWN 0.4V 100 A V SHUTDOWN 2.4V 170 500 A Shutdown input current high V SHUTDOWN 6.2V 0.6 1.5 mA Enable input current low V ENABLE 600 460 200 A Enable input current high V ENABLE 6.2V 200 A Enable threshold rising 2.8 3.6 V Enable threshold falling 1.0 2.4 3.4 V V IN I OUT 50mA 2.0 V Output High Saturation V OUT I OUT 500mA 2.5 V I OUT 50mA 0.5 V V OUT Output Low Saturation I OUT 500mA 2.5 V Thermal Shutdown 155 C Copyright 1997 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1708 UC2708 UC3708

www.ti.com SWITCHING CHARACTERISTICS (see Figure SWITCHING CHARACTERISTICS (see Figure UC1708 UC2708 UC3708 SLUS171C MARCH 1997 REVISED SEPTEMBER 2007 (VIN 20V, delays measured to 10% output change.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FROM A,B INPUT TO OUTPUT: CL 0pF ns UC1708 CL 1000pF ns Rise Time Delay (TPLH) UC2708/UC3708 UC1708 CL 2200pF ns UC2708/UC3708 CL 0pF ns UC1708 CL 1000pF (1) ns 10% to 90% Rise (TTLH) UC2708/UC3708 UC1708 CL 2200pF ns UC2708/UC3708 CL 0pF Fall Time Delay (TPHL) CL 1000pF (1) ns CL 2200pF CL 0pF 90% to 10% Fall (TTHL) CL 1000pF (1) ns CL 2200pF (1) These parameters, specified at 1000pF, although ensured over recommended operating conditions, are not tested in production. (VIN 20V, delays measured to 10% output change.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FROM SHUTDOWN INPUT TO OUTPUT: CL 0pF ns UC1708 CL 1000pF (1) ns Rise Time Delay (TPLH) UC2708/UC3708 UC1708 CL 2200pF ns UC2708/UC3708 CL 0pF ns UC1708 CL 1000pF (1) ns 10% to 90% Rise (TTLH) UC2708/UC3708 UC1708 CL 2200pF ns UC2708/UC3708 CL 0pF Fall Time Delay (TPHL) CL 1000pF (1) ns CL 2200pF CL 0pF 90% to 10% Fall (TTHL) CL 1000pF (1) ns CL 2200pF F 200kHz, 50% duty cycle, both channels; CL 0pF Total Supply Current mA F 200kHz, 50% duty cycle, both channels; CL 2200pF (1) These parameters, specified at 1000pF, although ensured over recommended operating conditions, are not tested in production. Submit Documentation Feedback Copyright 1997 2007, Texas Instruments Incorporated Product Folder Link(s): UC1708 UC2708 UC3708

www.ti.com AC□Input 12□V MPF 6660 50 /c87 LH0063 50 /c87 47 /c87 Input 20□V

10 F/c109 47 F/c109

C L Output 200□kHz tr 0.5□V/RS tf 0.5/RS Duty□Cycle□-□50% /c179 /c179 4.3□V OUTPUT 0□V 20□V INPUT 0□V TPHL TTLH TPLH TTHL 50% 50% 90% 90% 10%10% 5.6□V 8□k/c87 A/B Input Shutdown 500 /c87 10□k/c87 10□k/c87 2.5□pF 5.6□V 5.6□V To A/B Output Enable VIN

450 A/c109

5.6□V Internal Bias Under Voltage Lockout To A/B Output UC1708 UC2708 UC3708 SLUS171C MARCH 1997 REVISED SEPTEMBER 2007 Figure AC Test Circuit and Switching Time Waveforms NOTE: Shutdown feature available only in JE, NE or DW Packages. Figure Equivalent Input Circuits Copyright 1997 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1708 UC2708 UC3708

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-0051401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-0051401QEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 5962-0051401QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type 5962-0051401V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-0051401VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 5962-0051401VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type UC1708J ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type UC1708J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type UC1708JE ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type UC1708JE883B ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type UC1708L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type UC2708D OBSOLETE UTR TBD Call TI Call TI UC2708DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2708DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2708DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2708DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2708J OBSOLETE UTR TBD Call TI Call TI UC2708JE OBSOLETE UTR TBD Call TI Call TI UC2708N ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2708NE ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2708NEG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2708NG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2708Q OBSOLETE UTR TBD Call TI Call TI UC3708DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3708DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3708DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3708DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3708N ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3708NE ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3708NEG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3708NG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2008 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) UC3708Q OBSOLETE UTR TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2008 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2708DWTR SOIC DW 16 2000 346.0 346.0 33.0 UC3708DWTR SOIC DW 16 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 Pack Materials-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

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