57C43C-25

WS57C43C STMICROELECTRONICS | Alldatasheet

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O O 6 A5 A6 A7 VCC A8 A9 NC NC O 0 O 1 O 2 NC O3 O 4 O 5 GND 1432 28 2726 12 13 1415 16 17 18 TOP VIEW Chip Carrier CERDIP/Plastic DIP PIN CONFIGURATION 2-31 HIGH SPEED 4K x 8 CMOS PROM/RPROM KEY FEATURES

• Ultra-Fast Access Time • Pin Compatible with 4K x 8 Bipolar PROMs — tACC = 25 ns • Immune to Latch-UP — tCS = 12 ns — Up to 200 mA
• Low Power Consumption •ESD Protection Exceeds 2000 V
• Fast Programming •Available in 300 Mil DIP and PLDCC GENERAL DESCRIPTION The WS57C43C is a High Performance 32K UV Erasable Electrically Re-Programmable Read O nly Memory (RPROM). It is manufactured in an advanced CMOS technology which enables it to operate at Bipolar PROM speeds while consuming only 25% of the power required by its Bipolar counterparts. A further advantage of the WS57C43C over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology. This enables the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike devices which cannot be erased, every WS5743C in a windowed package is 100% tested with worst case test patterns both before and after assembly. The WS57C43C is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems which are currently using Bipolar PROMs, or its predecessor, the WS57C43B. PRODUCT SELECTION GUIDE PARAMETER 57C43C-25 57C43C-35 57C43C-45 57C43C-55 57C43C-70 Address Access Time (Max) 25 ns 35 ns 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 12 ns 20 ns 25 ns 25 ns 25 ns ROW DECODER EPROM ARRAY 32,768 BITS COLUMN DECODER SENSE AMPLIFIERS 8CS2 OUTPUTS CS1/ VPP A0 - A4 COLUMN ADDRESSES A5 - A11 ROW ADDRESSES BLOCK DIAGRAM Return to Main Menu

DC READ CHARACTERISTICS Over Operating Range. (See Above) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS VIL Input Low Voltage (Note 3) –0.1 0.8 V VIH Input High Voltage (Note 3) 2.0 V CC + 0.3 V VOL Output Low Voltage IOL = 16 mA 0.4 V VOH Output High Voltage IOH = –4 mA 2.4 V VCC = 5.5 V, f = 0 MHz (Note 1),Comm'l 30 mA ICC1 VCC Active Current Output Not Loaded Industrial 35 mA (CMOS) Add 3 mA/MHz for AC OperationMilitary 35 mA VCC = 5.5 V, f = 0 MHz (Note 1),Comm'l 40 mA ICC2 VCC Active Current Output Not Loaded Industrial 50 mA (TTL) Add 3 mA/MHz for AC OperationMilitary 50 mA ILI Input Leakage Current VIN = 5.5V or Gnd –10 10 µA ILO Output Leakage Current VOUT = 5.5 V or Gnd –10 10 µA WS57C43C 2-32 OPERATING RANGE RANGE TEMPERATURE V CC Commercial 0°C to +70°C +5V ± 10% Industrial –40°C to +85°C +5V ± 10% Military –55°C to +125°C +5V ± 10% ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with NOTES: 1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V. 2. TTL inputs: VIL≤ 0.8V, VIH ‡ 2.0V. 3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. *NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. PINS CS1/ CS2 V CC OUTPUTSMODE V PP Read V IL VIH VCC D OUT Output Disable V IH XV CC High Z Output Disable X V IL VCC High Z Program V PP XV CC D IN Program Verify V IL VIH VCC D OUT MODE SELECTION

AC READ CHARACTERISTICS Over Operating Range. (See Above) PARAMETER SYMBOL 57C43C-25 57C43C-35 57C43C-45 57C43C-55 57C43C-70 UNITS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Address to Output Delay tACC 25 35 45 55 70 CS1 to Output Delay t CS 12 20 25 25 25 nsOutput Disable to Output Float* tDF 12 25 25 25 25 Address to Output Hold t OH 00000 *Sampled, Not 100% Tested. AC READ TIMING DIAGRAM VALIDADDRESSES OUTPUTS tACC tOH tCS tDF VALID CS

SYMBOL PARAMETER CONDITIONS TYP (5) MAX UNITS C IN Input Capacitance V IN = 0V 4 6 pF C OUT Output Capacitance V OUT = 0V 8 12 pF C VPP VPP Capacitance V PP = 0 V 18 25 pF CAPACITANCE (4) TA = 25°C, f = 1 MHz 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 98 Ω 2.01 V D.U.T. A.C. TESTING INPUT/OUTPUT WAVEFORMTEST LOAD (High Impedance Test Systems) 3.0 0.0 1.5 1.5 TEST POINTS A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures. NOTES: 4. This parameter is only sampled and is not 100% tested. 5.Typical values are for TA = 25°C and nominal supply voltages. A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 1.5 V for input and output transitions in both directions.

1.2 1.1 1.0 0.9 0.8 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (°C) NORMALIZED I CC 1.60 1.40 1.20 1.00 0.80 0.60 SUPPLY VOLTAGE (V ) NORMALIZED I CC 1.6 1.4 1.2 1.0 0.8 0.6 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (°C) NORMALIZED T aa 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 200 400 600 800 1000 CAPACITANCE (pF ) DELTA T aa (ns) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING NORMALIZED T aa vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE

DC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER MIN MAX UNITS ILI Input Leakage Current –10 10 µA(VIN = VCC or Gnd) IPP VPP Supply Current During 60 mAProgramming Pulse ICC VCC Supply Current 30 mA VOL Output Low Voltage During Verify 0.45 V(IOL = 16 mA) VOH Output High Voltage During Verify 2.4 V(IOH = –4 mA) WS57C43C 2-36 SYMBOLS PARAMETER MIN TYP MAX UNITS tAS Address Setup Time 2 µs tDF Chip Disable Setup Time 30 ns tDS Data Setup Time 2 µs tPW Program Pulse Width 100 200 µs tDH Data Hold Time 2 µs tCS Chip Select Delay 30 ns tRF VPP Rise and Fall Time 1 µs NOTES: 8. VPP must not be greater than 13 volts including overshoot. AC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) PROGRAMMING WAVEFORM ADDRESS STABLEADDRESSES VIH VIL VPP VIH VIH VIL VIL CS1/VPP DATA tAS tDF tDS tPW tDH tCS tRF tRF DATA OUTDATA IN DON'T CARECS2 VIH VIL

ORDERING INFORMATION

PART NUMBER TEMPERATURE MANUFACTURING RANGE PROCEDURE WS57C43C-25D 25 24 Pin CERDIP, 0.6" D1 Comm’l Standard WS57C43C-25J 25 28 Pin PLDCC J3 Comm’l Standard WS57C43C-25S 25 24 Pin Plastic DIP, 0.3" S1 Comm’l Standard WS57C43C-25T 25 24 Pin CERDIP, 0.3" T1 Comm’l Standard WS57C43C-35CMB * 35 28 Pad CLLCC, 0.3" C1 Military MIL-STD-883C WS57C43C-35D 35 24 Pin CERDIP, 0.6" D1 Comm’l Standard WS57C43C-35J 35 28 Pin PLDCC J3 Comm’l Standard WS57C43C-35JI 35 28 Pin PLDCC J3 Industrial Standard WS57C43C-35S 35 24 Pin Plastic DIP, 0.3" S1 Comm’l Standard WS57C43C-35T 35 24 Pin CERDIP, 0.3" T1 Comm’l Standard WS57C43C-35TMB * 35 24 Pin CERDIP, 0.3" T1 Military MIL-STD-883C WS57C43C-45D 45 24 Pin CERDIP, 0.6" D1 Comm’l Standard WS57C43C-45J 45 28 Pin PLDCC J3 Comm’l Standard WS57C43C-45JI 45 28 Pin PLDCC J3 Industrial Standard WS57C43C-45S 45 24 Pin Plastic DIP, 0.3" S1 Comm’l Standard WS57C43C-45T 45 24 Pin CERDIP, 0.3" T1 Comm’l Standard WS57C43C-45TI 45 24 Pin CERDIP, 0.3" T1 Industrial Standard WS57C43C-45TMB * 45 24 Pin CERDIP, 0.3" T1 Military MIL-STD-883C WS57C43C-55D 55 24 Pin CERDIP, 0.6" D1 Comm’l Standard WS57C43C-55T 55 24 Pin CERDIP, 0.3" T1 Comm’l Standard WS57C43C-55TMB * 55 24 Pin CERDIP, 0.3" T1 Military MIL-STD-883C WS57C43C-70D 70 24 Pin CERDIP, 0.6" D1 Comm’l Standard 2-37 SPEED PACKAGE PACKAGE (ns) TYPE DRAWING WS57C43C NOTE: The actual part marking will not include the initials "WS." *SMD product. See section 4 for DESC SMD numbers. PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C43C is programmed using Algorithm D shown on page 5-9. Return to Main Menu