DM54S571 NSC | Alldatasheet
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Technical content
| 7] National = Semiconductor
2 DM54/74S571
O| (512 x 4) 2048-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 | ™ Advanced titanium-tungsten (Ti-W) fuses words by 4 bits configuration. A memory enable input is pro- | ™ Schottky-clamped for high speed vided to control the output states. When the device is en- Address access down to—35 ns max abled, the outputs represent the contents of the selected Enable access—25 ns max word. When disabled, the 4 outputs go to the “OFF” or high Enable recovery—25 ns max impedance state. 1m PNP inputs for reduced input loading PROMs are shipped from the factory with lows in all loca- ™ All DC and AC parameters guaranteed over tempera- tions. A high may be programmed into any selected location ture by following the programming instructions. ® Low voltage TRI-SAFET™ programming = TRI-STATE® outputs Block Diagram
48 Pin Names
is went a [S| output Enabie * [ano | Ground | = PEs i >. 460 - ENABLE BUFFER 03 02 o a0 TUDre713—4 3-50
i=} Connection Diagrams z Dual-In-Line Package Plastic Leaded Chip Carrier (PLCC) g iE . | as—2 15b-a7 g Mas 14 As Mos 18, A8 = A314 136 AS 7G so-45 12/0 roe 16 a0 M6 11if-ar M7 15, NC 47 10--a2 ae 14Fat cnn sto 9 10 111213 Top View TUD/9713-3 Order Number Top View DM54/74S571J, 571Ad, 571BJ Order Number DM74S571N, 571AN, 571BN DM74S571V, 571AV, 571BV See NS Package Number J16A or N16A See NS Package Number V20A
Ordering Information
Commercial Temperature Range (0°C to + 70°C) [—owassrw Sid - |_owrassres Ts | owrassy ts Military Temp. Range (—55°C to + 125°C) a [~owsassrigu SiS [_omssssryy Ts 3-51
r x | Absolute Maximum Ratings (note 1) Operating Conditions | If Military/Aerospace specified devices are required, Min Max Units > please contact the National Semiconductor Sales Supply Voltage (Vcc) f5 | _ Office/Distributors for availability and specifications. Military 4.50 5.50 v Q | Supply Voltage (Note 2) -0.5V to +7.0V Commercial 4.75 5.25 v Fe Input Voltage (Note 2) —1,.2V to +5.5V Ambient Temperature (Ta) B | Output Voltage (Note 2) -0.5V to +5.5V Mita ial = nd 6 65°C to +150" Prorage Tempereiure to 85°C to swe Logical “0” input Voltage ° 08 v ead Temp, (Soldering 10 sec.) Logical “1” Input Voltage 20 55 v ESD to be determined Note 1: Absolute maximum ratings are those values beyond which the de- vice may be permanently damaged. They do not mean that the device may be operated at these values. Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions. DM54S571 OM74S571 Symbol Conditions Units | rene | | min | tye | max | min | typ | Max | in [input toad Curent | voo=Maxvm=oav |_| -e0|-250] | -e0 | -250| pa i) input Leakage Curent | Veo =Maxvw=27v || |e ||. [2s [pa Voc=Maxvn=ssv | | | xo | || 10 | ma Vou__| tow Level Out Vantage | Voo = Min,io.=16ma__| | 08 | 050 | | oa8 | oms |v Vi__[towLevetinputvorage | TT oo | oo |v Vin | Hightevetinputvotage | feo | Teo TT C Input Capacitance Voc = 5.0V, Vin = 2.0V a Ta = 25°C, 1 MHz P Co Output Capacitance Voc = 5.0V, Vo = 2.0V ' Ta = 25°C, 1 MHz, Outputs Off i loc Power Supply Current Voc = Max, Input Grounded mA All Outputs Open los Short Circuit Vo = OV, Voc = Max -70 -70 A Output Current (Note 2) m loz | Output Leakage Voo=MaxVo=oasvozav| | | +50] | | +50 | na low = —65mA | | [ jests2} Jv Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Voc = §.0V and Ta = 28°C. Note 2: During log measurement, only one output at a time should be grounded. Permanent damage may otherwise result 3-52
i=] j = COMMERCIAL TEMP RANGE (0°C to + 70°C) 8 Smee Ei ‘ve x | min | typ | mex | min [ typ [ wax | min | typ | max | 5 Taa__| Tavav | Addressaccesstime | | 40 | 55 | [a0 | as | | a0 [35 | ns | Tex _| tevax | ouputenabietime | | 20 | so [| 16 | as [| as [ 25 | ns txz_| rexaz | oupuvisebietime [| 20 | a0 [ [as | 2s [| ts [as | ns MILITARY TEMP RANGE (—55°C to + 125°C) symbot | JEDEC DMs4s571 DM54S571A DMS54S571B Unit Symbol | min | typ | max | min [typ | mex | min | Tye | max | taa | Tava | AddrossAccesstine | | ao | 65 [| 30 | 60 | | 30 | 50 | as Ten _| Texax | EnabieRecoverytime | | 20 | a5 | [16 [a5 | [1s | 35 | ns txz__| texaz | Oupurbisabiotime | | 20 | as | [is [as [| a5 | 35 | ns Functional Description TESTABILITY TITANIUM-TUNGSTEN FUSES The Schottky PROM dis includes extra rows and columns of National's Programmable Read-Only Memories (PROMs) y fusable links for testing the programmability of each chip. feature titanium-tungsten (Ti-W) fuse links designed to pro- These test fuses are placed at the worst-case chip locations —_gram efficiently with only 10.5V applied. The high perform- to provide the highest possible confidence in the program- ance and reliability of these PROMS are the result of fabrica- ming tests in the final product. A ROM pattern is also per- tion by a Schottky bipolar process, of which the titanium- manently fixed in the additional circuitry and coded to pro- tungsten metallization is an integral part, and the use of an vide a parity check of input address levels. These and other on-chip programming circuit. test circuits are used to test for correct operation of the row a major advantage of the titanium-tungsten fuse technology and column-select circuits and functionality of input and en- ig the low programming voltage of the fuse links. At 10.5V, able gates. All test circuits are available at both wafer and this virtually eliminates the need for guard-ring devices and assembled device levels to allow 100% functional and para- wide spacings required for other fuse technologies. Care is metric testing at every stage of the test flow. taken, however, to minimize voltage drops across the die and to reduce parasitics. The device is designed to ensure RELIABILITY that worst: fu atin t is | hf As with all National products, the Ti-W PROMs are subject. Tint wor cane Tuse operat The Darlington prowracmning ed to an on-going reliability evaluation by the Reliability As- TO/@0!e long-term operation. ton Programming 5 Th Tut 4 forat. _cifCult is liberally designed to insure adequate power density ea ite ane ney evans ormeoy ace ating _{0F blowing the fuse links. The complete circuit design is Fra te fests. Including dynamic high-temperature operating oorimized to provide high performance over the entire oper- life, temperature-humidty life, temperature cycling, and ther- 2.0 anaes of Yoo ard tom perature mal shock. To date, nearly 7.4 million Schottky Ti-W PROM 9 ce device hours have been logged, with samples in Epoxy B molded DIP (N-package), PLCC (V-package) and CERDIP (J-package). Device performance in all package configura- tions is excellent. 3 | 3-53