56F807 MOTOROLA | Alldatasheet
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Technical content
© Motorola, Inc., 2004. All rights reserved.
- Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 6 0 K × 16-bit words Program Flash 2 K × 16-bit words Program RAM 8 K × 16-bit words Data Flash 4 K × 16-bit words Data RAM 2 K × 16-bit words Boot Flash Up to 64K × 16- bit words each of external Program and Data memory Two 6 channel PWM Modules Four 4 channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers J T A G / O n C ETM port for debugging 14 Dedicated and 18 Shared GPIO lines 160-pin LQFP or 160 MAPBGA Packages
Figure 1. 56F807 Block Diagram
6 PWM Outputs
- •
- • EXTBOOTCurrent Sense Inputs3 Quadrature Decoder 0 /Quad Timer CAN 2.0A/B CLKO External Address Bus Switch Bus Control External Data Bus Switch External Bus Interface Unit RD Enable WR Enable DS Select PS Select A[00:05] D[00:15] A[06:15] or GPIO-E2:E3 & GPIO-A0:A7
Freescale Semiconductor, Inc.
1.1 56F807 Features
1.1.1 Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface
1.1.2 Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution — 60K × 16-bit words of Program Flash — 2K × 16-bit words of Program RAM — 8K × 16-bit words of Data Flash — 4K × 16-bit words of Data RAM — 2K × 16-bit words of Boot Flash Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states — As much as 64K × 16 bits of Data memory — As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F807
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized Two Quadrature Decoders each with four inputs or two additional Quad Timers Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins CAN 2.0 B Module with 2-pin port for transmit and receive Two Serial Communication Interfaces each with two pins (or four additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer-Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins External reset input pin for hardware reset External reset output pin for system reset JTAG/On-Chip Emulation (OnCE™ ) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock
1.1.4 Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available 1.2 56F807 Description The 56F807 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F807 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It also supports program execution from external memory. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the analog-to-digital converters. The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and 14 dedicated GPIO lines are also included on the 56F807.
1.3 State of the Art Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the 56F807. Literature Distribution Centers, or online at http://www.motorola.com/semiconductors. Table 1. 56F807 Chip Documentation
1.5 Data Sheet Conventions
“asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
- Values for VIL, VOL , VIH, and VOH are defined by individual product specifications.
Freescale Semiconductor, Inc.
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals present on a pin. Table 2. Functional Group Pin Allocations
Description
Power (VDD or VDDA )1 1 Table 3 Ground (VSS or VSSA )1 3 Table 4 Supply Capacitors & VPP 4 Table 5 PLL and Clock 3 Table 6 Address Bus1 16 Table 7 Data Bus 16 Table 8 Bus Control 4 Table 9 Interrupt and Program Control 5 Table 10 Dedicated General Purpose Input/Output 14 Table 11 Pulse Width Modulator (PWM) Ports 26 Table 12 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins
4 Table 13
- Alternately, Quad Timer pins
8 Table 14
Serial Communications Interface (SCI) Ports1 4 Table 15 CAN Port 2 Table 16 Analog to Digital Converter (ADC) Ports 20 Table 17 Quad Timer Module Ports 6 Table 18 JTAG/On-Chip Emulation (OnCE) 6 Table 19 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 2. 56F807 Signals Identified by Functional Group1
- Alternate pin functionality is shown in parenthesis.
Freescale Semiconductor, Inc.
2.2 Power and Ground Signals
2.3 Clock and Phase Locked Loop Signals
Table 3. Power Inputs
8 VDD Power — These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
3 VDDA Analog Power— These pins is a dedicated power pin for the analog portion
of the chip and should be connected to a low noise 3.3V supply. Table 4. Grounds
9 VSS GND — These pins provide grounding for the internal structures of the chip and
should all be attached to VSS. 3 VSSA Analog Ground— This pin supplies an analog ground.
1 TCS TCS — This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS. Table 5. Supply Capacitors and VPP
2 VPP Input Input VPP — This pin should be left unconnected as an open circuit for
Table 6. PLL and Clock
1 EXTAL Input Input External Crystal Oscillator Input— This input should be
connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5.
1 XTAL Input/
information, please refer to Section 3.5. more information, please refer to Section 3.5.2. Freescale Semiconductor, Inc.
2.4 Address, Data, and Bus Control Signals
CLKOSEL[4:0] bits in CLKOSR. Table 7. Address Bus Signals
6 A0–A5 Output Tri-stated Address Bus— A0–A5 specify the address for external
Program or Data memory accesses.
2 A6 –A7
Program or Data memory accesses. can individually be programmed as input or output pins. After reset, the default state is Address Bus.
8 A8 –A15
Program or Data memory accesses. can be individually programmed as input or output pins. After reset, the default state is Address Bus. Table 8. Data Bus Signals
16 D0 –D15 Input/O
bus is inactive. Internal pullups may be active. Table 6. PLL and Clock (Continued) Freescale Semiconductor, Inc.
2.5 Interrupt and Program Control Signals
Table 9. Bus Control Signals
1 PS Output Tri-stated Program Memory Select— PS is asserted low for external program
1 DS Output Tri-stated Data Memory Select— DS is asserted low for external data
1 WR Output Tri-stated Write Enable— WR is asserted during external memory write
connected directly to the WE pin of a Static RAM. 1 RD Output Tri-stated Read Enable— RD is asserted during external memory read cycles. deasserted high, the external data is latched inside the device. can be connected directly to the OE pin of a Static RAM or ROM. Table 10. Interrupt and Program Control Signals
1 IRQA Input
be level-sensitive or negative-edge-triggered.
1 IRQB Input
1 RSTO Output Output Reset Output— This output reflects the internal reset state of
Freescale Semiconductor, Inc.
2.6 GPIO Signals
2.7 Pulse Width Modulator (PWM) Signals
1 RESET Input
Input Reset— This input is a direct hardware reset on the processor. internal clocks, after a fixed number of internal clocks. module. In this case, assert RESET, but do not assert TRST.
1 EXTBOOT Input
from off-chip memory. Otherwise, it is tied to VSS. Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
8 GPIOB0-G
After reset, the default state is GPIO input.
6 GPIOD0-G
can individually be programmed as an input or output pins. After reset, the default state is GPIO input. Table 12. Pulse Width Modulator (PWMA and PWMB) Signals 6 PWMA0-5 Output Tri- stated PWMA0-5 — Six PWMA output pins.
3 ISA0-2 Input
4 FAULTA0-3 Input
6 PWMB0-5 Output Tri- stated PWMB0-5 — Six PWMB output pins. Table 10. Interrupt and Program Control Signals (Continued) Freescale Semiconductor, Inc.
2.8 Serial Peripheral Interface (SPI) Signals
3 ISB0-2 Input
4 FAULTB0-3 Input
conditions originate off-chip. Table 13. Serial Peripheral Interface (SPI) Signals
1 MISO
state if the slave device is not selected. can individually be programmed as input or output pin. After reset, the default state is MISO.
1 MOSI
the clock edge that the slave device uses to latch the data. can individually be programmed as input or output pin. After reset, the default state is MOSI.
1 SCLK
can individually be programmed as input or output pin. After reset, the default state is SCLK. can individually be programmed as input or output pin. After reset, the default state is SS. Table 12. Pulse Width Modulator (PWMA and PWMB) Signals (Continued) Freescale Semiconductor, Inc.
2.9 Quadrature Decoder Signals
2.10 Serial Communications Interface (SCI) Signals
Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
1 PHASEA0
1 PHASEB0
1 INDEX0
1 HOME0
1 PHASEA1
1 PHASEB1
1 INDEX1
1 HOME1
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals
1 TXD0
that can individually be programmed as input or output pin. After reset, the default state is SCI output. Freescale Semiconductor, Inc.
2.11 CAN Signals
2.12 Analog-to-Digital Converter (ADC) Signals
1 RXD0
that can individually be programmed as input or output pin. After reset, the default state is SCI input.
1 TXD1
that can individually be programmed as input or output pin. After reset, the default state is SCI output.
1 RXD1
that can individually be programmed as input or output pin. After reset, the default state is SCI input. Table 16. CAN Module Signals
1 MSCAN_ RX Input
an internal pull-up resistor. is open-drain output and pull-up resistor is needed. Table 17. Analog to Digital Converter Signals
4 ANA0-3 Input Input ANA0-3 — Analog inputs to ADCA channel 1
4 ANA4-7 Input Input ANA4-7 — Analog inputs to ADCA channel 2
VDDA -0.3V for optimal performance.
4 ANB0-3 Input Input ANB0-3 — Analog inputs to ADCB, channel 1
4 ANB4-7 Input Input ANB4-7 — Analog inputs to ADCB, channel 2
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals (Continued) Freescale Semiconductor, Inc.
2.13 Quad Timer Module Signals
2.14 JTAG/OnCE
3.1 General Characteristics
of 3.3V I/O levels while being able to receive 5V levels without being damaged. Table 18. Quad Timer Module Signals
2 TC0-1 Input/Output Input TC0-1— Timer C Channels 0 and 1
4 TD0-3 Input/Output Input TD0-3— Timer D Channels 0, 1, 2, and 3
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
1 TCK Input
port. The pin is connected internally to a pull-down resistor.
1 TMS Input
edge of TCK and has an on-chip pull-up resistor.
1 TDI Input
of TCK and has an on-chip pull-up resistor.
1 TDO Output Tri-stated Test Data Output— This tri-statable output pin provides a serial
1 TRST Input
required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
1 DE Output Output Debug Event— DE provides a low pulse on recognized debug
Freescale Semiconductor, Inc.
unused inputs are tied to an appropriate voltage level. Table 20. Absolute Maximum Ratings Table 21. Recommended Operating Conditions Freescale Semiconductor, Inc.
- Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
- Junction to ambient thermal resistance, Theta-JA (R θJA) was simulated to be equivalent to the
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
- Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured
values using the cold plate technique with the cold plate temperature used as the “case” temperature.
- Thermal Characterization Parameter, Psi-JT (Ψ JT ), is the “resistance” from junction to reference
estimate junction temperature in steady state customer environments.
- Junction temperature is a function of on-chip power dissipation, package thermal resistance,
components on the board, and board thermal resistance.
- See Section 5.1 from more details on thermal design considerations.
Table 22. Thermal Characteristics6 Freescale Semiconductor, Inc.
3.2 DC Electrical Characteristics
Table 23. DC Electrical Characteristics Freescale Semiconductor, Inc.
- Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3,
- Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
- PWM pin output source current measured with 50% duty cycle.
- PWM pin output sink current measured with 50% duty cycle.
- I DDT = IDD + IDDA (Total supply current for VDD + VDDA )
- Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
- Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no
affects wait IDD ; measured with PLL enabled.
- This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same
V EIO interrupt is generated).
- This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage
will not be generated unless the external power supply drops below the minimum specified value (3.0V).
- Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power
Table 23. DC Electrical Characteristics (Continued) Freescale Semiconductor, Inc.
Figure 3. Maximum Run IDD vs. Frequency (see Note 6. in Table 16)
3.3 AC Electrical Characteristics
table. In Figure 4 the levels of VIH and VIL for an input signal are shown. Figure 4. Input Signal Measurement References Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data V alid state, when a signal level has reached VOL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
3.4 Flash Memory Characteristics
Figure 5. Signal States Table 24. Flash Memory Truth Table
- X address enable, all rows are disabled when XE=0
- Y address enable, YMUX is disabled when YE=0
- Output enable, tri-state Flash data out bus when OE=0
- Defines mass erase cycle, erase whole block
- Defines non-volatile store cycle
Table 25. IFREN Truth Table Freescale Semiconductor, Inc.
Figure 6. Flash Program Cycle Freescale Semiconductor, Inc.
3.5 External Clock Operation
3.5.1 Crystal Oscillator
frequency of operation of the crystal oscillator circuit. Figure 9. Connecting to a Crystal Oscillator
3.5.2 Ceramic Resonator
design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown. Figure 9 no external load capacitors should be used. Freescale Semiconductor, Inc.
Figure 10. Connecting a Ceramic Resonator resonators (which contain an internal bypass capacitor to ground).
3.5.3 External Clock Source
source is connected to XTAL and the EXTAL pin is grounded. Figure 11. Connecting an External Clock Signal Figure 12. External Clock Timing Table 27. External Clock Operation Timing Requirements5
- See Figure 11 for details on using the recommended connection of an external clock driver.
- The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
- Parameters listed are guaranteed by design.
Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
3.5.4 Phase Locked Loop Timing
3.6 External Bus Asynchronous Timing
Table 28. PLL Timing
- An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.2.
- ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter
- This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
Table 29. External Bus Asynchronous Timing1,2 Freescale Semiconductor, Inc.
- Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
- Parameters listed are guaranteed by design.
Figure 13. External Bus Asynchronous Timing Table 29. External Bus Asynchronous Timing1,2 (Continued) Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Freescale Semiconductor, Inc.
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 30. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5
- In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
- Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
- The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
- The interrupt instruction fetch is visible on the pins only in Mode 3.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
Figure 18. Recovery from Stop State Using Asynchronous Interrupt Timing Figure 19. Recovery from Stop State Using IRQA Interrupt Service Figure 20. Reset Output Timing
3.8 Serial Peripheral Interface (SPI) Timing
Table 31. SPI Timing1 Freescale Semiconductor, Inc.
3.9 Quad Timer Timing
3.10 Quadrature Decoder Timing
Table 32. Timer Timing1, 2
- In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.
- Parameters listed are guaranteed by design.
Figure 25. Timer Timing Table 33. Quadrature Decoder Timing1, 2
- In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. VSS = 0V , VDD =
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.11 Serial Communication Interface (SCI) Timing
Table 34. SCI Timing4 Figure 27. RXD Pulse Width Figure 28. TXD Pulse Width Figure 26. Quadrature Decoder Timing
- f MAX is the frequency of operation of the system clock in MHz.
- The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
- The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 35. ADC Characteristics
- For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert
to a digital output code of 0.
- V REF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF
- Measured in 10-90% range.
- LSB = Least Significant Bit.
- Guaranteed by characterization.
Freescale Semiconductor, Inc.
Figure 29. Equivalent Analog Input Circuit
- Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
- Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
- Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
- Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is
3.13 Controller Area Network (CAN) Timing
Table 36. CAN Timing2 Figure 30. Bus Wakeup Detection
- If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any
- Parameters listed are guaranteed by design
Freescale Semiconductor, Inc.
3.14 JTAG Timing
Table 37. JTAG Timing1, 3
- Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation,
- TCK frequency of operation must be less than 1/8 the processor rate.
- Parameters listed are guaranteed by design.
Figure 31. Test Clock Input Timing Diagram Freescale Semiconductor, Inc.
4.1 Package and Pin-Out Information 56F807
case, and Table 39 lists the pinout for the MAPBGA package. Figure 35. Top View, 56F807 160-pin LQFP Package Freescale Semiconductor, Inc.
Figure 36. 160-pin LQFP Mechanical Information
- DIMENSIONS ARE IN MILLIMETERS.
- INTERPRET DIMENSIONS AND TOLERANCES
- DA TUMS A, B, AND D TO BE DETERMINED
- DIMENSIONS D1 AND E1 DO NOT INCLUDE
PROTRUSION IS 0.25mm PER SIDE.
- DIMENSION b DOES NOT INCLUDE DAMBAR
DIMENSION BY MORE THAN 0.08mm.
- EXACT SHAPE OF CORNERS MAY V ARY .
Freescale Semiconductor, Inc.
Table 38. 56F807 LQFP Package Pin Identification by Pin Number
1 A 0 4 1G P I O B 18 1 P W M A 5 1 2 1 D E
2 A 1 4 2G P I O B 28 2 F A U L T A 01 2 2 V SS
3 A2 43 GPIOB3 83 FAULTA1 123 ISA0
4 A3 44 GPIOB4 84 FAULTA2 124 ISA1
5 A4 45 GPIOB5 85 FAULTA3 125 ISA2
6 A 5 4 6G P I O B 68 6 E X T B O O T1 2 6 T D 0
7 A 6 4 7G P I O B 78 7 V SSA 127 TD1
10 A8 50 GPIOD1 90 V SS 130 TC0
11 A9 51 GPIOD2 91 V SS 131 TC1
12 A10 52 GPIOD3 92 XTAL 132 TRST
13 A11 53 GPIOD4 93 EXTAL 133 TCS
14 A12 54 GPIOD5 94 V DD 134 TCK
15 A13 55 TXD1 95 V SS 135 TMS
16 A14 56 RXD1 96 V DD 136 TDI
17 A15 57 PWMB0 97 RSTO 137 TDO
18 V SS 58 PWMB1 98 RESET 138 VCAPC2
19 PS 59 PWMB2 99 VREF 139 MSCAN_TX
20 DS 60 PWMB3 100 V DDA 140 V DD
21 WR 61 PWMB4 101 V SSA 141 V SS
22 RD 62 PWMB5 102 ANA0 142 MSCAN_RX
23 D0 63 V DD 103 ANA1 143 SS
24 D1 64 ISB0 104 ANA2 144 SCLK
25 D2 65 VCAPC1 105 ANA3 145 MISO
26 D3 66 ISB1 106 ANA4 146 MOSI
27 D4 67 ISB2 107 ANA5 147 PHA0
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28 D5 68 VPP2 108 ANA6 148 PHB0
29 D6 69 IRQA 109 ANA7 149 INDX0
30 D7 70 IRQB 110 VREF2 150 HOME0
31 D8 71 FAULTB0 111 V DDA 151 PHA1
32 D9 72 FAULTB1 112 V SSA 152 PHB1
33 D10 73 FAULTB2 113 ANB0 153 V DD
34 V DD 74 FAULTB3 114 ANB1 154 INDX1
35 D11 75 PWMA0 115 ANB2 155 HOME1
36 D12 76 V SS 116 ANB3 156 VPP
37 D13 77 PWMA1 117 ANB4 157 V SS
38 D14 78 PWMA2 118 ANB5 158 CLKO
39 D15 79 PWMA3 119 ANB6 159 TXD0
40 GPIOB0 80 PWMA4 120 ANB7 160 RXD0
Table 38. 56F807 LQFP Package Pin Identification by Pin Number (Continued) Freescale Semiconductor, Inc.
Figure 37. 160 MAPBGA Mechanical Information
- DIMENSIONS ARE IN MILLIMETERS.
TOLERANCES PER ASME Y14.5M, 1994.
- DIMENSION b IS MEASURED A T THE
- DATUM Z (SEA TING PLANE) IS DEFINED BY
- PARALLELISM MEASUREMENT SHALL
Freescale Semiconductor, Inc.
Table 39. 160 MAPBGA Package Pin Identification by Pin Number Freescale Semiconductor, Inc.
Table 39. 160 MAPBGA Package Pin Identification by Pin Number (Continued) Freescale Semiconductor, Inc.
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: Where: TA = ambient temperature °C R θJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: R θJA = package junction-to-ambient thermal resistance °C/W R θJC = package junction-to-case thermal resistance °C/W R θCA = package case-to-ambient thermal resistance °C/W R θJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA . For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. T J T A PD R θJA×()+= R θJA R θJC R θCA+= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation: Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and from the board ground to each VSS pin. The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD /VSS pairs, including VDDA /VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and V SS pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a high-grade capacitor such as a tantalum capacitor. Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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