56F8037

56F8037_07 FREESCALE | Alldatasheet

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16-bit Digital Signal Controllers freescale.com 56F8037 Data Sheet Preliminary Technical Data MC56F8037 Rev. 3

56F8037 Data Sheet, Rev. 3

2 Freescale Semiconductor

Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years).

• I n Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• I n Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-21 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum Rev. 2 In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Rev. 3 • Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Changed the description of the GPIOC4 signal in Table 2-3 (was “...the signal goes to both the ANA0 and CMPAI3”, is “...the signal goes to both ANB0 and CMPB13”). Please see http://www.freescale.com for the most current data sheet revision.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 3 Preliminary 56F8037 Block Diagram DAC or GPIOD Programmable Interval Timer Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller Unified Data / Program RAM 4K x 16 PDB PDB XAB1 XAB2 XDB2 CDBR QSPI0 or PWM or I2C or TMRA or GPIOB IPBus Bridge (IPBB) System Bus Control R/W ControlMemory PAB PAB CDBW CDBR CDBW JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg Low-Voltage Supervisor VCAP VDD VSS VDDA VSSA RESET or GPIOA AD08 Clock Generator* System Integration Module P O R O S C PWM or TMRA or TMRB or CMP or QSPI1 or GPIOA *Includes On-Chip Relaxation Oscillator COP/ Watchdog AD18 Program Memory 32K x 16 Flash ADC or CMP or QSCI1 or GPIOC QSCI0 or PWM or I2C or QSPI1 or TMRA or TMRB or GPIOB I2C or CAN or TMRB or CMP or GPIOB XTAL, CLKIN, or GPIOD EXTAL or GPIOD

• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 8-channel 12-bit Analog-to-Digital Converters (ADCs)
• Two 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• Two Queued Serial Commun ication Interfaces (QSCIs) with LIN slave functionality
• Two Queued Serial Peripheral Interfaces (QSPIs)
• Freescale’s scalable controller area network (MSCAN)

2.0 A/B Module

• Two 16-bit Quad Timers
• One Inter-Integrated Circuit (I 2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-V oltage Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 53 GPIO lines
• 64-pin LQFP Package 56F8037 General Description

56F8037 Data Sheet, Rev. 3

4 Freescale Semiconductor

1.3. Award-Winning Development Environment . 8 Part 2: Signal/Connection Descriptions . . 17 3.7. External Clock Input - Crystal Part 6: System Integration Module (SIM) . . 89 7.2. Flash Access Lock and Part 8: General Purpose Input/Output Part 9: Joint Test Action Group (JTAG) . .136 10.8. Reset, Stop, Wait, Mode Select, 10.9. Serial Peripheral Interface (SPI) Timing . 148 10.11. Queued Serial Communication 10.12. Freescale’s Scalable Controller Area 10.13. Inter-Integrated Circuit Interface 10.15. Analog-to-Digital Converter 10.18. Digital-to-Analog Converter 11.1. 56F8037 Package and 56F8037 Data Sheet Table of Contents

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 5 Preliminary Part 1 Overview 1.1 56F8037 Features

1.1.1 Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Cont roller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Pe r Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stac k with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

1.1.2 Memory

• Dual Harvard architecture permits as many as thre e simultaneous accesses to program and data memory
• Flash security and protection that prevent unauth orized users from gaining access to the internal Flash
• O n - c h i p m e m o r y — 64KB of Program Flash — 8KB of Unified Data/Program RAM
• EEPROM emulation capability using Flash

1.1.3 Peripheral Circuits for 56F8037

• One multi-function six-output Pu lse Width Modulator (PWM) module — Up to 96MHz PWM operating clock — 15 bits of resolution — Center-aligned and Edge-aligned PWM signal mode — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Each complementary PWM signal pair allows selection of a PWM supply source from: –P W M g e n e r a t o r

56F8037 Data Sheet, Rev. 3

6 Freescale Semiconductor

–E x t e r n a l G P I O – Internal timers – Analog comparator outputs – ADC conversion result which compares with valu es of ADC high- and low-limit registers to set PWM output

• Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 8 channel inputs — Supports both simultaneous and sequential conversions — ADC conversions can be synchronized by both PWM and timer modules — Sampling rate up to 2.67MSPS — 16-word result buffer registers
• Two 12-bit Digital-to-A nalog Converters (DACs) — 2 microsecond settling time when output swing from rail to rail — Automatic waveform generation generates sq uare, triangle and sawtooth waveforms with programmable period, update rate, and range
• Two 16-bit multi-purpose Quad Timer modules (TMRs) — Up to 96MHz operating clock — Eight independent 16-bit counter/ timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes
• Two Queued Serial Communication Interfa ces (QSCIs) with LIN Slave functionality — Full-duplex or single-wire operation — Two receiver wake-up methods: – Idle line – Address mark — Four-bytes-deep FIFOs are availabl e on both transmitter and receiver
• Two Queued Serial Peripheral Interfaces (QSPIs) — Full-duplex operation — Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I 2C) port — Operates up to 400kbps — Supports both master and slave operation — Supports both 10-bit address mode and broadcasting mode
• One Freescale scalable controller area network (MSCAN) module

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 7 Preliminary — Fully compliant with CAN protocol - Version 2.0 A/B — Supports standard and extended data frames — Supports data rate up to 1Mbps — Five receive buffers and three transmit buffers

• Three 16-bit Programmable Interval Timers (PITs)
• Two analog Comparators (CMPs) — Selectable input source includes external pins, DACs — Programmable output polarity — Output can drive Timer input, PW M fault input, PWM source, external pin output and trigger ADCs — Output falling and rising edge det ection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog tim er capable of selecting different clock sources
• Up to 53 General-Purpose I/O (G PIO) pins with 5V tolerance
• Integrated Power-On Reset an d Low-V oltage Interrupt Module
• Phase Lock Loop (PLL) to provide high- speed clock to the core and peripherals
• Clock sources: — On-chip relaxation oscillator — External clock: crystal oscillator, cera mic resonator and external clock source
• JTAG/EOnCE debug programming in terface for real-time debugging

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be indivi dually disabled to save power 1.2 56F8037 Description The 56F8037 is a member of the 56800E core-based family of Digital Signal Cont rollers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and comp act program code, the 56F8037 is we ll-suited for many applications. The 56F8037 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inve rters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per inst ruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8037 supports program executio n from internal memories. Two data operands can be accessed

56F8037 Data Sheet, Rev. 3

8 Freescale Semiconductor

from the on-chip data RAM per in struction cycle. The 56F8037 also offers up to 53 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8037 Digital Signal Controll er includes 64KB of Progra m Flash and 8KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peri pherals—PWM, ADCs, QSCIs, QSPIs, I2C, PITs, Quad Timers, DACs and analog comparators—supports vari ous applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

1.3 Award-Winning Development Environment

Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Devel opment Environment is a sophisti cated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) , demonstration board kit and development system cards will s upport concurrent engin eering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Architecture Block Diagram

The 56F8037’s architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6 and 1-7 detail how the device ’s I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please see Part 2, Signal/Connection Descriptions, for information about which signals are multiplexed with those of other peripherals.

1.4.1 PWM, TMR and ADC Connections

Figure 1-3 shows the over- and under-voltage connections from the ADC to the PWM and the connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner to the over- and under-voltage control signals. See the 56F802x and 56F803x Peri pheral Reference Manual for additional information. The PWM_reload_sync output ca n be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1.

Architecture Block Diagram 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 9 Preliminary Figure 1-1 56800E Core Block Diagram Data DSP56800E Core Arithmetic Logic Unit (ALU) XAB2 PAB PDB CDBW CDBR XDB2 Program Memory Data / IPBUS Interface Bit- Manipulation Unit M01 Address XAB1 Generation Unit (AGU) PC LA LA2 HWS0 HWS1 FIRA OMR SR FISR LC LC2 Instruction Decoder Interrupt Unit Looping Unit Program Control Unit ALU1 ALU2 MAC and ALU A1A2 A0 B1B2 B0 C1C2 C0 D1D2 D0 Enhanced JTAG TAP SP N Y Multi-Bit Shifter OnCE™ Program RAM

56F8037 Data Sheet, Rev. 3

10 Freescale Semiconductor

Figure 1-2 Peripheral Subsystem IPBus GPIO A Interrupt Controller To/From IPBus Bridge GPIO B GPIO C OCCS (ROSC / PLL / OSC) POR & LVI SIM GPIO D Low-Voltage Interrupt System POR COP Reset RESET (Muxed with GPIOA7) COP (Continues on Figure 1-3)

Architecture Block Diagram 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 11 Preliminary Figure 1-3 56F8037 I/O Pin-Out Muxing (Part 1/5) To/From IPBus Bridge IPBus

3 DAC SYNC on Figure 1-5

MSTR_CNT_EN MSTR_CNT_EN MSTR_CNT_EN Sync0, Sync1

2 SYNC0, SYNC1 on Figure 1-7

ANA1, 5-7 ANB1, 5-7 ANA4 ANB4 ADC GPIOC1, 9-11 GPIOC5, 13-15 ANA0 ANA0 on Figure 1-5 ANA2 (VREFHA) GPIOC2 ANA3 (VREFLA) GPIOC3 ANB0 ANB0 on Figure 1-5 ANB3 (VREFLB) GPIOC7 ANB2 (VREFHA) GPIOC6 ANA4 on Figure 1-4 ANA1, 5-7 4 ANB4 on Figure 1-4 ANB1, 5-7 4

56F8037 Data Sheet, Rev. 3

12 Freescale Semiconductor

Figure 1-4 56F8037 I/O Pin-Out Muxing (Part 2/5) To/From IPBus Bridge IPBus QSPI1 TMRB GPIOB4 T2, T3 QSCI0 QSPI0 I2C MSCAN QSCI1 TA1-3 on Figure 1-7 SCLK1, MISO1, MOSI1 TB0 on Figure 1-5 TB1 on Figure 1-5 TB2, TB3 on Figure 1-5 TA0 on Figure 1-7 CLKO GPIOA12 - 14 SS1 2RXD0, TXD0 TA2, TA3 on Figure 1-7 MISO0, MOSI0 2 SCLK0, SS0 SCL, SDA 2 TXD1, RXD1 2 ANA4, ANB4 on Figure 1-3 2 CANTX, CANRX GPIOB6 - 7 GPIOB2 - 3 GPIOB0 - 1 GPIOB8 - 9 GPIOB12 - 13 GPIOC8 - 12

Architecture Block Diagram 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 13 Preliminary Figure 1-5 56F8037 I/O Pin-Out Muxing (Part 3/5) To/From IPBus Bridge IPBus GPIOA8 DAC0 TA2 on Figure 1-7 FAULT1 on Figure 1-6 GPIOC0 GPIOD6 GPIOD7 GPIOB11 GPIOA11 GPIOC4 GPIOA9 CMPA CMP_IN1 CMP_IN3 CMP_IN2 Export Import CMPAI1 CMPAI3 CMPAI2 ANA0 on Figure 1-3 TB2 on Figure 1-4 TB0 on Figure 1-4 DAC0 DAC1 DAC1 TA3 on Figure 1-7 FAULT2 on Figure 1-6 CMPBI1 CMPBI3 CMPBI2 TB3 on Figure 1-4 TB1 on Figure 1-4 CMPB CMP_IN2 CMP_IN3 CMP_IN1 ExportImport GPIOB10 GPIOA10 TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 CMP_OUT CMPAO on Figure 1-6, Figure 1-7 ANB0 on Figure 1-3 CMP_OUT CMPBO on Figure 1-6, Figure 1-7

56F8037 Data Sheet, Rev. 3

14 Freescale Semiconductor

Figure 1-6 56F8037 I/O Pin-Out Muxing (Part 4/5) To/From IPBus Bridge IPBus GPIOA6 TA0 on Figure 1-7 TA2 - 3 on Figure 1-7 GPIOA0 - 3 PWM PWM0 - 3 FAULT0 PWMA4 - 5 FAULT1 RELOAD PSRC0 - 2 GPIOA4 - 5 FAULT2 FAULT3 RELOAD on Figure 1-7, Figure 1-5 FAULT1 on Figure 1-5 GPIOB5 TA1 on Figure 1-7 GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3 CMPAO on Figure 1-5 CMPBO on Figure 1-5 FAULT2 on Figure 1-5 CMPAO on Figure 1-5 CMPBO on Figure 1-5

Architecture Block Diagram 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 15 Preliminary Figure 1-7 56F8037 I/O Pin-Out Muxing (Part 5/5) To/From IPBus Bridge IPBus TMRA T0o T0i T1o T1i T2o T2i T3o T3i TA0o on Figure 1-6 (PWM) TA0 on Figure 1-6 (GPIOA6) TA0 on Figure 1-4 (GPIOB4) TA1 on Figure 1-4(GPIOA12) TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) TA2 on Figure 1-5 (GPIOA8) TA2 on Figure 1-4 (GPIOA13) TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) TA3 on Figure 1-5 (GPIOA9) TA3 on Figure 1-4 (GPIOA14) TA 3 on Figure 1-4 (GPIOB3) RELOAD on Figure 1-6 (PWM)

56F8037 Data Sheet, Rev. 3

16 Freescale Semiconductor

1.5 Product Documentation

The documents listed in Table 1-1 are required for a complete description and proper design with the 56F8037. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribut ion Centers, or online at: http://www.freescale.com Table 1-1 56F8037 Chip Documentation

1.6 Data Sheet Conventions

This data sheet uses the following conventions: Topic Description Order Number DSP56800E Reference Manual Detailed description of the 56800E family architecture, 16-bit Digital Signal Controller core processor, and the instruction set DSP56800ERM 56F802x and 56F803x Peripheral Reference Manual Detailed description of peripherals of the 56F802x and 56F803x family of devices MC56F80xxRM 56F802x and 56F803x Serial Bootloader User Guide Detailed description of the Serial Bootloader in the 56F802x and 56F803x family of devices 56F80xxBLUG 56F8037 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) MC56F8037 56F8037 Errata Details any chip issues that might be present MC56F8037E OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is hi gh or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage 1. Values for V IL, VOL, VIH, and VOH are defined by individual product specifications. PIN True Asserted V IL/VOL PIN False Deasserted V IH/VOH PIN True Asserted V IH/VOH PIN False Deasserted V IL/VOL

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 17 Preliminary Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8037 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Power Inputs (VDD, VDDA)4 Ground (VSS, VSSA)5 Supply Capacitors 2 Reset1 1. Pins may be shared with other peripherals. See Table 2-2. Pulse Width Modulator (PWM) Ports1 13 Queued Serial Peripheral Interface 0 (QSPI0) Ports1 4 Queued Serial Peripheral Interface 1 (QSPI1) Ports1 4 Timer Module A (TMRA) Ports1 4 Timer Module B (TMRB) Ports1 4 Analog-to-Digital Converter (ADC) Ports1 16 Digital-to-Analog Converter (DAC) Ports1 2 Queued Serial Communications Interface 0 (QSCI0) Ports1 2 Queued Serial Communications Interface 1 (QSCI1) Ports1 2 Inter-Integrated Circuit Interface (I2C) Ports1 2 MSCAN Ports1 2 Oscillator Signals1 2 JTAG/Enhanced On-Chip Emulation (EOnCE)1 4

56F8037 Data Sheet, Rev. 3

18 Freescale Semiconductor

In Table 2-2, peripheral pins in bold identify reset state. Table 2-2 56F8037 Pins Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground JTAG Misc.

1 GPIOB6 GPIOB6, RXD0, SDA,

2 GPIOB1 GPIOB1, SS0, SDA B1 SDA SS 0

3 GPIOB7 GPIOB7, TXD0, SCL B7 SCL TXD0

4 GPIOB5 GPIOB5, TA1,

FAULT3, CLKIN B5 FAULT3 TA1 CLKIN

5 GPIOA9 GPIOA9, FAULT2,

TA3, CMPBI1 A9 FAULT2 TA3 CMPBI1

6 GPIOA11 GPIOA11, TB3,

7 VDD VDD VDD

8 VSS VSS VSS

9 GPIOC12 GPIOC12, ANB4,

10 GPIOC4 GPIOC4, ANB0,

11 GPIOC5 GPIOC5, ANB1 C5 ANB1

12 GPIOC13 GPIOC13, ANB5 C13 ANB5

13 GPIOC6 ANB2, VREFHB C6 ANB2

14 GPIOC7 GPIOC7, ANB3,

15 GPIOD7 GPIOD7, DAC1 D7 DAC1

16 VDDA VDDA VDDA

17 VSSA VSSA VSSA

18 GPIOD6 GPIOD6, DAC0 D6 DAC0

19 GPIOC3 GPIOC3, ANA3,

20 GPIOC2 GPIOC2, ANA2,

21 GPIOC9 GPIOC9, ANA5 C9 ANA5

22 GPIOC1 GPIOC1, ANA1 C1 ANA1

23 GPIOC10 GPIOC10, ANA6 C10 ANA6

24 GPIOC0 GPIOC0, ANA0,

25 GPIOC11 GPIOC11, ANA7 C11 ANA7

26 GPIOC8 GPIOC8, ANA4, TXD1 C8 TXD1 ANA4

27 VSS VSS VSS

28 VCAP VCAP VCAP

29 TCK TCK, GPIOD2 D2 TCK

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 19 Preliminary

30 GPIOB10 GPIOB10, CMPAO,

31 RESET RESET, GPIOA7 A7 RESET

32 GPIOB3 GPIOB3, MOSI0, TA3,

33 GPIOB2 GPIOB2, MISO0, TA2,

34 GPIOA6 GPIOA6, FAULT0,

35 GPIOA10 GPIOA10, TB2,

36 GPIOA8 GPIOA8, FAULT1,

TA2, CMPAI1 A8 FAULT1 TA2 CMPAI1

37 GPIOA12 GPIOA12, TB1,

SCLK1, TA1 A12 SCLK1 TB1 TA1

38 GPIOB4 GPIOB4, SS1, TB0,

TA0, PSRC2, CLKO B4 SS1 PSRC2 TA0 TB0 CLKO

39 GPIOA5 GPIOA5, PWM5, TA3,

40 VSS VSS VSS

41 VDD VDD VDD

42 GPIOB0 GPIOB0, SCLK0, SCL B0 SCL SCLK0

43 GPIOA4 GPIOA4, PWM4, TA2,

44 GPIOA13 GPIOA13, TB2,

MISO1, TA2 A13 MISO1 TB2 TA2

45 GPIOA14 GPIOA14, TB3,

MOSI1, TA3 A14 MOSI1 TB3 TA3

46 GPIOB9 GPIOB9, SDA,

47 GPIOA2 GPIOA2, PWM2 A2 PWM2

48 GPIOA3 GPIOA3, PWM3 A3 PWM3

49 VCAP VCAP VCAP

50 VDD VDD VDD

51 VSS VSS VSS

52 GPIOD5 GPIOD5, XTAL, CLKIN D5 XTAL

53 GPIOD4 GPIOD4, EXTAL D4 EXTAL

54 GPIOB8 GPIOB8, SCL, CANTX B8 SCL CANTX

55 GPIOA1 GPIOA1, PWM1 A1 PWM1

56 GPIOA0 GPIOA0, PWM0 A0 PWM0

57 GPIOB12 GPIOB12, CANTX B12 CANTX

Table 2-2 56F8037 Pins (Continued) Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground JTAG Misc.

56F8037 Data Sheet, Rev. 3

20 Freescale Semiconductor

58 GPIOB13 GPIOB13, CANRX B13 CANRX

59 TDI TDI, GPIOD0 D0 TD1

60 GPIOB11 GPIOB11, CMPBO,

61 GPIOC15 GPIOC15, ANB7 C15 ANB7

62 GPIOC14 GPIOC14, ANB6 C14 ANB6

63 TMS TMS, GPIOD3 D3 TMS

64 TDO TDO, GPIOD1 D1 TDO

Table 2-2 56F8037 Pins (Continued) Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground JTAG Misc.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 21 Preliminary Figure 2-1 56F8037 Signals Identified by Functional Group VDD VDDA VSSA GPIOD5 (XTAL, CLKIN) GPIOD4 (EXTAL) Other Supply Ports OSC Port or GPIO JTAG/ EOnCE or GPIOD VCAP TCK (GPIOD2) TMS (GPIOD3) GPIOC2 (ANA2, VREFHA) 56F8037 TDI (GPIOD0) TDO (GPIOD1) GPIOB5 (TA1, FAULT3, CLKIN) GPIOB6 (RXD0, SDA, CLKIN) GPIOB7 (TXD0, SCL) VSS Power Ground Power Ground GPIOC1 (ANA1) GPIOC0 (ANA0 & CMPAI3) GPIOC3 (ANA3, VREFLA) GPIOC8 (ANA4, TXD1) RESET or GPIOA RESET (GPIOA7) GPIOB0 (SCLK0, SCL) GPIOB1 (SS0, SDA) QSPI0 or I2C or PWM or TMRA or GPIOB QSCI0 or PWM or I2C or TMRA or TMRB or QSPI1 or GPIOB ADC or CMP or QSCI1 or GPIOC GPIOB2 (MISO0, TA2, PSRC0) GPIOB3 (MOSI0, TA3, PSRC1) GPIOA9 (FAULT2, TA3, CMPBI1) GPIOA0-3 (PWM0-3) GPIOA4 (PWM4, TA2, FAULT1) GPIOA5 (PWM5, TA3, FAULT2) GPIOA8 (FAULT1, TA2, CMPAI1) GPIOA6 (FAULT0, TA0) GPIOA10 (TB2, CMPAI2) GPIOA11 (TB3, CMPBI2) PWM or TMRA or TMRB or CMP or QSPI1 or GPIOA GPIOB10 (TB0, CMPAO) GPIOB9 (SDA, CANRX) GPIOB8 (SCL, CANTX) GPIOB11 (TB1, CMPBO) I2C or CAN or TMRB or CMP or GPIOB GPIOC6 (ANB2, VREFHB) GPIOC5 (ANB1) GPIOC4 (ANB0 & CMPBI3) GPIOC7 (ANB3, VREFLB) GPIOC12 (ANB4, RXD1) GPIOB4 (SS1, TB0, TA0, PSRC2, CLKO) DAC or GPIOD GPIOD6-7 (DAC0-1) GPIOA12 (SCLK1, TB1, TA1) GPIOA13 (MISO1, TB2, TA2) GPIOA14 (MOSI1, TB3, TA3) GPIOB12 (CANTX) GPIOB13 (CANRX) GPIOC9-11 (ANA5-7) GPIOC13-15 (ANA5-7)

56F8037 Data Sheet, Rev. 3

22 Freescale Semiconductor

2.2 56F8037 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 7 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 41 VDD 50 VSS 8 Supply Supply VSS — These pins provide ground fo r chip logic and I/O drivers. VSS 27 VSS 40 VSS 51 VDDA 16 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. VSSA 17 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules. VCAP 28 Supply Supply VCAP — Connect this pin to a 4.7μF or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. See Section 10.2.1.VCAP 49 RESET (GPIOA7)

31 Input

Input, internal pull-up enabled Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the chip is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. Return to Table 2-2

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 23 Preliminary GPIOA0 (PWM0)

56 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. GPIOA1 (PWM1)

55 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM1 — This is one of the six PWM output pins. After reset, the default state is GPIOA1. GPIOA2 (PWM2)

47 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM2 — This is one of the six PWM output pins. After reset, the default state is GPIOA2. GPIOA3 (PWM3)

48 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM3 — This is one of the six PWM output pins. After reset, the default state is GPIOA3. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

24 Freescale Semiconductor

(PWM4) (TA21) (FAULT12)

43 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM4 — This is one of the six PWM output pins. TA2 — Timer A, Channel 2 Fault1 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA4. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 1The TA2 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins. 2The Fault1 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins. GPIOA5 (PWM5) (TA33) (FAULT24)

39 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM5 — This is one of the six PWM output pins. TA3 — Timer A, Channel 3 Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 3The TA3 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins. 4The Fault2 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 25 Preliminary GPIOA6 (FAULT0) (TA05)

34 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 — Timer A, Channel 0. After reset, the default state is GPIOA6. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 5The TA0 signal is also brought out on the GPIOB4 pin. GPIOA8 (FAULT1) (TA2) (CMPAI1)

36 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault1 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 — Timer A, Channel 2. Comparator A, Input 1 — This is an analog input to Comparator A. After reset, the default state is GPIOA8. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOA9 (FAULT2) (TA3) (CMPBI1)

5 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 — Timer A, Channel 3. Comparator B, Input 1 — This is an analog input to Comparator B. After reset, the default state is GPIOA9. The peripheral functionality is controlled via the SIM. See Section 6.3.16. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

26 Freescale Semiconductor

(TB26) (CMPAI2)

35 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. TB2 — Timer B, Channel 2. Comparator A, Input 2 — This is an analog input to Comparator A. After reset, the default state is GPIOA10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 6The TB2 signal is also brought out on the GPIOA13 pin. GPIOA11 (TB37) (CMPBI2)

6 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. TB3 — Timer B, Channel 3. Comparator B, Input 2 — This is an analog input to Comparator B. After reset, the default state is GPIOA11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 7The TB3 signal is also brought out on the GPIOA14 pin. GPIOA12 (SCLK1) (TB18) (TA19)

37 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. TB1 — Timer B, Channel 1. TA1 — Timer A, Channel 1. After reset, the default state is GPIOA12. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 8The TB1 signal is also brought out on the GPIOB11 pin. 9The TA1 signal is also brought out on the GPIOB5 pin. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 27 Preliminary GPIOA13 (MISO1) (TB210) (TA211)

44 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI1 Master In/Slave Out— This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master devices uses to latch the data. TB2 — Timer B, Channel 2. TA2 — Timer A, Channel 2. After reset, the default state is GPIOA13. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 10The TB2 signal is also brought out on the GPIOA10 pin. 11The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOB2 pins. GPIOA14 (MOSI1) (TB312) (TA313)

45 Input/

Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI1 MasterOut/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave devices uses to latch the data. TB3 — Timer B, Channel 3. TA3 — Timer A, Channel 3. After reset, the default state is GPIOA14. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 12The TB3 signal is also brought out on the GPIOA11 pin. 13The TA3 signal is also brought out on the GPIOA5, GPIOA9, and GPIOB3 pins. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

28 Freescale Semiconductor

(SCLK0) (SCL14)

42 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Serial Clock — This pin serves as the I 2C serial clock. After reset, the default state is GPIOB0. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 14The SCL signal is also brought out on the GPIOB7 and GPIOB8 pins. GPIOB1 (SS0) (SDA15)

2 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI0 Slave Select — SS is used in slave mode to indicate to the QSPI0 module that the current transfer is to be received. Serial Data — This pin serves as the I 2C serial data line. After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 15The SDA signal is also brought out on the GPIOB6 and GPIOB9 pins. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 29 Preliminary GPIOB2 (MISO0) (TA216) (PSRC0)

33 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. TA2 — Timer A, Channel 2 PSRC0 — External PWM signal source input for the complementary PWM4/PWM5 pair. After reset, the default state is GPIOB2. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 16The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOA13 pins. GPIOB3 (MOSI0) (TA317) (PSRC1)

32 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI0 Master Out/Slave In— This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. TA3 — Timer A, Channel 3 PSRC1 — External PWM signal source input for the complementary PWM2/PWM3 pair. After reset, the default state is GPIOB3. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 17The TA3 signal is also brought out on the GPIOA5, GPIOA9 and GPIOA14 pins. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

30 Freescale Semiconductor

(SS1) (TB018) (TA019) (PSRC2) (CLKO)

38 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI1 Slave Select — This is used in slave mode to indicate to the QSPI1 module that the current transfer is to be received. TB0 — Timer B, Channel 0 TA0 — Timer A, Channel 0 PSRC2 — External PWM signal source input for the complementary PWM0/PWM1 pair. Clock Output — This is a buffered clock out put; the clock source is selected by Clockout Select (CLKOSEL) bits in the Clock Output Select Register (CLKOUT). See Section 6.3.7. After reset, the default state is GPIOB4. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 18The TB0 signal is also brought out on the GPIOB4 and GPIOB10 pins. 19The TA0 signal is also brought out on the GPIOB4 and GPIOA6 pins. GPIOB5 (TA120) (FAULT3) (CLKIN)

4 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TA1 — Timer A, Channel 1 FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. External Clock Input— This pin serves as an external clock input. After reset, the default state is GPIOB5. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 20The TA1 signal is also brought out on the GPIOA12 pin. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 31 Preliminary GPIOB6 (RXD0) (SDA21) (CLKIN)

1 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Receive Data 0 — QSCI0 receive data input. Serial Data — This pin serves as the I 2C serial data line. External Clock Input — This pin serves as an optional external clock input. After reset, the default state is GPIOB6. The peripheral functionality is controlled via the SIM (See Section 6.3.16) and the CLKMODE bit of the OCCS Oscillator Control Register. 21The SDA signal is also brought out on the GPIOB1 and GPIOB9 pins. GPIOB7 (TXD0) (SCL22)

3 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Transmit Data 0 — QSCI0 transmit data output or transmit / receive in single wire operation. Serial Clock — This pin serves as the I 2C serial clock. After reset, the default state is GPIOB7. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 22The SCL signal is also brought out on the GPIOB0 and GPIOB8 pins. GPIOB8 (SCL23) (CANTX24)

54 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Clock 1 — This pin serves as the I 2C serial clock. CAN Transmit Data — This is the SCAN interface output. After reset, the default state is GPIOB8. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 23The SCL signal is also brought out on the GPIOB0 and GPIOB7 pins. 24The CANTX signal is also brought out on the GPIOB12 pin. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

32 Freescale Semiconductor

(SDA25) (CANRX26)

46 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Data 1 — This pin serves as the I 2C serial data line. CAN Receive Data — This is the MSCAN interface input. After reset, the default state is GPIOB9. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 25The SDA signal is also brought out on the GPIOB1 and GPIOB6 pins. 26The CANRX signal is also brought out on the GPIOB13 pin. GPIOB10 (TB027) (CMPAO)

30 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TB0— Timer B, Channel 0. Comparator A Output— This is the output of comparator A. After reset, the default state is GPIOB10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 27The TB0 signal is also brought out on the GPIOB4 pin. GPIOB11 (TB128) (CMPBO)

60 Input/

Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TB1— Timer B, Channel 1. Comparator B Output— This is the output of comparator B. After reset, the default state is GPIOB11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 28The TB1 signal is also brought out on the GPIOA12 pin. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 33 Preliminary GPIOB12 (CANTX29)

57 Input/

Input Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Transmit Data — This is the MSCAN interface output. After reset, the default state is GPIOB12. 29The CANTX signal is also brought out on the GPIOB8 pin. GPIOB13 (CANRX30)

58 Input/

Input Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Receive Data — This is the MSCAN interface input. After reset, the default state is GPIOB13. 30The CANRX signal is also brought out on the GPIOB9 pin. GPIOC0 (ANA0 & CMPAI3)

24 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA0 — Analog input to ADC A, Channel 0. Comparator A, Input 3 — This is an analog input to Comparator A. When used as an analog input, the signal goes to both ANA0 and CMPAI3. After reset, the default state is GPIOC0. GPIOC1 (ANA1)

22 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA1 — Analog input to ADC A, Channel 1. After reset, the default state is GPIOC1. GPIOC2 (ANA2) (VREFHA)

20 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA2 — Analog input to ADC A, Channel 2. VREFHA — Analog reference voltage high (ADC A). After reset, the default state is GPIOC2. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

34 Freescale Semiconductor

(ANA3) (VREFLA)

19 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA3 — Analog input to ADC A, Channel 3. VREFLA — Analog reference voltage low. (ADC A). After reset, the default state is GPIOC3. GPIOC4 (ANB0 & CMPBI3)

10 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0 — Analog input to ADC B, Channel 0. Comparator B, Input 3 — This is an analog input to Comparator B. When used an analog input, the signal goes to both ANB0 and CMPB13. After reset, the default state is GPIOC4. GPIOC5 (ANB1)

11 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB1 — Analog input to ADC B, Channel 1. After reset, the default state is GPIOC5. GPIOC6 (ANB2) (VREFHB)

13 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2 — Analog input to ADC B, Channel 2. VREFHx — Analog reference voltage high (ADC B). After reset, the default state is GPIOC6. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 35 Preliminary GPIOC7 (ANB3) (VREFLB)

14 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. VREFLB — Analog reference voltage low (ADC B). After reset, the default state is GPIOC7. GPIOC8 (ANA4) (TXD1)

26 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA4 — Analog input to ADC A, Channel 4. Transmit Data 1 — SCI1 transmit data output. After reset, the default state is GPIOC8. GPIOC9 (ANA5)

21 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA5 — Analog input to ADC A, Channel 5. After reset, the default state is GPIOC9. GPIOC10 (ANA6)

23 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA6 — Analog input to ADC A, Channel 6. After reset, the default state is GPIOC10. GPIOC11 (ANA7)

25 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA7 — Analog input to ADC A, Channel 7. After reset, the default state is GPIOC11. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

36 Freescale Semiconductor

(ANB4) (RXD1)

9 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB4 — Analog input to ADC B, Channel 4. Receive Data 1 — SCI1 receive data input. After reset, the default state is GPIOC12. GPIOC13 (ANB5)

12 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB5 — Analog input to ADC B, Channel 5. After reset, the default state is GPIOC13. GPIOC14 (ANB6)

62 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB6 — Analog input to ADC B, Channel 6. After reset, the default state is GPIOC14. GPIOC15 (ANB7)

61 Input/

Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB7 — Analog input to ADC B, Channel 7. After reset, the default state is GPIOC15. GPIOD4 (EXTAL)

53 Input/

Input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is being driven by an external clock source. After reset, the default state is GPIOD4. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 37 Preliminary GPIOD5 (XTAL) (CLKIN)

52 Input/

Input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. External Clock Input — This pin serves as an external clock input. After reset, the default state is GPIOD5. GPIOD6 (DAC0)

18 Input/

Input, internal pull-up enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. DAC0— Digital-to-Analog Converter output 0. After reset, the default state is GPIOD6. GPIOD7 (DAC1)

15 Input/

Input, internal pull-up enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. DAC1— Digital-to-Analog Converter output 1. After reset, the default state is GPIOD7. TDI (GPIOD0)

59 Input

Input, internal pull-up enabled Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. TDO (GPIOD1)

64 Output

tri-stated, internal pull-up enabled Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

56F8037 Data Sheet, Rev. 3

38 Freescale Semiconductor

3.1 Overview

The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 fami ly devices at user-sel ectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual. TCK (GPIOD2)

29 Input

Input, internal pull-up enabled Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. TMS (GPIOD3)

63 Input

Input, internal pull-up enabled Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to VDD through a 2.2K resistor. Return to Table 2-2 Table 2-3 56F8037 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset Signal Description

Features

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 39 Preliminary

3.2 Features

The OCCS module interfaces to the oscillator and PLL and offers these features:

• Internal relaxation oscillator
• Ability to power down the internal rela xation oscillator or crystal oscillator
• Ability to put the internal rela xation oscillator into Standby mode
• 3-bit postscaler provides control for the PLL output
• Ability to power down the PLL
• Provides a 2X system clock which operates at twice the system clock to the System Integration Module (SIM)
• Provides a 3X system clock which operates at thr ee times the system clock to PWM and Timer modules
• Safety shutdown feature is availabl e if the PLL reference clock is lost
• Can be driven from an external clock source The clock generation module provid es the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator.

3.3 Operating Modes

In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be used to provide a reference clock to the SIM. The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency x 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. The 56F8000 family devices’ on-chip clock synthesis module has the following registers:

• Control Register (OCCS_CTRL)
• Divide-by Register (OCCS_DIVBY)
• Status Register (OCCS_STAT)
• Shutdown Register (OCCS_SHUTDN)
• Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference Manual.

56F8037 Data Sheet, Rev. 3

40 Freescale Semiconductor

3.4 Internal Clock Source

An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations which accommodate different operating conditions. The in ternal relaxation oscillator has very little temperature and voltage variability. To optimize power, the architecture supports a standby state and a power-down state. During a boot or reset sequence, the relaxation oscill ator is enabled by defaul t (the PRECS bit in the PLLCR word is set to 0). Application code can then also switch to the extern al clock source and power down the internal oscillator, if de sired. If a changeover be tween internal and exte rnal clock sources is required at power-on, the user must ensure that the clock source is not switched until the desired external clock source is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (tri m) to this preset value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved. The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the 56F802x and 56F803x Peripheral Reference Manual.

3.5 Crystal Oscillator

The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provid e maximum stability and re liable start-up. The load capacitance values used in the oscillator circuit de sign should include all stra y layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 41 Preliminary Figure 3-1 External Crystal Oscillator Circuit

3.6 Ceramic Resonator

The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz. Figure 3-2 shows the typical 2 and 3 terminal ce ramic resonators and their circuits. Follow the resonator supplier ’s recommendations when selecting a resonator, since their parameters determine the component values required to provide maximum stability and re liable start up. The load capacitance values used in the re sonator circuit design should includ e all stray layout capacitances. The resonator and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Figure 3-2 External Ceramic Resonator Circuit

3.7 External Clock Input - Crystal Oscillator Option

The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver. Sample External Crystal Parameters: Rz = 750 KΩ Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg Ω EXTAL XTAL Rz CL1 CL2 Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 KΩ EXTAL XTAL Rz CL1 CL2 Resonator Frequency = 4 - 8MHz (optimized for 8MHz)

3 Terminal2 Terminal

56F8037 Data Sheet, Rev. 3

42 Freescale Semiconductor

Figure 3-3 Connecting an External Clock Signal using XTAL

3.8 Alternate External Clock Input

The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/ RXD (primary) or GPIOB5/TA1 /FAULT3/XTAL/EXTAL (secondary). The user has the option of us ing GPIO6/RXD/CLKIN or GPIOB5 /TA1/FAULT3/CLKIN as external clock input. Figure 3-4 Connecting an External Clock Signal using GPIO Part 4 Memory Maps

4.1 Introduction

The 56F8037 device is a 16-bit motor-control chip ba sed on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both spaces and Flash memory is used only in Program space. This section provides memory maps for:

• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. 56F8037 External Clock XTAL EXTAL GND or GPIO CLKMODE = 1 56F8037 GPIO External Clock

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 43 Preliminary

4.2 Interrupt Vector Table

Table 4-2 provides the 56F8037’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with hi gher-priority vectors at the top and lowe r-priority interrupts lower in the table. As indicated, the priority of an in terrupt can be assigned to different levels, allo wing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8 for the reset value of the VBA. By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Table 4-1 Chip Memory Configurations On-Chip Memory 56F8037 Use Restrictions Program Flash (PFLASH) 32k x 16 or 64KB Erase / Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4k x 16 or 8KB Usable by both the Program and Data memory spaces Table 4-2 Interrupt Vector Table Contents1 Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function core P:$00 Reserved for Reset Overlay2 core P:$02 Reserved for COP Reset Overlay core 2 3 P:$04 Illegal Instruction core 3 3 P:$06 SW Interrupt 3 core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C EOnCE Step Counter core 7 1-3 P:$0E EOnCE Breakpoint Unit core 8 1-3 P:$10 EOnCE Trace Buffer core 9 1-3 P:$12 EOnCE Transmit Register Empty core 10 1-3 P:$14 EOnCE Receive Register Full core 11 2 P:$16 SW Interrupt 2 core 12 1 P:$18 SW Interrupt 1 core 13 0 P:$1A SW Interrupt 0

56F8037 Data Sheet, Rev. 3

44 Freescale Semiconductor

14 Reserved

LVI 15 1-3 P:$1E Low-Voltage Detector (Power Sense) PLL 16 1-3 P:$20 Phase-Locked Loop FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data , and Address Buffers Empty MSCAN 20 0-2 P:$28 MSCAN Error MSCAN 21 0-2 P:$2a MSCAN Receive MSCAN 22 0-2 P:$2C MSCAN Transmit MSCAN 23 0-2 P:$2E MSCAN Wake-Up GPIOD 24 0-2 P:$30 GPIOD GPIOC 25 0-2 P:$32 GPIOC GPIOB 26 0-2 P:$34 GPIOB GPIOA 27 0-2 P:$36 GPIOA QSPI0 28 0-2 P:$38 QSPI 0 Receiver Full QSPI0 29 0-2 P:$3A QSPI0 Transmitter Empty QSPI1 30 0-2 P:$3C QSPI 1 Receiver Full QSPI1 31 0-2 P:$3E QSPI1 Transmitter Empty QSCI0 32 0-2 P:$40 QSCI0 Transmitter Empty QSCI0 33 0-2 P:$42 QSCI0 Transmitter Idle QSCI0 34 0-2 P:$44 QSCI0 Receiver Error QSCI0 35 0-2 P:$46 QSCI0 Receiver Full QSCI1 36 0-2 P:$48 QSCI1 Transmitter Empty QSCI1 37 0-2 P:$4A QSCI1 Transmitter Idle QSCI1 38 0-2 P:$4C QSCI1 Receiver Error QSCI1 39 0-2 P:$4E QSCI1 Receiver Full I2C 40 0-2 P:$50 I 2C Error I2C 41 0-2 P:$52 I2C General I2C 42 0-2 P:$54 I2C Receive I2C 43 0-2 P:$56 I2C Transmit I2C 44 0-2 P:$58 I2C Status TMRA 45 0-2 P:$5A Timer A, Channel 0 TMRA 46 0-2 P:$5C Timer A, Channel 1 TMRA 47 0-2 P:$5E Timer A, Channel 2 TMRA 48 0-2 P:$60 Timer A, Channel 3 TMRB 49 0-2 P:$62 Timer B, Channel 0 TMRB 50 0-2 P:$64 Timer B, Channel 1 TMRB 51 0-2 P:$66 Timer B, Channel 2 TMRB 52 0-2 P:$68 Timer B, Channel 3 Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 45 Preliminary

4.3 Program Map

The Program Memory map is shown in Table 4-3. CMPA 53 0-2 P:$6A Comparator A CMPB 54 0-2 P:$6C Comparator B PIT0 55 0-2 P:$6E Interval Timer 0 PIT1 56 0-2 P:$70 Interval Timer 1 PIT2 57 0-2 P:$72 Interval Timer 2 ADC 58 0-2 P:$74 ADC A Conversion Complete ADC 59 0-2 P:$76 ADC B Conversion Complete ADC 60 0-2 P:$78 ADC Zero Crossing or Limit Error PWM 61 0-2 P:$7A Reload PWM PWM 62 0-2 P:$7C PWM Fault SWILP 63 -1 P:$7E SW Interrupt Low Priority 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0000, the first two locations of the vector table will overlay the chip reset addresses since the reset address would match the base of this vector table. Table 4-3 Program Memory Map1 at Reset 1. All addresses are 16-bit Word addresses. Begin/End Address Memory Allocation P: $1F FFFF P: $00 9000 RESERVED P: $00 8FFF P: $00 8000 On-Chip RAM2 8KB 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1. P: $00 7FFF P: $00 0000 Internal Program Flash 64KB Cop Reset Address = $00 0002 Boot Location = $00 0000 Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function

56F8037 Data Sheet, Rev. 3

46 Freescale Semiconductor

4.4 Data Map

4.5 EOnCE Memory Map

Figure 4-5 lists all EOnCE registers necessary to access or control the EOnCE. Table 4-4 Data Memory Map1 1. All addresses are 16-bit Word addresses. Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 9000 RESERVED X:$00 8FFF X:$00 8000 RESERVED X:$00 7FFF X:$00 1000 RESERVED X:$00 0FFF X:$00 0000 On-Chip Data RAM 8KB2 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1. Reserved RAM Reserved Flash Reserved EOnCE Peripherals Reserved RAM Dual Port RAM Program Data

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 47 Preliminary

4.6 Peripheral Memory-Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read or written using word accesses only. Table 4-5 EOnCE Memory Map Address Register Acronym Register Name X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word X:$FF FFFE OTX / ORX (32 bits) Transmit Register Receive Register X:$FF FFFD OTXRXSR Transmit and Receive Status and Control Register X:$FF FFFC OCLSR Core Lock / Unlock Status Register X:$FF FFFB - X:$FF FFA1 Reserved X:$FF FFA0 OCR Control Register X:$FF FF9F Instruction Step Counter X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9D OSR Status Register X:$FF FF9C OBASE Peripheral Base Address Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9A OTBPR Trace Bu ffer Pointer Register X:$FF FF99 Trace Buffer Register Stages X:$FF FF98 OTB (21 - 24 bits/stage) Trace Buffer Register Stages X:$FF FF97 Breakpoint Unit Control Register X:$FF FF96 OBCR (24 bits) Breakpoint Unit Control Register X:$FF FF95 Breakpoint Unit Address Register 1 X:$FF FF94 OBAR1 (24 bits) Breakpoint Unit Address Register 1 X:$FF FF93 Breakpoint Unit Address Register 2 X:$FF FF92 OBAR2 (32 bits) Breakpoint Unit Address Register 2 X:$FF FF91 Breakpoint Unit Mask Register 2 X:$FF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2 X:$FF FF8F Reserved X:$FF FF8E OBCNTR EOnCE Breakpoint Unit Counter X:$FF FF8D Reserved X:$FF FF8C Reserved X:$FF FF8B Reserved X:$FF FF8A OESCR External Signal Control Register X:$FF FF89 - X:$FF FF00 Reserved

56F8037 Data Sheet, Rev. 3

48 Freescale Semiconductor

Table 4-6 summarizes base addresses for the set of pe ripherals on the 56F8037 de vice. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Table 4-6 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number Timer A TMRA X:$00 F000 4-7 Timer B TMRB X:$00 F040 4-8 ADC ADC X:$00 F080 4-9 PWM PWM X:$00 F0C0 4-10 ITCN ITCN X:$00 F0E0 4-11 SIM SIM X:$00 F100 4-12 COP COP X:$00 F120 4-13 CLK, PLL, OSC OCCS X:$00 F130 4-14 Power Supervisor PS X:$00 F140 4-15 GPIO Port A GPIOA X:$00 F150 4-16 GPIO Port B GPIOB X:$00 F160 4-17 GPIO Port C GPIOC X:$00 F170 4-18 GPIO Port D GPIOD X:$00 F180 4-19 PIT 0 PIT0 X:$00 F190 4-20 PIT 1 PIT1 X:$00 F1A0 4-21 PIT 2 PIT2 X:$00 F1B0 4-22 DAC 0 DAC0 X:$00 F1C0 4-23 DAC 1 DAC1 X:$00 F1D0 4-24 Comparator A CMPA X:$00 F1E0 4-25 Comparator B CMPB X:$00 F1F0 4-26 QSCI 0 QSCI0 X:$00 F200 4-27 QSCI 1 QSCI1 X:$00 F210 4-28 QSPI 0 QSPI0 X:$00 F220 4-29 QSPI 1 QSPI1 X:$00 F230 4-30 I2C I2C X:$00 F280 4-31 FM FM X:$00 F400 4-32 MSCAN CAN X:$00 F800 4-33

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 49 Preliminary Table 4-7 Quad Timer A Registers Address Map (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA0_COMP1 $0 Compare Register 1 TMRA0_COMP2 $1 Compare Register 2 TMRA0_CAPT $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCTRL $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_CSCTRL $A Comparator Status and Control Register TMRA0_FILT $B Input Filter Register Reserved TMRA0_ENBL $F Timer Channel Enable Register TMRA1_COMP1 $10 Compare Register 1 TMRA1_COMP2 $11 Compare Register 2 TMRA1_CAPT $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCTRL $17 Status and Control Register TMRA1_CMPLD1 $18 Comparator Load Register 1 TMRA1_CMPLD2 $19 Comparator Load Register 2 TMRA1_CSCTRL $1A Comparator Status and Control Register TMRA1_FILT $1B Input Filter Register Reserved TMRA2_COMP1 $20 Compare Register 1 TMRA2_COMP2 $21 Compare Register 2 TMRA2_CAPT $22 Capture Register TMRA2_LOAD $23 Load Register TMRA2_HOLD $24 Hold Register TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCTRL $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register 1

56F8037 Data Sheet, Rev. 3

50 Freescale Semiconductor

TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_CSCTRL $2A Comparator Status and Control Register TMRA2_FILT $2B Input Filter Register Reserved TMRA3_COMP1 $30 Compare Register 1 TMRA3_COMP2 $31 Compare Register 2 TMRA3_CAPT $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCTRL $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_CSCTRL $3A Comparator Status and Control Register TMRA3_FILT $3B Input Filter Register Reserved Table 4-8 Quad Timer B Registers Address Map (TMRB_BASE = $00 F040) Register Acronym Address Offset Register Description TMRB0_COMP1 $0 Compare Register 1 TMRB0_COMP2 $1 Compare Register 2 TMRB0_CAPT $2 Capture Register TMRB0_LOAD $3 Load Register TMRB0_HOLD $4 Hold Register TMRB0_CNTR $5 Counter Register TMRB0_CTRL $6 Control Register TMRB0_SCTRL $7 Status and Control Register TMRB0_CMPLD1 $8 Comparator Load Register 1 TMRB0_CMPLD2 $9 Comparator Load Register 2 TMRB0_CSCTRL $A Comparator Status and Control Register TMRB0_FILT $B Input Filter Register Reserved TMRB0_ENBL $F Timer Channel Enable Register TMRB1_COMP1 $10 Compare Register 1 TMRB1_COMP2 $11 Compare Register 2 Table 4-7 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 51 Preliminary TMRB1_CAPT $12 Capture Register TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register TMRB1_SCTRL $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_CSCTRL $1A Comparator Status and Control Register TMRB1_FILT $1B Input Filter Register Reserved TMRB2_COMP1 $20 Compare Register 1 TMRB2_COMP2 $21 Compare Register 2 TMRB2_CAPT $22 Capture Register TMRB2_LOAD $23 Load Register TMRB2_HOLD $24 Hold Register TMRB2_CNTR $25 Counter Register TMRB2_CTRL $26 Control Register TMRB2_SCTRL $27 Status and Control Register TMRB2_CMPLD1 $28 Comparator Load Register 1 TMRB2_CMPLD2 $29 Comparator Load Register 2 TMRB2_CSCTRL $2A Comparator Status and Control Register TMRB2_FILT $2B Input Filter Register Reserved TMRB3_COMP1 $30 Compare Register 1 TMRB3_COMP2 $31 Compare Register 2 TMRB3_CAPT $32 Capture Register TMRB3_LOAD $33 Load Register TMRB3_HOLD $34 Hold Register TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCTRL $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_CSCTRL $3A Comparator Status and Control Register TMRB3_FILT $3B Input Filter Register Reserved Table 4-8 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F040) Register Acronym Address Offset Register Description

56F8037 Data Sheet, Rev. 3

52 Freescale Semiconductor

Table 4-9 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_CTRL1 $0 Control Register 1 ADC_CTRL2 $1 Control Register 2 ADC_ZXCTRL $2 Zero Crossing Control Register ADC_CLIST 1 $3 Channel List Register 1 ADC_CLIST 2 $4 Channel List Register 2 ADC_CLIST 3 $5 Channel List Register 3 ADC_CLIST 4 $6 Channel List Register 4 ADC_SDIS $7 Sample Disable Register ADC_STAT $8 Status Register ADC_RDY $9 Conversion Ready Register ADC_LIMSTAT $A Limit Status Register ADC_ZXSTAT $B Zero Crossing Status Register ADC_RSLT0 $C Result Register 0 ADC_RSLT1 $D Result Register 1 ADC_RSLT2 $E Result Register 2 ADC_RSLT3 $F Result Register 3 ADC_RSLT4 $10 Result Register 4 ADC_RSLT5 $11 Result Register 5 ADC_RSLT6 $12 Result Register 6 ADC_RSLT7 $13 Result Register 7 ADC_RSLT8 $14 Result Register 8 ADC_RSLT9 $15 Result Register 9 ADC_RSLT10 $16 Result Register 10 ADC_RSLT11 $17 Result Register 11 ADC_RSLT12 $18 Result Register 12 ADC_RSLT13 $19 Result Register 13 ADC_RSLT14 $1A Result Register 14 ADC_RSLT15 $1B Result Register 15 ADC_LOLIM0 $1C Low Limit Register 0 ADC_LOLIM1 $1D Low Limit Register 1 ADC_LOLIM2 $1E Low Limit Register 2 ADC_LOLIM3 $1F Low Limit Register 3 ADC_LOLIM4 $20 Low Limit Register 4 ADC_LOLIM5 $21 Low Limit Register 5 ADC_LOLIM6 $22 Low Limit Register 6 ADC_LOLIM7 $23 Low Limit Register 7

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 53 Preliminary ADC_HILIM0 $24 High Limit Register 0 ADC_HILIM1 $25 High Limit Register 1 ADC_HILIM2 $26 High Limit Register 2 ADC_HILIM3 $27 High Limit Register 3 ADC_HILIM4 $28 High Limit Register 4 ADC_HILIM5 $29 High Limit Register 5 ADC_HILIM6 $2A High Limit Register 6 ADC_HILIM7 $2B High Limit Register 7 ADC_OFFST0 $2C Offset Register 0 ADC_OFFST1 $2D Offset Register 1 ADC_OFFST2 $2E Offset Register 2 ADC_OFFST3 $2F Offset Register 3 ADC_OFFST4 $30 Offset Register 4 ADC_OFFST5 $31 Offset Register 5 ADC_OFFST6 $32 Offset Register 6 ADC_OFFST7 $33 Offset Register 7 ADC_PWR $34 Power Control Register ADC_CAL $35 Calibration Register Reserved Table 4-10 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_CTRL $0 Control Register PWM_FCTRL $1 Fault Control Register PWM_FLTACK $2 Fault Status Acknowledge Register PWM_OUT $3 Output Control Register PWM_CNTR $4 Counter Register PWM_CMOD $5 Counter Modulo Register PWM_VAL0 $6 Value Register 0 PWM_VAL1 $7 Value Register 1 PWM_VAL2 $8 Value Register 2 PWM_VAL3 $9 Value Register 3 PWM_VAL4 $A Value Register 4 PWM_VAL5 $B Value Register 5 PWM_DTIM0 $C Dead Time Register 0 PWM_DTIM1 $D Dead Time Register 1 PWM_DMAP1 $E Disable Mapping Register 1 Table 4-9 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description

56F8037 Data Sheet, Rev. 3

54 Freescale Semiconductor

PWM_DMAP2 $F Disable Mapping Register 2 PWM_CNFG $10 Configure Register PWM_CCTRL $11 Channel Control Register PWM_PORT $12 Port Register PWM_ICCTRL $13 Internal Correction Control Register PWM_SCTRL $14 Source Control Register PWM_SYNC $15 Synchronization Window Register PWM_FFILT0 $16 Fault0 Filter Register PWM_FFILT1 $17 Fault1 Filter Register PWM_FFILT2 $18 Fault2 Filter Register PWM_FFILT3 $19 Fault3 Filter Register Table 4-11 Interrupt Control Registers Address Map (ITCN_BASE = $00 F0E0) Register Acronym Address Offset Register Description ITCN_IPR0 $0 Interrupt Priority Register 0 ITCN_IPR1 $1 Interrupt Priority Register 1 ITCN_IPR2 $2 Interrupt Priority Register 2 ITCN_IPR3 $3 Interrupt Priority Register 3 ITCN_IPR4 $4 Interrupt Priority Register 4 ITCN_IPR5 $5 Interrupt Priority Register 5 ITCN_IPR6 $6 Interrupt Priority Register 6 ITCN_VBA $7 Vector Base Address Register ITCN_FIM0 $8 Fast Interrupt Match 0 Register ITCN_FIVAL0 $9 Fast Interrupt Ve ctor Address Low 0 Register ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register ITCN_FIM1 $B Fast Interrupt Match 1 Register ITCN_FIVAL1 $C Fast Interrupt Ve ctor Address Low 1 Register ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register ITCN_IRQP0 $E IRQ Pending Register 0 ITCN_IRQP1 $F IRQ Pending Register 1 ITCN_IRQP2 $10 IRQ Pending Register 2 ITCN_IRQP3 $11 IRQ Pending Register 3 Reserved ITCN_ICTRL $16 Interrupt Control Register Reserved Table 4-10 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 55 Preliminary Table 4-12 SIM Registers Address Map (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register SIM_RSTAT $1 Reset Status Register SIM_SWC0 $2 Software Control Register 0 SIM_SWC1 $3 Software Control Register 1 SIM_SWC2 $4 Software Control Register 2 SIM_SWC3 $5 Software Control Register 3 SIM_MSHID $6 Most Significant Half JTAG ID SIM_LSHID $7 Least Signifi cant Half JTAG ID SIM_PWR $8 Power Control Register Reserved SIM_CLKOUT $A Clock Out Select Register SIM_PCR $B Peripheral Clock Rate Register SIM_PCE0 $C Peripheral Clock Enable Register 0 SIM_PCE1 $D Peripheral Clock Enable Register 1 SIM_SD0 $E Peripheral STOP Disable Register 0 SIM_SD1 $F Peripheral STOP Disable Register 1 SIM_IOSAHI $10 I/O Short Address Location High Register SIM_IOSALO $11 I/O Short Address Location Low Register SIM_PROT $12 Protection Register SIM_GPSA0 $13 GPIO Peripheral Se lect Register 0 for GPIOA SIM_GPSA1 $14 GPIO Peripheral Se lect Register 1 for GPIOA SIM_GPSB0 $15 GPIO Peripheral Se lect Register 0 for GPIOB SIM_GPSB1 $16 GPIO Peripheral Se lect Register 1 for GPIOB SIM_GPSCD $17 GPIO Periph eral Select Register for GPIOC and GPIOD SIM_IPS0 $18 Internal Peripheral Source Select Register 0 for PWM SIM_IPS1 $19 Internal Peripheral Source Select Register 1 for DACs SIM_IPS2 $1A Internal Peripheral So urce Select Register 2 for TMRA Reserved Table 4-13 Computer Operating Properly Registers Address Map (COP_BASE = $00 F120) Register Acronym Address Offset Register Description COP_CTRL $0 Control Register COP_TOUT $1 Time-Out Register COP_CNTR $2 Counter Register

56F8037 Data Sheet, Rev. 3

56 Freescale Semiconductor

Table 4-14 Clock Generation Module Registers Address Map (OCCS_BASE = $00 F130) Register Acronym Address Offset Register Description OCCS_CTRL $0 Control Register OCCS_DIVBY $1 Divide-By Register OCCS_STAT $2 Status Register Reserved OCCS_OCTRL $5 Oscillator Control Register OCCS_CLKCHK $6 Clock Check Register OCCS_PROT $7 Protection Register Table 4-15 Power Supervisor Registers Address Map (PS_BASE = $00 F140) Register Acronym Address Offset Register Description PS_CTRL $0 Control Register PS_STAT $1 Status Register Reserved Table 4-16 GPIOA Registers Address Map (GPIOA_BASE = $00 F150) Register Acronym Address Offset Register Description GPIOA_PUPEN $0 Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register GPIOA_IASSRT $4 Interrupt Assert Register GPIOA_IEN $5 Interrupt Enable Register GPIOA_IPOL $6 Interrupt Polarity Register GPIOA_IPEND $7 Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register GPIOA_RDATA $A Raw Data Input Register GPIOA_DRIVE $B Output Drive Strength Control Register

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 57 Preliminary Table 4-17 GPIOB Registers Address Map (GPIOB_BASE = $00 F160) Register Acronym Address Offset Register Description GPIOB_PUPEN $0 Pull-up Enable Register GPIOB_DATA $1 Data Register GPIOB_DDIR $2 Data Direction Register GPIOB_PEREN $3 Peripheral Enable Register GPIOB_IASSRT $4 Interru pt Assert Register GPIOB_IEN $5 Interrupt Enable Register GPIOB_IPOL $6 Interrupt Polarity Register GPIOB_IPEND $7 Interrupt Pending Register GPIOB_IEDGE $8 Interrupt Edge-Sensitive Register GPIOB_PPOUTM $9 Push-Pull Output Mode Control Register GPIOB_RDATA $A Raw Data Input Register GPIOB_DRIVE $B Output Drive Strength Control Register Table 4-18 GPIOC Registers Address Map (GPIOC_BASE = $00 F170) Register Acronym Address Offset Register Description GPIOC_PUPEN $0 Pull-up Enable Register GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IPOL $6 Interrupt Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register GPIOC_PPOUTM $9 Push-Pull Output Mode Control Register GPIOC_RDATA $A Raw Data Input Register GPIOC_DRIVE $B Output Drive Strength Control Register

56F8037 Data Sheet, Rev. 3

58 Freescale Semiconductor

Table 4-19 GPIOD Registers Address Map (GPIOD_BASE = $00 F180) Register Acronym Address Offset Register Description GPIOD_PUPEN $0 Pull-up Enable Register GPIOD_DATA $1 Data Register GPIOD_DDIR $2 Data Direction Register GPIOD_PEREN $3 Peripheral Enable Register GPIOD_IASSRT $4 Interr upt Assert Register GPIOD_IEN $5 Interrupt Enable Register GPIOD_IPOL $6 Interrupt Polarity Register GPIOD_IPEND $7 Interrupt Pending Register GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register GPIOD_PPOUTM $9 Push-Pull Output Mode Control Register GPIOD_RDATA $A Raw Data Input Register GPIOD_DRIVE $B Output Drive Strength Control Register Table 4-20 Programmable Interval Timer 0 Registers Address Map (PIT0_BASE = $00 F190) Register Acronym Address O ffset Register Description PIT0_CTRL $0 Control Register PIT0_MOD $1 Modulo Register PIT0_CNTR $2 Counter Register Table 4-21 Programmable Interval Timer 1 Registers Address Map (PIT1_BASE = $00 F1A0) Register Acronym Address O ffset Register Description PIT1_CTRL $0 Control Register PIT1_MOD $1 Modulo Register PIT1_CNTR $2 Counter Register Table 4-22 Programmable Interval Timer 2 Registers Address Map (PIT2_BASE = $00 F1B0) Register Acronym Address O ffset Register Description PIT2_CTRL $0 Control Register PIT2_MOD $1 Modulo Register PIT2_CNTR $2 Counter Register

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 59 Preliminary Table 4-23 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0) Register Acronym Address O ffset Register Description DAC0_CTRL $0 Control Register DAC0_DATA $1 Data Register DAC0_STEP $2 Step Register DAC0_MINVAL $3 Minimum Value Register DAC0_MAXVAL $4 Maximum Value Register Table 4-24 Digital-to-Analog Converter 0 Registers Address Map (DAC1_BASE = $00 F1D0) Register Acronym Address O ffset Register Description DAC1_CTRL $0 Control Register DAC1_DATA $1 Data Register DAC1_STEP $2 Step Register DAC1_MINVAL $3 Minimum Value Register DAC1_MAXVAL $4 Maximum Value Register Table 4-25 Comparator A Registers Address Map (CMPA_BASE = $00 F1E0) Register Acronym Address O ffset Register Description CMPA_CTRL $0 Control Register CMPA_STAT $1 Status Register CMPA_FILT $2 Filter Register Table 4-26 Comparator B Registers Address Map (CMPB_BASE = $00 F1F0) Register Acronym Address O ffset Register Description CMPB_CTRL $0 Control Register CMPB_STAT $1 Status Register CMPB_FILT $2 Filter Register

56F8037 Data Sheet, Rev. 3

60 Freescale Semiconductor

Table 4-27 Queued Serial Communication Interface 0 Registers Address Map (QSCI0_BASE = $00 F200) Register Acronym Address O ffset Register Description QSCI0_RATE $0 Baud Rate Register QSCI0_CTRL1 $1 Control Register 1 QSCI0_CTRL2 $2 Control Register 2 QSCI0_STAT $3 Status Register QSCI0_DATA $4 Data Register Table 4-28 Queued Serial Communication Interface 1 Registers Address Map (QSCI1_BASE = $00 F210) Register Acronym Address O ffset Register Description QSCI1_RATE $0 Baud Rate Register QSCI1_CTRL1 $1 Control Register 1 QSCI1_CTRL2 $2 Control Register 2 QSCI1_STAT $3 Status Register QSCI1_DATA $4 Data Register Table 4-29 Queued Serial Peripheral Interface 0 Registers Address Map (QSPI0_BASE = $00 F220) Register Acronym Address Offset Register Description QSPI0_SCTRL $0 Status and Control Register QSPI0_DSCTRL $1 Data Size and Control Register QSPI0_DRCV $2 Data Receive Register QSPI0_DXMIT $3 Data Transmit Register QSPI0_FIFO $4 FIFO Control Register QSPI0_DELAY $5 Delay Register Table 4-30 Queued Serial Peripheral Interface 1 Registers Address Map (QSPI1_BASE = $00 F230) Register Acronym Address Offset Register Description QSPI1_SCTRL $0 Status and Control Register QSPI1_DSCTRL $1 Data Size and Control Register QSPI1_DRCV $2 Data Receive Register QSPI1_DXMIT $3 Data Transmit Register QSPI1_FIFO $4 FIFO Control Register QSPI1_DELAY $5 Delay Register

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 61 Preliminary Table 4-31 I2C Registers Address Map (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_CTRL $0 Control Register I2C_TAR $2 Target Address Register I2C_SAR $4 Slave Address Register I2C_DATA $8 RX/TX Data Buffer and Command Register I2C_SSHCNT $A Standard Speed Clock SCL High Count Register I2C_SSLCNT $C Standard Speed Clock SCL Low Count Register I2C_FSHCNT $E Fast Speed Clock SCL High Count Register I2C_FSLCNT $10 Fast Speed Clock SCL Low Count Register I2C_ISTAT $16 Interrupt Status Register I2C_IMASK $18 Interrupt Mask Register I2C_RISTAT $1A Raw Interrupt Status Register I2C_RXFT $1C Receive FIFO Threshold Register I2C_TXFT $1E Transmit FIFO Threshold Register I2C_CLRINT $20 Clear Combined and Individual Interrupts Register I2C_CLRRXUND $22 Clear RX_UNDER Interrupt Register I2C_CLRRXOVR $24 Clear RX_O VER Interrupt Register I2C_CLRTXOVR $26 Clear TX_OVER Interrupt Register I2C_CLRRDREQ $28 Clear RD_REQ Interrupt Register I2C_CLRTXABRT $2A Clear TX_ ABRT Interrupt Register I2C_CLRRXDONE $2C Clear RX_DONE Interrupt Register I2C_CLRACT $2E Clear Acti vity Interrupt Register I2C_CLRSTPDET $30 Clear STOP_DET Interrupt Register I2C_CLRSTDET $32 Clear START_DET Interrupt Register I2C_CLRGC $34 Clear GEN_CALL Interrupt Register I2C_ENBL $36 Enable Register I2C_STAT $38 Status Register I2C_TXFLR $3A Transmit FIFO Level Register I2C_RXFLR $3C Receive FIFO Level Register I2C_TXABRTSRC $40 Transmit Abort Status Register

56F8037 Data Sheet, Rev. 3

62 Freescale Semiconductor

Table 4-32 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address O ffset Register Description FM_CLKDIV $0 Clock Divider Register FM_CNFG $1 Configuration Register $2 Reserved FM_SECHI $3 Security High Half Register FM_SECLO $4 Security Low Half Register $5 - $9 Reserved FM_PROT $10 Protection Register $11 - $12 Reserved FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 - $17 Reserved FM_DATA $18 Data Buffer Register $19 - $A Reserved FM_OPT1 $1B Information Option Register 1 $1C Reserved FM_TSTSIG $1D Test Array Signature Register Table 4-33 MSCAN Registers Address Map (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_CTRL0 $00 Control Register 0 MSCAN_CTRL1 $01 Control Register 1 MSCAN_BTR0 $02 Bus Timing Register 0 MSCAN_BTR1 $03 Bus Timing Register 1 MSCAN_RFLG $04 Receiver Flag Register MSCAN_RIER $05 Receiver Interrupt Enable Register MSCAN_TFLG $06 Transmitter Flag Register MSCAN_TIER $07 Transmitter Interrupt Enable Register MSCAN_TARQ $08 Transmitter Message Abort Request Register MSCAN_TAAK $09 Transmitter Message Abort Acknowledge Register MSCAN_TBSEL $0A Transmitter Buffer Selection Register MSCAN_IDAC $0B Identifier Acceptance Control Register Reserved MSCAN_MISC $0D Miscellaneous Register MSCAN_RXERR $0E Receive Error Register

Peripheral Memory-Mapped Registers 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 63 Preliminary MSCAN_TXERR $0F Transmit Error Register MSCAN_IDAR0 $10 Identifier Acceptance Register 0 MSCAN_IDAR1 $11 Identifier Acceptance Register 1 MSCAN_IDAR2 $12 Identifier Acceptance Register 2 MSCAN_IDAR3 $13 Identifier Acceptance Register 3 MSCAN_IDMR0 $14 Identifier Mask Register 0 MSCAN_IDMR1 $15 Identifier Mask Register 1 MSCAN_IDMR2 $16 Identifier Mask Register 2 MSCAN_IDMR3 $17 Identifier Mask Register 3 MSCAN_IDAR4 $18 Identifier Acceptance Register 4 MSCAN_IDAR5 $19 Identifier Acceptance Register 5 MSCAN_IDAR6 $1A Identifier Acceptance Register 6 MSCAN_IDAR7 $1B Identifier Acceptance Register 7 MSCAN_IDMR4 $1C Identifier Mask Register 4 MSCAN_IDMR5 $1D Identifier Mask Register 5 MSCAN_IDMR6 $1E Identifier Mask Register 6 MSCAN_IDMR7 $1F Identifier Mask Register 7 MSCAN_RXFG0 $20 Foreground Receive Buffer 0 MSCAN_RXFG1 $21 Foreground Receive Buffer 1 MSCAN_RXFG2 $22 Foreground Receive Buffer 2 MSCAN_RXFG3 $23 Foreground Receive Buffer 3 MSCAN_RXFG4 $24 Foreground Receive Buffer 4 MSCAN_RXFG5 $25 Foreground Receive Buffer 5 MSCAN_RXFG6 $26 Foreground Receive Buffer 6 MSCAN_RXFG7 $27 Foreground Receive Buffer 7 MSCAN_RXFG8 $28 Foreground Receive Buffer 8 MSCAN_RXFG9 $29 Foreground Receive Buffer 9 MSCAN_RXFG10 $2A Foreground Receive Buffer 10 MSCAN_RXFG11 $2B Foreground Receive Buffer 11 MSCAN_RXFG12 $2C Foreground Receive Buffer 12 MSCAN_RXFG13 $2D Foreground Receive Buffer 13 MSCAN_RXFG14 $2E Foreground Receive Buffer 14 MSCAN_RXFG15 $2F Foreground Receive Buffer 15 MSCAN_TXFG0 $30 Foreground Transmit Buffer 0 MSCAN_TXFG1 $31 Foreground Transmit Buffer 1 MSCAN_TXFG2 $32 Foreground Transmit Buffer 2 Table 4-33 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description

56F8037 Data Sheet, Rev. 3

64 Freescale Semiconductor

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to the 56800E core when an interrupt of sufficient priori ty exists, and to what a ddress to jump in order to service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

• Programmable priority levels for each IRQ
• Two programmable Fast Interrupts
• Notification to SIM module to restar t clocks out of Wait and Stop modes
• Ability to drive initial address on the address bus after reset For further information, see Table 4-2, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller is a slave on the IPBus. It contains register s that allow each of the 64 interrupt sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority and number 63 is the lowest. MSCAN_TXFG3 $33 Foreground Transmit Buffer 3 MSCAN_TXFG4 $34 Foreground Transmit Buffer 4 MSCAN_TXFG5 $35 Foreground Transmit Buffer 5 MSCAN_TXFG6 $36 Foreground Transmit Buffer 6 MSCAN_TXFG7 $37 Foreground Transmit Buffer 7 MSCAN_TXFG8 $38 Foreground Transmit Buffer 8 MSCAN_TXFG9 $39 Foreground Transmit Buffer 9 MSCAN_TXFG10 $3A Foreground Transmit Buffer 10 MSCAN_TXFG11 $3B Foreground Transmit Buffer 11 MSCAN_TXFG12 $3C Foreground Transmit Buffer 12 MSCAN_TXFG13 $3D Foreground Transmit Buffer 13 MSCAN_TXFG14 $3E Foreground Transmit Buffer 14 MSCAN_TXFG15 $3F Foreground Transmit Buffer 15 Reserved Table 4-33 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 65 Preliminary

5.3.1 Normal Interrupt Handling

Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt.

5.3.2 Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priori ty than the current exception to be serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0 and I1 bits in its status register. The IPIC bits of the ICTR L register reflect the state of the pr iority level being presented to the 56800E core.

5.3.3 Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIM n register to the appropriate vector number 3. Setting the FIV AL n and FIV AHn registers with the address of the code for the Fast Interrupt Table 5-1 Interrupt Mask Bit Definition SR[9] (I1) SR[8] (I0) Exceptions Permitted Exceptions Masked 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 Table 5-2 Interrupt Priority Encoding IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority

00 No interrupt or SWILP Priorities 0, 1, 2, 3

01 Priority 0 Priorities 1, 2, 3

10 Priority 1 Priorities 2, 3

11 Priority 2 or 3 Priority 3

56F8037 Data Sheet, Rev. 3

66 Freescale Semiconductor

When an interrupt occurs, its vector number is compar ed with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVAL n and FIVAHn registers, instead of gene rating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts its Fast Interrupt handling.

5.4 Block Diagram

Figure 5-1 Interrupt Controller Block Diagram Priority Level 2 -> 4 Decode INT1 Priority Level 2 -> 4 Decode INT64 Level 0 64 -> 6 Priority Encoder any0 Level 3 64 -> 6 Priority Encoder any3 INT VAB IPIC CONTROL

6 PIC_EN

SR[9:8]

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 67 Preliminary

5.5 Operating Modes

The ITCN module design contains two major modes of operation:

• Functional Mode The ITCN is in this mode by default.
• Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.

5.6 Register Descriptions

A register address is the sum of a base address and an addr ess offset. The base addr ess is defined at the system level and the address offset is defined at the module level. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F060) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.5 IPR5 $5 Interrupt Priority Register 5 5.6.6 IPR6 $6 Interrupt Priority Register 6 5.6.7 VBA $7 Vector Base Address Register 5.6.8 FIM0 $8 Fast Interrupt Match 0 Register 5.6.9 FIVAL0 $9 Fast Interrupt 0 Vector Address Low Register 5.6.10 FIVAH0 $A Fast Interrupt 0 Vector Address High 0 Register 5.6.11 FIM1 $B Fast Interrupt Match 1 Register 5.6.12 FIVAL1 $C Fast Interrupt 1 Vector Address Low Register 5.6.13 FIVAH1 $D Fast Interrupt 1 Vector Address High Register 5.6.14 IRQP0 $E IRQ Pending Register 0 5.6.15 IRQP1 $F IRQ Pending Register 1 5.6.16 IRQP2 $10 IRQ Pending Register 2 5.6.17 IRQP3 $11 IRQ Pending Register 3 5.6.18 Reserved ICTRL $16 Interrupt Control Register 5.6.19 Reserved

56F8037 Data Sheet, Rev. 3

68 Freescale Semiconductor

Figure 5-2 ITCN Register Map Summary Add. Offset Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 IPR0 R PLL IPL LVI IPL 0 0 RX_REG IPL TX_REG IPL TRBUF IPL BKPT_U IPL STPCNT IPLW $1 IPR1 R GPIOD IPL MSCAN_WK UP IPL MSCAN_TX IPL MSCAN_RX IPL MSCAN_ERR IPL FM_CBE IPL FM_CC IPL FM_ERR IPLW $2 IPR2 R QSCI0_XMIT IPL QSPI1_XMIT IPL QSPI1_RCV IPL QSPI0_XMIT IPL QSPI0_RCV IPL GPIOA IPL GPIOB IPL GPIOC IPLW $3 IPR3 R I2C_ERR IPL QSCI1_RCV IPL QSCI1_RER R IPL QSCI1_TIDL IPL QSCI1_XMIT IPL QSCI0_RCV IPL QSCI0_RERR IPL QSCI0_TIDL IPLW $4 IPR4 R TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL I2C_TX IPL I2C_RX IPL I2C_GEN IPLW $5 IPR5 R PIT1 IPL PIT0 IPL COMPB IPL COMPA IPL TMRB_3 IPL TMRB_2 IPL TMRB_1 IPL TMRB_0 IPLW $6 IPR6 0 0 0 0 PWM_F IPL PWM_RL IPL ADC_ZC IPL ADCB_CC IPL ADCA_CC IPL PIT2 IPL $7 VBA R 0 0 VECTOR_BASE_ADDRESSW $8 FIM0 R 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0W $9 FIVAL0 R FAST INTERRUPT 0 VECTOR ADDRESS LOWW $A FIVAH0 R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGHW $B FIM1 R 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1W $C FIVAL1 R FAST INTERRUPT 1 VECTOR ADDRESS LOWW $D FIVAH1 R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGHW $E IRQP0 R PENDING[16:2] 1 W $F IRQP1 R PENDING[32:17] W $10 IRQP2 R PENDING[48:33] W $11 IRQP3 R PENDING[63:49] W Reserved $16 ICTRL R INT IPIC VAB INT_ DIS 1 1 1 0 0 W Reserved = Reserved

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 69 Preliminary

5.6.1 Interrupt Priority Register 0 (IPR0)

Figure 5-3 Interrupt Priority Register 0 (IPR0)

5.6.1.1 PLL Loss of Referenc e or Change in Lock Status Interrupt Priority Level

(PLL IPL)—Bits 15–14 This field is used to set the interrupt priority levels for the PLL Loss of Reference or Change in Lock Status IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.6.1.2 Low Voltage Detector Interru pt Priority Level (LVI IPL)—Bits 13–12

This field is used to set the interrupt priority levels for the Low Voltage Detector IRQ. This IRQ is limited to priorities 1 through 3 and is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.6.1.3 Reserved—Bits 11–10

This bit field is reserved. Each bit must be set to 0.

5.6.1.4 EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)— Bits 9–8 This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3 Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PLL IPL LVI IPL 0 0 RX_REG IPL TX_REG IPL TRBUF IPL BKPT_U IPL STPCNT IPL Write RESET 0 0 0 0 0 0 0000000000

56F8037 Data Sheet, Rev. 3

70 Freescale Semiconductor

5.6.1.5 EOnCE Transmit Regist er Empty Interrupt Priority Level

(TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.6.1.6 EOnCE Trace Buffer Interrupt Priority Level

(TRBUF IPL)— Bits 5–4 This field is used to set the interrupt priority level for the EOnCE Trace Buffer IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.6.1.7 EOnCE Breakpoint Un it Interrupt Priority Level

(BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for the EOnCE Breakpoint Unit IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.6.1.8 EOnCE Step Counte r Interrupt Priority Level

(STPCNT IPL)— Bits 1–0 This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 71 Preliminary

5.6.2 Interrupt Priority Register 1 (IPR1)

Figure 5-4 Interrupt Priority Register 1 (IPR1)

5.6.2.1 GPIOD Interrupt Priorit y Level (GPIOD IPL)—Bits 15–14

This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.2 MSCAN Wake Up Interrupt Priority Level

(MSCAN_WKUP IPL)—Bits 13–12 This field is used to set the interrupt priority level for the MSCAN Wake Up IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.3 MSCAN Transmit Interrupt Priority Level (MSCAN_TX IPL)—Bits 11–10

This field is used to set the interrupt priority level for the MSCAN Transmit IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.4 MSCAN Receive Interrupt Pri ority Level (MSCAN_RX IPL)—Bits 9–8

This field is used to set the inte rrupt priority level for MSCAN Receive IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2 Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read GPIOD IPL MSCAN_WK UP IPL MSCAN_TX IPL MSCAN_RX IPL MSCAN_ERR IPL FM_CBE IPL FM_CC IPL FM_ERR IPL Write RESET 00000000 0 0000000

56F8037 Data Sheet, Rev. 3

72 Freescale Semiconductor

5.6.2.5 MSCAN Error Interrupt Priori ty Level (MSCAN_ERR IPL)—Bits 7–6

This field is used to set the interrupt priority le vel for the MSCAN Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.6 FM Command, Data, Address Buffers Empty Interrupt Priority Level

(FM_CBE IPL)—Bits 5–4 This field is used to set the in terrupt priority level for the FM Command, Data Address Buffers Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.7 FM Command Complete Inte rrupt Priority Level (FM_CC IPL)—Bits 3–2

This field is used to set the in terrupt priority level for the FM Command Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.2.8 FM Error Interrupt Prio rity Level (FM_ERR IPL)—Bits 1–0

This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3 Interrupt Priority Register 2 (IPR2)

Figure 5-5 Interrupt Priority Register 2 (IPR2) Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read QSCI0_XMIT IPL QSPI1_XMIT IPL QSPI1_RCV IPL QSPI0_XMIT IPL QSPI0_RCV IPL GPIOA IPL GPIOB IPL GPIOC IPL Write RESET 0000000000000000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 73 Preliminary

5.6.3.1 QSCI 0 Transmitter Empty Inte rrupt Priority Level (QSCI0_XMIT IPL)—

Bits 15–14 This field is used to set the inte rrupt priority level fo r the QSCI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.2 QSPI 1 Transmitter Empty I nterrupt Priority Level (QSPI1_XMIT IPL)—

Bits 13–12 This field is used to set the interrupt priority le vel for the QSPI1 Transmitte r Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.3 QSPI 1 Receiver Full Interr upt Priority Level (QSPI1_RCV IPL)—

Bits 11–10 This field is used to set the interru pt priority level for the QSPI1 Recei ver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.4 QSPI 0 Transmitter Empty I nterrupt Priority Level (QSPI0_XMIT IPL)—

Bits 9–8 This field is used to set the interrupt priority le vel for the QSPI0 Transmitte r Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

56F8037 Data Sheet, Rev. 3

74 Freescale Semiconductor

5.6.3.5 QSPI 0 Receiver Full Interrupt Pr iority Level (QSPI0_RCV IPL)—Bits 7–6

This field is used to set the interru pt priority level for the QSPI0 Recei ver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.6 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4

This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.7 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2

This field is used to set the interrupt priority level for the GPIOB IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.3.8 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0

This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4 Interrupt Priority Register 3 (IPR3)

Figure 5-6 Interrupt Priority Register 3 (IPR3) Base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read I2C_ERR IPL QSCI1_RCV IPL QSCI1_RER R IPL QSCI1_TIDL IPL QSCI1_XMIT IPL QSCI0_RCV IPL QSCI0_RERR IPL QSCI0_TIDL IPLWrite RESET 0 00000000000 0 0 00

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 75 Preliminary

5.6.4.1 I 2C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14

This field is used to set the interrupt priority level for the I2C Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.2 QSCI 1 Receiver Full Interr upt Priority Level (QSCI1_RCV IPL)—

Bits 13–12 This field is used to set the interrupt priority level for the QSCI1 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.3 QSCI 1 Receiver Error Inte rrupt Priority Level (QSCI1_RERR IPL)—

Bits 11–10 This field is used to set the interrupt priority level for the QSCI1 Receiver Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.4 QSCI 1 Transmitter Idle I nterrupt Priority Level (QSCI1_TIDL IPL)—

Bits 9–8 This field is used to set the interrupt priority level for the QSCI1 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

56F8037 Data Sheet, Rev. 3

76 Freescale Semiconductor

5.6.4.5 QSCI 1 Transmitter Empty Inte rrupt Priority Level (QSCI1_XMIT IPL)—

Bits 7–6 This field is used to set the inte rrupt priority level fo r the QSCI1 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.6 QSCI 0 Receiver Full Interrupt Pr iority Level (QSCI0_RCV IPL)—Bits 5–4

This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.7 QSCI 0 Receiver Error Inte rrupt Priority Level (QSCI0_RERR IPL)—

Bits 3–2 This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.4.8 QSCI 0 Transmitter Idle I nterrupt Priority Level (QSCI0_TIDL IPL)—

Bits 1–0 This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 77 Preliminary

5.6.5 Interrupt Priority Register 4 (IPR4)

Figure 5-7 Interrupt Priority Register 4 (IPR4)

5.6.5.1 Timer A, Channel 3 I nterrupt Priority Level (TMRA_3 IPL)—

Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.2 Timer A, Channel 2 I nterrupt Priority Level (TMRA_2 IPL)—

Bits 13–12 This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.3 Timer A, Channel 1 I nterrupt Priority Level (TMRA_1 IPL)—

Bits 11–10 This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2 Base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL I2C_TX IPL I2C_RX IPL I2C_GEN IPL Write RESET 00000000000 0 0 0 0 0

56F8037 Data Sheet, Rev. 3

78 Freescale Semiconductor

5.6.5.4 Timer A, Channel 0 I nterrupt Priority Level (TMRA_0 IPL)—

Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.5 I 2C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6

This field is used to set the interrupt priority level for the I2C Status IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.6 I 2C Transmit Interrupt Priority Level (I2C_TX IPL)—Bits 5–4

This field is used to set the in terrupt priority level for the I 2C Transmit IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.7 I 2C Receive Interrupt Priority Level (I2C_RX IPL)— Bits 3–2

This field is used to set the interrupt priority level for the I 2C Receiver IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.5.8 I 2C General Call Interrupt Priority Level (I2C_GEN IPL)—Bits 1–0

This field is used to set the interrupt priority level for the I 2C General Call IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 79 Preliminary

5.6.6 Interrupt Priority Register 5 (IPR5)

Figure 5-8 Interrupt Priority Register 5 (IPR6)

5.6.6.1 Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)—

Bits 15–14 This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.2 Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)—

Bits 13–12 This field is used to set the interrupt priority level for the Programmable Interval Timer 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.3 Comparator B Interru pt Priority Level (COMPB IPL)—

Bits 11–10 This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2 Base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PIT1 IPL PIT0 IPL COMPB IPL COMPA IPL TMRB_3 IPL TMRB_2 IPL TMRB_1 IPL TMRB_0 IPL Write RESET 00000000000 0 0 0 0 0

56F8037 Data Sheet, Rev. 3

80 Freescale Semiconductor

5.6.6.4 Comparator A Interru pt Priority Level (COMPA IPL)—

Bits 9–8 This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.5 Timer B, Channel 3 Interr upt Priority Level (TMRB_3 IPL)—Bits 7–6

This field is used to set the interrupt priority level for the Timer B, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.6 Timer B, Channel 2 Interr upt Priority Level (TMRB_2 IPL)—Bits 5–4

This field is used to set the interrupt priority level for the Timer B, Channel 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.7 Timer B, Channel 1 Interr upt Priority Level (TMRB_1 IPL)—Bits 3–2

This field is used to set the interrupt priority level for the Timer B, Channel 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.6.8 Timer B, Channel 0 Interr upt Priority Level (TMRB_0 IPL)—Bits 1–0

This field is used to set the interrupt priority level for the Timer B, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 81 Preliminary

5.6.7 Interrupt Priority Register 6 (IPR6)

Figure 5-9 Interrupt Priority Register 6 (IPR6)

5.6.7.1 Reserved—Bits 15–12

This bit field is reserved. Each bit must be set to 0.

5.6.7.2 PWM Fault Interrupt Priori ty Level (PWM_F IPL)—Bits 11–10

This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.7.3 Reload PWM Interrupt Pri ority Level (PWM_RL IPL)—Bits 9–8

This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.7.4 ADC Zero Crossing Interrupt Pr iority Level (ADC_ZC IPL)—Bits 7–6

This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2 Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 PWM_F IPL PWM_RL IPL ADC_ZC IPL ADCB_CC IPL ADCA_CC IPL PIT2 IPL Write RESET 00000000000 0 0 0 0 0

56F8037 Data Sheet, Rev. 3

82 Freescale Semiconductor

5.6.7.5 ADC B Conversion Comp lete Interrupt Priority Level

(ADCB_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.7.6 ADC A Conversion Comp lete Interrupt Priority Level

(ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.7.7 Programmable Interval Timer 2 Interrupt Priority Level

(PIT2 IPL)—Bits 1–0 This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.6.8 Vector Base Address Register (VBA)

Figure 5-10 Vector Base Address Register (VBA)

5.6.8.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0. Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 VECTOR_BASE_ADDRESS Write RESET 0 00000 0 0000 0 1 1. The 56F8037 resets to a value of 0 x 0000. This corresponds to reset addresses of 0 x 000000. 0000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 83 Preliminary

5.6.8.2 Vector Address Bus (VAB) Bits 13–0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core.

5.6.9 Fast Interrupt Match 0 Register (FIM0)

Figure 5-11 Fast Interrupt Match 0 Register (FIM0)

5.6.9.1 Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.9.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexp ected results will occur if a Fast Interrupt vector is set to any othe r priority. A Fast Interrupt automa tically becomes the highest-priority level 2 interrupt regardless of its location in the interru pt table prior to being de clared as Fast Interrupt. Fast Interrupt 0 has priority over Fa st Interrupt 1. To determine the v ector number of each IRQ, refer to the vector table.

5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 Write RESET 0000000000000000 Base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0000000000000000

56F8037 Data Sheet, Rev. 3

84 Freescale Semiconductor

5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0)

Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.6.11.1 Reserved—Bits 15–5

This bit field is reserved. Each bit must be set to 0.

5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.12 Fast Interrupt 1 Match Register (FIM1)

Figure 5-14 Fast Interrupt 1 Match Register (FIM1)

5.6.12.1 Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.12.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexp ected results will occur if a Fast Interrupt vector is set to any othe r priority. A Fast Inte rrupt automatically beco mes the highest priority level 2 interrupt, regardless of its location in the interr upt table prior to being d eclared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector numbe r of each IRQ, refer to the vector table.

5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGHWrite RESET 0000000000000000 Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 Write RESET 0000000000000000 Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 VECTOR ADDRESS LOW Write RESET 0000000000000000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 85 Preliminary

5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)

Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.6.14.1 Reserved—Bits 15–5

This bit field is reserved. Each bit must be set to 0.

5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.15 IRQ Pending Register 0 (IRQP0)

Figure 5-17 IRQ Pending Register 0 (IRQP0)

5.6.15.1 IRQ Pending (PENDING)—Bits 16–2

This register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations.

• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

5.6.15.2 Reserved—Bit 0

This bit field is reserved. It must be set to 0. Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGHWrite RESET 0000000000000000 Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING[16:2] 1 Write RESET 1111111111111111

56F8037 Data Sheet, Rev. 3

86 Freescale Semiconductor

5.6.16 IRQ Pending Register 1 (IRQP1)

Figure 5-18 IRQ Pending Register 1 (IRQP1)

5.6.16.1 IRQ Pending (PENDING)—Bits 32–17

This register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations.

• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

5.6.17 IRQ Pending Register 2 (IRQP2)

Figure 5-19 IRQ Pending Register 2 (IRQP2)

5.6.17.1 IRQ Pending (PENDING)—Bits 48–33

This register bit values represent the pending IRQs for interrupt vector numbers 33 through 48. Ascending IRQ numbers correspond to ascending bit locations.

• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

5.6.18 IRQ Pending Register 3 (IRQP3)

Figure 5-20 IRQ Pending Register 3 (IRQP3)

5.6.18.1 IRQ Pending (PENDING)—Bits 63–49

This register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending IRQ numbers correspond to ascending bit locations.

• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number Base + $F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING[32:17] Write RESET 1111111111111111 Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING[48:33] Write RESET 1111111111111111 Base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING[63:49] Write RESET 1111111111111111

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 87 Preliminary

5.6.19 Interrupt Contro l Register (ICTRL)

Figure 5-21 Interrupt Control Register (ICTRL)

5.6.19.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

• 0 = No interrupt is be ing sent to the 56800E core
• 1 = An interrupt is be ing sent to the 56800E core

5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed fo r a new IRQ to interrupt the current interrupt being sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it.

• 00 = Required nested exception prio rity levels are 0, 1, 2, or 3
• 01 = Required nested exception pr iority levels are 1, 2, or 3
• 10 = Required nested exceptio n priority levels are 2 or 3
• 11 = Required nested exception priority level is 3

5.6.19.3 Vector Number - Vec tor Address Bus (VAB)—Bits 12–6

This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken. In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. $Base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INT IPIC VAB INT_ DIS 1 1 1 0 0 Write RESET 0000000000011100 Table 5-4 Interrupt Priority Encoding IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority

56F8037 Data Sheet, Rev. 3

88 Freescale Semiconductor

5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

• 0 = Normal operation (default)
• 1 = All interrupts disabled

5.6.19.5 Reserved—Bits 4-2

This bit field is reserved. Each bit must be set to 1.

5.6.19.6 Reserved—Bits 1–0

This bit field is reserved. Each bit must be set to 0.

5.7 Resets

5.7.1 General

5.7.2 Description of Reset Operation

5.7.2.1 Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-22. Figure 5-22 Reset Interface Table 5-5 Reset Summary Reset Priority Source Characteristics Core Reset RST Core reset from the SIM RES CLK VAB PAB RESET_VECTOR_ADR READ_ADR

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 89 Preliminary

5.7.3 ITCN After Reset

After reset, all of the ITCN regist ers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities:

• Illegal Instruction
• SW Interrupt 3
• HW Stack Overflow
• Misaligned Long Word Access
• SW Interrupt 2
• SW Interrupt 1
• SW Interrupt 0
• SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM)

6.1 Introduction

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module’s functions are discussed in more detail in the following sections.

56F8037 Data Sheet, Rev. 3

90 Freescale Semiconductor

6.2 Features

The SIM has the following features:

• Chip reset sequencing
• Core and peripheral clock control and distribution
• Stop/Wait mode control
• System status control
• Registers containing the JTAG ID of the chip
• Controls for programmable peripheral and GPIO connections
• Peripheral clocks for TMR and PWM with a high-speed (3X) option
• Power-saving clock gating for peripherals
• Three power modes (Run, Wait, St op) to control power utilization — Stop mode shuts down the 56800E core, system clock, and peripheral clock — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full device operation
• Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection capability
• Controls the enable/disable functio ns of Large Regulator Standby mode with write protection capability
• Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts
• Controls for programmable peripheral and GPIO connections
• Software chip reset
• I/O short address ba se location control
• Peripheral protection control to provide runaway code protection for safety-critical applications
• Controls output of internal clock sources to CLKO pin
• Four general-purpose software control registers are reset only at power-on
• Peripherals Stop mode clocking control

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 91 Preliminary

6.3 Register Descriptions

A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.3.3 SWC3 $5 Software Control Register 3 6.3.3 MSHID $6 Most Significant Half of JTAG ID 6.3.4 LSHID $7 Least Signific ant Half of JTAG ID 6.3.5 PWR $8 Power Control Register 6.3.6 Reserved CLKOUT $A CLKO Select Register 6.3.7 PCR $B Peripheral Clock Rate Register 6.3.8 PCE0 $C Peripheral Clock Enable Register 0 6.3.9 PCE1 $D Peripheral Clock Enable Register 0 6.3.10 SD0 $E Stop Disable Register 0 6.3.11 SD1 $F Stop Disable Register 1 6.3.12 IOSAHI $10 I/O Short Address Location High Register 6.3.13 IOSALO $11 I/O Short Address Location Low Register 6.3.14 PROT $12 Protection Register 6.3.15 GPSA0 $13 GPIO Peripheral Sele ct Register 0 for GPIOA 6.3.16 GPSA1 $14 GPIO Peripheral Sele ct Register 1 for GPIOA 6.3.17 GPSB0 $15 GPIO Peripheral Sele ct Register 0 for GPIOB 6.3.18 GPSB1 $16 GPIO Peripheral Sele ct Register 1 for GPIOB 6.3.19 GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD 6.3.20 IPS0 $18 Internal Peripheral Source Select Register 0 for PWM 6.3.21 IPS1 $19 Internal Peripheral Source Select Register 1 for DACs 6.3.22 IPS2 $1A Internal Peripheral Source Select Register 2 for Quad Timer A 6.3.23 Reserved

56F8037 Data Sheet, Rev. 3

92 Freescale Semiconductor

Figure 6-1 SIM Register Map Summary Add. Offset Address Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 SIM_ CTRL R 0 0 0 0 0 0 0 0 0 0 ONCE EBL0 SW RST STOP_ DISABLE WAIT_ DISABLEW $1 SIM_ RSTAT R 0 0 0 0 0 0 0 0 0 SWR COP_ TOR COP_ LOR EXTR POR 0 0 W $2 SIM_SWC0 R Software Control Data 0 W $3 SIM_SWC1 R Software Control Data 1 W $4 SIM_SWC2 R Software Control Data 2 W $5 SIM_SWC3 R Software Control Data 3 W $6 SIM_MSHID R 0 0 0 0 0 001 1 1110010 W $7 SIM_LSHID R 1 0 0 0 0 000 0 0011101 W $8 SIM_PWR R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRSTDBY W Reserved $A SIM_ CLKOUT R 0 0 0 0 0 0 PWM3P W M2P W M 1P W M 0 CLK DIS CLKOSEL $B SIM_PCR R TMRB_ CR TMRA_ CR PWM_C R I2C_ CR 0 0 0 0 0 0 0 0 0 0 0 0 W $C SIM_PCE0 R CMPB CMPA DAC1 DAC0 ADC 0 0 0 I2C QSCI1 QSCI0 QSPI1 QSPI0 PWM W $D SIM_PCE1 R 0 PIT2 PIT1 PIT0 0 0 0 0 TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0 W $E SIM_SD0 R CMPB_ SD CMPA_ SD DAC1_S D DAC0_ SD

0 ADC_

0 0 0 I2C_ SD QSCI1 _SD QSCI0 _SD QSPI1 _SD QSPI0 _SD

0 PWM_

$F SIM_SD1 R 0 PIT2_ SD PIT1_S D PIT0_ SD 0 0 0 0 TB3_ SD TB2_ SD TB1_ SD TB0_ SD TA3_ SD TA2_ SD TA1_ SD TA0_ SDW $10 SIM_IOSAHI R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISAL[23:22] W $11 SIM_IOSALO R ISAL[21:6] W $12 SIM_PROT R 0 0 0 0 0 0 0 0 0 0 0 0 PCEP GIPSP W $13 SIM_GPSA0 R 0 0 0 GPS_ A6 GPS_A5 GPS_A4 0 0 0 0 0 0 0 0 W $14 SIM_GPSA1 R 0 0 GPS_A14 GPS_A13 GPS_A12

0 GPS_

A10 GPS_A9 GPS_A8 W $15 SIM_GPSB0 R 0 GPS_B6 GPS_B5 GPS_B4 GPS_B3 GPS_B2 $16 SIM_GPSB1 R 0 0 0 0 0 0 0 GPS_ B11 $17 SIM_GPSCD R 0 0 0 GPS_ 0 0 0 0 0 0 0 GPS_ C12 W $18 SIM_IPS0 R 0 0 IPS0_ FAULT2

0 IPS0_

IPS0_PSRC2 IPS0_PSRC1 IPS0_PSRC0 W $19 SIM_IPS1 R 0 0 0 0 0 0 0 0 0 IPS1_DSYNC1 IPS1_DSYNC0 W $1A SIM_IPS2 R 0 0 0 IPS2_ TA3 0 0 0 IPS2_ TA2 0 0 0 IPS2_ TA1 0 0 0 0 W Reserved 0 = Read as 0 1 = Read as 1 = Reserved

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 93 Preliminary

6.3.1 SIM Control Register (SIM_CTRL)

Figure 6-2 SIM Control Register (SIM_CTRL)

6.3.1.1 Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

6.3.1.2 OnCE Enable (ONCEEBL)—Bit 5

• 0 = OnCE clock to 56800E core en abled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled Note: Using default state “0” is recommended.

6.3.1.3 Software Reset (SWRST)—Bit 4

• Writing 1 to this field will cause the device to reset
• Read is zero

6.3.1.4 Stop Disable (S TOP_DISABLE)—Bits 3–2

• 00 = Stop mode will be entered when the 56800E core executes a STOP instruction
• 01 = The 56800E STOP instruction will not cause entry into Stop mode
• 10 = Stop mode will be entered when the 5680 0E core executes a STOP instruction and the STOP_DISABLE field is write-protected until the next reset
• 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is write-protected until the next reset

6.3.1.5 Wait Disable (WAIT_DISABLE)—Bits 1–0

• 00 = Wait mode will be entered when th e 56800E core executes a WAIT instruction
• 01 = The 56800E WAIT instructio n will not cause entry into Wait mode
• 10 = Wait mode will be entered when the 568 00E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset
• 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset

6.3.2 SIM Reset Status Register (SIM_RSTAT)

This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular rese t vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST STOP_ DISABLE WAIT_ DISABLEWrite RESET 0 00000 0 0 0 0 0 0 000 0

56F8037 Data Sheet, Rev. 3

94 Freescale Semiconductor

most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is Power-On Reset, External Reset, COP Loss of Re ference Reset, COP Time-O ut Reset, and Software Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On Reset has deasserted. Figure 6-3 SIM Reset Status Register (SIM_RSTAT)

6.3.2.1 Reserved—Bits 15–7

This bit field is reserved. Each bit must be set to 0.

6.3.2.2 Software Reset (SWR)—Bit 6

When set, this bit indicates that the previous system reset occurred as a result of a software reset (written 1 to SWRST bit in the SIM_CTRL register).

6.3.2.3 COP Time-Out Reset (COP_TOR)—Bit 5

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.4 COP Loss of Refere nce Reset (COP_LOR)—Bit 4

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.5 External Reset (EXTR)—Bit 3

When set, this bit indicates that the previous system reset was caused by an external reset.

6.3.2.6 Power-On Reset (POR)—Bit 2

This bit is set during a Power-On Reset.

6.3.2.7 Reserved—Bits 1–0

This bit field is reserved. Each bit must be set to 0. Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 SWR COP_ TOR COP_ LOR EXTR POR 0 0 Write RESET 0 00000 0 0 0 0 0 0 01 0 0

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 95 Preliminary

6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1,

SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow. Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)

6.3.3.1 Software Control Register 0 - 3 (FIELD)—Bits 15–0

This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to contain data that will be unaffected by the other reset sources (ext ernal reset, software reset, and COP reset).

6.3.4 Most Significant Half of JTAG ID (SIM_MSHID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2. Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)

6.3.5 Least Significant Half of JTAG ID (SIM_LSHID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $801D. Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Software Control Data 0 - 3 Write RESET 0 0 0 0 0 0 00000 0 0000 Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 01111 1 0010 Write RESET 0 0 0 0 0 0 01111 1 0010 Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 0 0 0 0 0 00000 1 1101 Write RESET 1 0 0 0 0 0 00000 1 1101

56F8037 Data Sheet, Rev. 3

96 Freescale Semiconductor

6.3.6 SIM Power Control Register (SIM_PWR)

This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption. Refer to the overview of power-down modes and the overview of clock generation for more information on the use of large regulator standby. Figure 6-7 SIM Power Control Register (SIM_PWR)

6.3.6.1 Reserved—Bits 15–2

This bit field is reserved. Each bit must be set to 0.

6.3.6.2 Large Regulator Sta ndby Mode[1:0] (LRSTDBY)—Bits 1–0

• 00 = Large regulator is in Normal mode
• 01 = Large regulator is in Standby (reduced-power) mode
• 10 = Large regulator is in Normal mode and the LR STDBY field is write-protected until the next reset
• 11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset

6.3.7 Clock Output Sele ct Register (SIM_CLKOUT)

The Clock Output Select register can be used to multiplex out selected clock sources generated inside the clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source to the output is unspecified. The observability of the CLKO clock output signal at an output pad is subject to the frequency limitations of the associated IO cell. GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for the peripheral function of GPIOA[3: 0] to be programmed as PWM (sel ected by bits [9:6] of the Clock Output Select register). GPIOB4 can function as GPIO, or as other peripheral outputs, including clock output (CLKO). If GPIOB4 is programmed to operate as a pe ripheral output and CLKO is selected in the SIM_GPSB0 register, bits [4:0] decide if CLKO is enabled or disabled and which clock source is selected if CLKO is enabled. See Figure 6-8 for details. Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRSTDBY Write RESET 0000000000000000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 97 Preliminary Figure 6-8 CLKO Select Register (SIM_CLKOUT)

6.3.7.1 Reserved—Bits 15–10

This bit field is reserved. Each bit must be set to 0.

6.3.7.2 PWM 3—Bit 9

• 0 = Peripheral output function of GPIOA[3] is defined to be PWM 3
• 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock

6.3.7.3 PWM 2—Bit 8

• 0 = Peripheral output function of GPIOA[2] is defined to be PWM 2
• 1 = Peripheral output function of GPIOA[2] is defined to be the system clock

6.3.7.4 PWM 1—Bit 7

• 0 = Peripheral output function of GPIOA[1] is defined to be PWM 1
• 1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock

6.3.7.5 PWM 0—Bit 6

• 0 = Peripheral output function of GPIOA[0] is defined to be PWM 0
• 1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock

6.3.7.6 Clockout Disable (CLKDIS)—Bit 5

• 0 = CLKOUT output function is enabled and will output the signal indicated by CLKOSEL
• 1 = CLKOUT output function is disabled

6.3.7.7 Clockout Select (CLKOSEL)—Bits 4–0

CLKOSEL selects clock to be muxed out on the CLKO pin as defined in the following. Internal delay to CLKO output is unspecified. Signal at the output pad is undefined when CLKO signal frequency exceeds the rated frequency of the I/O cel l. CLKO may not operate as exp ected when CLKDIS and CLKOSEL settings are changed.

• 00000 = Continuous system clock
• 00001 = Continuous peripheral clock
• 00010 = 3X system clock Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 PWM3P W M 2P W M 1P W M 0 CLK DIS CLKOSEL Write RESET 0 0 0 0 0 0 0 0 0 0 100000

56F8037 Data Sheet, Rev. 3

98 Freescale Semiconductor

6.3.8 Peripheral Clock Ra te Register (SIM_PCR)

By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it. Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured. Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)

6.3.8.1 Quad Timer B Clock Rate (TMRB_CR)—Bit 15

This bit selects the clock speed for the Quad Timer B module.

• 0 = Quad Timer B clock rate equals the sy stem clock rate, to a maximum 32MHz (default)
• 1 = Quad Timer B clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14

This bit selects the clock speed for the Quad Timer A module.

• 0 = Quad Timer A clock rate equals the sy stem clock rate, to a maximum 32MHz (default)
• 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13

This bit selects the clock speed for the PWM module.

• 0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)
• 1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.4 Inter-Integrated Circui t Run Clock Rate (I2C_CR)—Bit 12

This bit selects the clock speed for the I2C run clock.

• 0 = I 2C module run clock rate equals the system clock rate, to a maximum 32MHz (default)
• 1 = I 2C module run clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.5 Reserved—Bits 11–0

This bit field is reserved. Each bit must be set to 0. Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRB_ CR TMRA_ CR PWM_ CR I2C_ CR 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 0 0 0000 0 0 00 0 0 0 0 0 0

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 99 Preliminary

6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0)

The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use. When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock is shut off. IPBus writes are not possible. Setting the PCE bit does not guarantee that the pe ripheral’s clock is running. Enabled peripheral clocks will still become disabled in Stop mode, unless the periphe ral’s Stop Disable control in the SDn register is set to 1. Note: The MSCAN module supports extended power management capabilities, including Sleep, Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. Refer to the 56F802x and 56F803x Peripheral Reference Manual for details. Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)

6.3.9.1 Comparator B Clock Enable (CMPB)—Bit 15

• 0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)
• 1 = The clock is enabled to the Comparator B module

6.3.9.2 Comparator A Clock Enable (CMPA)—Bit 14

• 0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)
• 1 = The clock is enabled to the Comparator A module

6.3.9.3 Digital-to-Analog Cl ock Enable 1 (DAC1)—Bit 13

• 0 = The clock is not provided to the DA C1 module (the DAC1 module is disabled)
• 1 = The clock is enabled to the DAC1 module

6.3.9.4 Digital-to-Analog Cl ock Enable 0 (DAC0)—Bit 12

• 0 = The clock is not provided to the DA C0 module (the DAC0 module is disabled)
• 1 = The clock is enabled to the DAC0 module

6.3.9.5 Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.9.6 Analog-to-Digital Conver ter Clock Enable (ADC)—Bit 10

• 0 = The clock is not provided to the ADC module (the ADC module is disabled)
• 1 = The clock is enabled to the ADC module Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read CMPB CMPA DAC1 DAC0 ADC 0 0 0 I2C QSCI1 QSCI0 QSPI1 QSPI0 PWM Write RESET 0 0 00000 0 00 0 0 0 00 0

56F8037 Data Sheet, Rev. 3

100 Freescale Semiconductor

6.3.9.7 Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.9.8 Inter-Integrated Circui t IPBus Clock Enable (I2C)—Bit 6

• 0 = The clock is not provided to the I 2C module (the I2C module is disabled)
• 1 = The clock is enabled to the I 2C module

6.3.9.9 QSCI 1 Clock Enable (QSCI1)—Bit 5

• 0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled)
• 1 = The clock is enabled to the QSCI1 module

6.3.9.10 QSCI 0 Clock Enable (QSCI0)—Bit 4

• 0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
• 1 = The clock is enabled to the QSCI0 module

6.3.9.11 QSPI 1 Clock Enable (QSPI1)—Bit 3

• 0 = The clock is not provided to the QS PI1 module (the QSPI1 module is disabled)
• 1 = The clock is enabled to the QSPI1 module

6.3.9.12 QSPI 0 Clock Enable (QSPI0)—Bit 2

• 0 = The clock is not provided to the QS PI0 module (the QSPI0 module is disabled)
• 1 = The clock is enabled to the QSPI0 module

6.3.9.13 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.9.14 PWM Clock Enable (PWM)—Bit 0

• 0 = The clock is not provided to the PWM module (the PWM module is disabled)
• 1 = The clock is enabled to the PWM module

6.3.10 Peripheral Clock Enab le Register 1 (SIM_PCE1)

See Section 6.3.9 for general information about Peripheral Clock Enable registers. Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1) Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 PIT2 PIT1 PIT0 0 0 0 0 TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0 Write RESET 0000000 0 000 00 00 0

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 101 Preliminary

6.3.10.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.10.2 Programmable Interval Ti mer 2 Clock Enable (PIT2)—Bit 14

• 0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled)
• 1 = The clock is enabled to the PIT2 module

6.3.10.3 Programmable Interval Ti mer 1 Clock Enable (PIT1)—Bit 13

• 0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled)
• 1 = The clock is enabled to the PIT1 module

6.3.10.4 Programmable Interval Ti mer 0 Clock Enable (PIT0)—Bit 12

• 0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)
• 1 = The clock is enabled to the PIT0 module

6.3.10.5 Reserved—Bits 11–8

This bit field is reserved. Each bit must be set to 0.

6.3.10.6 Quad Timer B, Channel 3 Clock Enable (TB3)—Bit 7

• 0 = The clock is not provided to the Timer B3 module (the Timer B3 module is disabled)
• 1 = The clock is enabled to the Timer B3 module

6.3.10.7 Quad Timer B, Channel 2 Clock Enable (TB2)—Bit 6

• 0 = The clock is not provided to the Timer B2 module (the Timer B2 module is disabled)
• 1 = The clock is enabled to the Timer B2 module

6.3.10.8 Quad Timer B, Channel 1 Clock Enable (TB1)—Bit 5

• 0 = The clock is not provided to the Timer B1 module (the Timer B1 module is disabled)
• 1 = The clock is enabled to the Timer B1 module

6.3.10.9 Quad Timer B, Channel 0 Clock Enable (TB0)—Bit 4

• 0 = The clock is not provided to the Timer B0 module (the Timer B0 module is disabled)
• 1 = The clock is enabled to the Timer B0 module

6.3.10.10 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3

• 0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)
• 1 = The clock is enable d to the Timer A3 module

6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2

• 0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)
• 1 = The clock is enable d to the Timer A2 module

56F8037 Data Sheet, Rev. 3

102 Freescale Semiconductor

6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1

• 0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)
• 1 = The clock is enable d to the Timer A1 module

6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0

• 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
• 1 = The clock is enable d to the Timer A0 module

6.3.11 Stop Disable Register 0 (SD0)

By default, peripheral cl ocks are disabled during Stop mode in order to maximize power savings. This register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the system to return to Run mode, this feature is provided so that selected peripherals can be left operating in Stop mode for the purpose of generating a wake-up interrupt. For power-conscious applications, it is recommended that only a minimum set of peripherals be configured to remain operational during Stop mode. Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless their corresponding Stop Disable cont rol is set to 1. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. R eads and writes cannot be made to a module that has its clock disabled. Note: The MSCAN module supports extended power management capabilities including Sleep, Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For details, refer to the 56F802x and 56F803x Peripheral Reference Manual. Figure 6-12 Stop Disable Register 0 (SD0)

6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)—Bit 15

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.2 Comparator A Clock Stop Disable (CMPA_SD)—Bit 14

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read CMPB_ SD CMPA_ SD DAC1_ SD DAC0_ SD

0 0 0 I2C_ SD QSCI1 _SD QSCI0 _SD QSPI1 _SD QSPI0 _SD RESET 0 0 0 0 000 0 00 0 0 0 00 0

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 103 Preliminary

6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.5 Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.11.6 Analog-to-Digital Converte r Clock Stop Disable (ADC_SD)—Bit 10

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.7 Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.9 QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

56F8037 Data Sheet, Rev. 3

104 Freescale Semiconductor

6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2

Each bit controls clocks to the indicated peripheral.

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.11.13 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE0 register

6.3.12 Stop Disable Register 1 (SD1)

See Section 6.3.11 for general information about Stop Disable Registers. Figure 6-13 Stop Disable Register 1 (SD1)

6.3.12.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register Base + $F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 PIT2_ SD PIT1_ SD PIT0_ SD 0 0 0 0 TB3_ SD TB2_ SD TB1_ SD TB0_ SD TA3_ SD TA2_ SD TA1_ SD TA0_ SDWrite RESET 000 00 0 000 00000 00

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 105 Preliminary

6.3.12.5 Reserved—Bits 11–8

This bit field is reserved. Each bit must be set to 0.

6.3.12.6 Quad Timer B, Channel 3 Clock Stop Disable (TB3_SD)—Bit 7

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.7 Quad Timer B, Channel 2 Clock Stop Disable (TB2_SD)—Bit 6

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.8 Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)—Bit 5

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.9 Quad Timer B, Channel 0 Clock Stop Disable (TB0_SD)—Bit 4

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.10 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.11 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.12 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

6.3.12.13 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0

• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the cl ock to this peripheral is enabled in the SIM_PCE1 register

56F8037 Data Sheet, Rev. 3

106 Freescale Semiconductor

6.3.13 I/O Short Address Locatio n Register High (SIM_IOSAHI)

In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area in peripheral space with single word instruction. Short address location registers specify the upper 18 bits of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address mode, regardless of the physical location of the peripheral, as shown in Figure 6-14. Figure 6-14 I/O Short Address Determination With this register set, software can set the SIM_IOSAHI and SIM_IO SALO registers to point to its peripheral registers and then use the I/O short addressing mode to access them. Note: The default value of this register set points to the EOnCE registers. Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is five instruction cycles. Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)

6.3.13.1 Reserved—Bits 15—2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.13.2 Input/Output Short Addres s Location (ISAL[23:22])—Bits 1–0

This field represents the upper two address bits of the “hard coded” I/O short address. Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISAL[23:22] Write RESET 0000000 00000 0 0 11 Instruction Portion“Hard Coded” Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_IOSALO Register

2 bits from SIM_IOSAHI Register Full 24-Bit for Short I/O Address

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 107 Preliminary

6.3.14 I/O Short Address Locat ion Register Low (SIM_IOSALO)

See Section 6.3.13 for general information about I/O short address location registers. Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)

6.3.14.1 Input/Output Short Addres s Location (ISAL[21:6])—Bits 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.3.15 Protection Register (SIM_PROT)

This register provides write protec tion of selected contro l fields for safety-cr itical applications. The primary purpose is to prevent uns afe conditions due to the unintenti onal modification of these fields between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP) field protects the SIM registers’ contents, which contain peripheral cloc k controls. Some peripherals provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for details. Flexibility is provided so that write protection control values may themselves be optionally locked (write-protected). Protection controls in this register have two bit values which determine the setting of the control and whether the value is locked. While a protection control remains unlocked, protection can be disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by a chip reset, which restores its default non-locked value. Figure 6-17 Protection Register (SIM_PROT)

6.3.15.1 Reserved—Bits 15–4

This bit field is reserved. Each bit must be set to 0. Base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ISAL[21:6] Write RESET 1111111 11111 1 1 11 Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 PCEP GIPSP Write RESET 0 0 0 0 00000000 0000

56F8037 Data Sheet, Rev. 3

108 Freescale Semiconductor

6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2

These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.

• 00 = Write protection off (default)
• 01 = Write protection on
• 10 = Write protection off and locked until chip reset
• 11 = Write protection on and locked until chip reset

6.3.15.3 GPIO and Internal Periphera l Select Protection (GIPSP)—Bits 1–0

These bits enable wr ite protection of GPS n and IPS n registers in the SIM m odule and write protect all GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.

• 00 = Write protection off (default)
• 01 = Write protection on
• 10 = Write protection off and locked until chip reset
• 11 = Write protection on and locked until chip reset Note: The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for in-house test only.

6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)

Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn registers select which peripheral function has control of the I/O. Figure 6-18 illustrates the output path to an I/O pin when an I/O has two peripheral functions. Similar muxing is require d on peripheral function inputs to receive input from the properly selected I/O pin. Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one GPIOA6_PEREN Register GPIOA6 GPIOA6 pin SIM_GPSA0 Register PWM FAULT0 Timer A0

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 109 Preliminary of these I/O must be configured to control that peripheral function. If more than one I/O is configured to control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input signal will be the logical OR and AND of all the I/O signals. Complete lists of I/O muxings are provided in Table 2-3. The GPSn setting can be altered during no rmal operation, but a delay must be inserted between the time when one function is disabled and another function is enabled. Note: After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin. Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)

6.3.16.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0.

6.3.16.2 Configure GPIOA6 (GPS_A6)—Bit 12

This field selects the alternate function for GPIOA6.

• 0 = FAULT0 - PWM FAULT0 Input (default)
• 1 = TA0 - Timer A0

6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10

This field selects the alternate function for GPIOA5.

• 00 = PWM5 - PWM5 (default)
• 01 = FAULT2 - PWM FAULT2 Input
• 10 = TA3 - Timer A3
• 1 1 = R e s e r v e d

6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8

This field selects the alternate function for GPIOA4.

• 00 = PWM4 - PWM4 (default)
• 01 = FAULT1 - PWM FAULT1 Input
• 10 = TA2 - Timer A2
• 1 1 = R e s e r v e d

6.3.16.5 Reserved—Bits 7–0

This bit field is reserved. Each bit must be set to 0. Base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 GPS_A6 GPS_A5 GPS_A4 0 0 0 0 0 0 0 0 Write RESET 0 0 0 0 00000000 0000

56F8037 Data Sheet, Rev. 3

110 Freescale Semiconductor

6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)

6.3.17.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

6.3.17.2 Configure GPIOA14 (GPS_A14)—Bits 13–12

This field selects the alternate function for GPIOA14.

• 00 = TB3 - Timer B3 (default)
• 01 = MOSI1 - QSPI1 Master Out/Slave In
• 10 = TA3 - Timer A3
• 1 1 = R e s e r v e d

6.3.17.3 Configure GPIOA13 (GPS_A13)—Bits 11–10

This field selects the alternate function for GPIOA13.

• 00 = TB2 - Timer B2 (default)
• 01 = MISO1 - QSPI1 Master In/Slave Out
• 10 = TA2 - Timer A2
• 1 1 = R e s e r v e d

6.3.17.4 Configure GPIO A12 (GPS_A12)—Bits 9–8

This field selects the alternate function for GPIOA12.

• 00 = TB1- Timer B1 (default)
• 01 = SCLK1 - QSPI1 Serial Clock
• 10 = TA1 - Timer A1
• 1 1 = R e s e r v e d

6.3.17.5 Reserved—Bit 7

This bit field is reserved. It must be set to 0.

6.3.17.6 Configure GPIOA11 (GPS_A11)—Bit 6

This field selects the alternate function for GPIOA11. Base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 GPS_A14 GPS_A13 GPS_A12 A10 GPS_A9 GPS_A8 Write RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 111 Preliminary

• 0 = CMPBI2 - Comparator B Input 2 (default)
• 1 = TB3 - Timer B3

6.3.17.7 Reserved—Bit 5

This bit field is reserved. It must be set to 0.

6.3.17.8 Configure GPIOA10 (GPS_A10)—Bit 4

This field selects the alternate function for GPIOA10.

• 0 = CMPAI2- Comparator A Input 2 (default)
• 1 = TB2 - Timer B2

6.3.17.9 Configure GPIOA9 (GPS_A9)—Bits 3–2

This field selects the alternate function for GPIOA9.

• 00 = FAULT2 - PWM FAULT2 Input (default)
• 01 = TA3 - Timer A3
• 10 = CMPBI1 - Comparator B Input 1
• 1 1 = R e s e r v e d

6.3.17.10 Configure GPIOA8 (GPS_A8)—Bits 1–0

This field selects the alternate function for GPIOA8.

• 00 = FAULT1 - PWM FAULT1 Input (default)
• 01 = TA2 - Timer A2
• 10 = CMPAI1 - Comparator A Input 1
• 1 1 = R e s e r v e d

6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)

6.3.18.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.18.2 Configure GPIOB6 (GPS_B6)—Bits 14–13

This field selects the alternate function for GPIOB6. Base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 GPS_B6 GPS_B5 GPS_B4 GPS_B3 GPS_B2 RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3

112 Freescale Semiconductor

• 00 = RXD0 - QSCI0 Receive Data (default)
• 01 = SDA - I2C Serial
• 10 = CLKIN - External Clock Input
• 1 1 = R e s e r v e d

6.3.18.3 Configure GPIOB5 (GPS_B5)—Bits 12–11

This field selects the alternate function for GPIOB5.

• 00 = TA1 - Timer A1 (default)
• 01 = FAULT3 - PWM FAULT3 Input
• 10 = CLKIN - External Clock Input
• 1 1 = R e s e r v e d

6.3.18.4 Configure GP IOB4(GPS_B4)—Bits 10–8

This field selects the alternate function for GPIOB4.

• 000 = TA0 - Timer A0 (default)
• 001 = CLKO - Clock Output
• 0 1 0 = S S1 - QSPI1 Slave Select
• 011 = TB0 - Timer B0
• 100 = PSRC2 - PWM4 / PWM5 Pair External Source
• 11x = Reserved
• 1x1 = Reserved

6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6

This field selects the alternate function for GPIOB3.

• 00 = MOSI0 - QSPI0 Master Out/Slave In (default)
• 01 = TA3 - Timer A3
• 10 = PSRC1 - PWM2 / PWM3 Pair External Source
• 1 1 = R e s e r v e d

6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4

This field selects the alternate function for GPIOB2.

• 00 = MISO0 QSPI0 Master In/Slave Out (default)
• 01 = TA2 - Timer A2
• 10 = PSRC0 - PWM0 / PWM1 Pair External Source
• 1 1 = R e s e r v e d

6.3.18.7 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 113 Preliminary

6.3.18.8 Configure GPIOB1 (GPS_B1)—Bit 2

This field selects the alternate function for GPIOB1.

• 0 = S S 0 - QSPI0 Slave Select (default)
• 1 = SDA - I2C Serial Data

6.3.18.9 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.18.10 Configure GPIOB0 (GPS_B0)—Bits 0

This field selects the alternate function for GPIOB0.

• 0 = SCLK0 - QSPI0 Serial Clock (default)
• 1 = SCL - I 2C Serial Clock

6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)

6.3.19.1 Reserved—Bits 15–9

This bit field is reserved. Each bit must be set to 0.

6.3.19.2 Configure GPIOB11 (GPS_B11)—Bit 8

This field selects the alternate function for GPIOB11.

• 0 = CMPBO - Comparator B Output (default)
• 1 = TB1 - Timer B1

6.3.19.3 Reserved—Bit 7

This bit field is reserved. It must be set to 0.

6.3.19.4 Configure GPIOB10 (GPS_B10)—Bit 6

This field selects the alternate function for GPIOB10.

• 0 = CMPAO - Comparator A Output (default)
• 1 = TB0 - Timer B0

6.3.19.5 Reserved—Bit 5

This bit field is reserved. It must be set to 0. Base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 GPS_ B11 RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3

114 Freescale Semiconductor

6.3.19.6 Configure GPIOB9 (GPS_B9)—Bit 4

This field selects the alternate function for GPIOB9.

• 0 = SDA - I 2C Serial Data (default)
• 1 = MSCANRX - MSCAN Receive Data

6.3.19.7 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.19.8 Configure GPIOB8 (GPS_B8)—Bit 2

This field selects the alternate function for GPIOB8.

• 0 = SCL - I2C Serial Clock (default)
• 1 = MSCANTX - MSCAN Transmit Data

6.3.19.9 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.19.10 Configure GPIOB7 (GPS_B7)—Bit 0

This field selects the alternate function for GPIOB7.

• 0 = TXD0 - QSCI0 Transmit Data (default)
• 1 = SCL - I2C Serial Clock

6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD

(SIM_GPSCD) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)

6.3.20.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0. Base + $17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 GPS_ 0 0 0 0 0 0 0 GPS_ C12 RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 115 Preliminary

6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12

This field selects the alternate function for GPIOD5.

• 0 = XTAL - External Crysta l Oscillator Output (default)
• 1 = CLKIN - External Clock Input

6.3.20.3 Reserved—Bits 11–5

This bit field is reserved. Each bit must be set to 0.

6.3.20.4 Configure GPIOC12 (GPS_C12)—Bit 4

This field selects the alternate function for GPIOC12.

• 0 = ANB4 - ADCB, Channel 4 (default)
• 1 = RXD1 - QSCI1 Receive Data

6.3.20.5 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.20.6 Configure GPIOC8 (GPS_C8)—Bit 2

This field selects the alternate function for GPIOC8.

• 0 = ANA4 - ADCA, Channel 4 (default)
• 1 = TXD1 - QSCI1 Transmit Data

6.3.20.7 Reserved—Bits 1—0

This bit field is reserved. Each bit must be set to 0.

6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width

Modulator (SIM_IPS0) The internal integration of peripherals provides input signal source selection for peripherals where an input signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral type and provide a selection list for every peripheral input signal that has more than one alternative source to indicate which source is selected. If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control of the I/O.

56F8037 Data Sheet, Rev. 3

116 Freescale Semiconductor

Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control IPSn settings should not be altere d while an affected peripheral is in an enabled (operational) configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details. Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0)

6.3.21.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

6.3.21.2 Select Peripheral Input So urce for FAULT2 (IPS0_FAULT2)—Bit 13

This field selects the alternate input source signal to feed PWM input FAULT2.

• 0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default)
• 1 = CMPBO (Internal) - Use Comparator B Output

6.3.21.3 Reserved—Bit 12

This bit field is reserved. It must be set to 0.

6.3.21.4 Select Peripheral Input So urce for FAULT1 (IPS0_FAULT1)—Bit 11

This field selects the alternate input source signal to feed PWM input FAULT1.

• 0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default)
• 1 = CMPAO (Internal) - Use Comparator A Output Base + $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 IPS0_ FAULT2

IPS0_PSRC2 IPS0_PSRC1 IPS0_PSRC0 Write RESET 0 0 0 0 0 0000000 0000 GPIOA5_PEREN Register GPIOA5 GPIOA5 pin SIM_IPS0 Register PWM FAULT2 Comparator A Output (Internal) 101 PWM5 Timer A3 SIM_GPSA0 Register

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 117 Preliminary

6.3.21.5 Reserved—Bits 10–9

This bit field is reserved. Each bit must be set to 0.

6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source

(IPS0_PSRC2)—Bits 8–6 This field selects the alternate input source signa l to feed PWM input PSRC 2 as the PWM4/PWM5 pair source.

• 000 = I/O Pin (External) - Use a PSRC2 input pin as PWM source (default)
• 001 = TA3 (Internal) - Use Ti mer A3 output as PWM source
• 010 = ADC SAMPLE2 (Internal) - Use ADC SAMPLE2 result as PWM source — If the ADC conversion result in SAMPLE2 is greater than the value programmed into the High Limit register HLMT2, then PWM4 is set to 0 and PWM5 is set to 1 — If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0
• 011 = CMPAO (Internal) - Use Comparator A output as PWM source
• 100 = CMPBO (Internal) - Use Co mparator B output as PWM source
• 11x = Reserved
• 1x1 = Reserved

6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source

(IPS0_PSRC1)—Bits 5–3 This field selects the alternate input source signa l to feed PWM input PSRC 1 as the PWM2/PWM3 pair source.

• 000 = I/O pin (External) - Use a PSRC1 input pin as PWM source (default)
• 001 = TA2 (Internal) - Use Ti mer A2 output as PWM source
• 010 = ADC SAMPLE1 (Internal) - Use ADC SAMPLE1 result as PWM source — If the ADC conversion result in SAMPLE1 is greater than the value programmed into the High Limit register HLMT1, then PWM2 is set to 0 and PWM3 is set to 1 — If the ADC conversion result in SAMPLE1 is less than the value programmed into the Low Limit register LLMT2, then PWM2 is set to 1 and PWM3 is set to 0
• 011 = CMPAO (Internal) - Use Comparator A output as PWM source
• 100 = CMPBO (Internal) - Use Comparator B output as PWM source
• 11x = Reserved
• 1x1 = Reserved

6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source

(IPS0_PSRC0)—Bits 2–0 This field selects the alternate input source signa l to feed PWM input PSRC 0 as the PWM0/PWM1 pair source.

• 000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default)

56F8037 Data Sheet, Rev. 3

118 Freescale Semiconductor

• 001 = TA0 (Internal) - Use Ti mer A0 output as PWM source
• 010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source — If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit register HLMT1, then PWM0 is set to 0 and PWM1 is set to 1 — If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit register LLMT2, then PWM0 is set to 1 and PWM1 is set to 0
• 011 = CMPAO (Internal) - Use Comparator A output as PWM source
• 100 = CMPBO (Internal) - Use Comparator B output as PWM source
• 11x = Reserved
• 1x1 = Reserved

6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog

Converters (SIM_IPS1) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)

6.3.22.1 Reserved—Bits 15–7

This bit field is reserved. Each bit must be set to 0.

6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1

(IPS1_DSYNC1)—Bits 6–4 This field selects the alternate input source signal to feed DAC1 SYNC input.

• 000 = PIT0 (Internal) - Use Programmable Interv al Timer 0 Output as DAC SYNC input (default)
• 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
• 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
• 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
• 100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
• 101 = TA1 (Internal) - Use Time r A1 output as DAC SYNC input
• 11x = Reserved

6.3.22.3 Reserved—Bit 3

This bit field is reserved. It must be set to 0. Base + $19 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 IPS1_DSYNC1 IPS1_DSYNC0 Write RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 119 Preliminary

6.3.22.4 Select Peripheral Inpu t Source for SYNC Input to DAC 0

(IPS1_DSYNC0)—Bits 2–0 This field selects the alternate input source signal to feed DAC0 SYNC input.

• 000 = PIT0 (Internal) - Use Programmable Interv al Timer 0 Output as DAC SYNC input (default)
• 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
• 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
• 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
• 100 = TA0 (Internal) - Use Time r A0 output as DAC SYNC input
• 101 = TA1 (Internal) - Use Time r A1 output as DAC SYNC input
• 11x = Reserved

6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A

(SIM_IPS2) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)

6.3.23.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0.

6.3.23.2 Select Peripheral Inpu t Source for TA3 (IPS2_TA3)—Bit 12

This field selects the alternate input source signal to feed Quad Timer A, input 3.

• 0 = I/O pin (External) - Use Timer A3 input/output pin
• 1 = PWM SYNC (Internal) - Use PWM reload synchronization signal

6.3.23.3 Reserved—Bits 11–9

This bit field is reserved. Each bit must be set to 0.

6.3.23.4 Select Peripheral Inpu t Source for TA2 (IPS2_TA2)—Bit 8

This field selects the alternate input source signal to feed Quad Timer A, input 2.

• 0 = I/O pin (External) - Use Timer A2 input/output pin
• 1 = CMPBO (Internal) - Use Comparator B output

6.3.23.5 Reserved—Bits 7–5

This bit field is reserved. Each bit must be set to 0. Base + $1A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 IPS2_ TA3 0 0 0 IPS2_ TA2 0 0 0 IPS2_ TA1 0 0 0 0 Write RESET 0 0 0 000000000 0000

56F8037 Data Sheet, Rev. 3

120 Freescale Semiconductor

6.3.23.6 Select Peripheral Inpu t Source for TA1 (IPS2_TA1)—Bit 4

This field selects the alternate input source signal to feed Quad Timer A, input 1.

• 0 = I/O pin (External) - Use Timer A1 input/output pin
• 1 = CMPAO (Internal) - Use Comparator A output

6.3.23.7 Reserved—Bits 3–0

This bit field is reserved. Each bit must be set to 0. For Timer A to detect the PWM SYNC signal, th e clock rate of both the PWM module and Timer A module must be identical, at either the system clock rate or 3X system clock rate.

6.4 Clock Generation Overview

The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to produce a system clock at a maximum of 32MHz for the peripheral, core and memory. It divides the master clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and can be an optional cl ock for PWM, Timer A, Timer B, and I 2C modules. These clocks are generated by gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls. The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either an external clock (CLKIN), a crysta l oscillator, or the rela xation oscillator can be selected as the master clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full speed (8MHz), standby speed (4 00kHz using ROSB), or powered down (using ROPD). An 8MHz MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master clocks to the SIM. When the PLL is selected, both the 3X system cl ock and the 2X system clock are enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC. In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables, and clock rate controls to provide flexible control of clocking and power utilizat ion. The clock rate controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM, but requires the PLL to be on and selected. Refer to the 56F802x and 56F803x Peri pheral Reference Manual for further details. The peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used.

6.5 Power-Saving Modes

The 56F8037 operates in one of five Power-Saving modes, as shown in Table 6-2.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 121 Preliminary The power-saving modes provide additional power management opt ions by disabl ing the clock, reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2. Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction. Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2. Executing a Debug mode entry command during the 56800E core JTAG interface 3. Any reset (POR, external, software, COP) Stop Master clock generation in the OCCS remains operational, but the SIM disables the generation of system and peripheral clocks. Core executes STOP instruction to enter this mode. Possible recoveries from Stop mode to Run mode are: 1. Interrupt from any peripheral configured in the CTRL register to operate in Stop mode (TA0-3, QSCI0, PIT0-1, CAN, CMPA-B) 2. Low-voltage interrupt 3. Executing a Debug mode entry command using the 56800E core JTAG interface 4. Any reset (POR, external, software, COP) Standby The OCCS generates the master clock at a reduced frequency (400kHz). The PLL is disabled and the high-speed peripheral option is not available. System and peripheral clocks operate at 200kHz. The user configures the OCCS and SIM to select the relaxation oscillator clock source (PRECS), shut down the PLL (PLLPD), put the relaxation oscillator in Standby mode (ROSB), and put the large regulator in Standby (LRSTDBY). The device is fully operational, but operating at a minimum frequency and power configuration. Recovery requires reversing the sequence used to enter this mode (allowing for PLL lock time). Power-Down Master clock generation in the OCCS is completely shut down. All system and peripheral clocks are disabled. The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset

56F8037 Data Sheet, Rev. 3

122 Freescale Semiconductor

A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the device and minimizes its power utilization but is only recoverable via reset. When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator. All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system clock for PWM, Timers, and I2C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of operation is 32MHz.

6.6 Resets

The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). Th e three synchronous sources are the software reset (SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, the COP time-out reset (COP_TOR), and the CO P loss-of-reference reset (COP_LOR). The reset generation module has three reset detectors, which resolve into four primary resets. These are outlined in Table 6-3. The JTAG circuitry is reset by the Power-On Reset. Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset. Table 6-3 Primary System Resets Reset Sources Reset Signal POR External Software COP Comments EXTENDED_POR X Stretched version of POR released 64 OSC_CLK cycles after POR deasserts CLKGEN_RST XXXX R e l e a s e d 3 2 O S C _ C L K c y c l e s a f t e r a l l r e s e t sources, including EXTENDED_POR, have released PERIP_RST XXXX R e l e a s e s 3 2 SYS_CLK cycles after the CLKGEN_RST is released CORE_RST XXXX R e l e a s e s 3 2 SYS_CLK cycles after PERIP_RST is released

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 123 Preliminary Figure 6-28 Sources of RESET Functional Diagram (Test modes not included) POR resets are extended 64 OSC_CL K clocks to stabilize the power supply and clock source. All resets are subsequently extended for an additional 32 OSC_CLK clocks and 64 system cloc ks as the various internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset from when power comes on to when code is running is 28 µS. An external reset generation circuit may also be used. A description of how these resets are used to initialize the clocking system and system modules is included in Section 6.7.

6.7 Clocks

The memory, peripheral and core cl ocks all operate at the same fre quency (32MHz maximum) with the exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option to operate at 3X system clock. The SIM is responsible for clock distributions. While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion cloc ks are generated by a direct in terface between the ADC and the OCCS module. EXTENDED_POR JTAG Memory Subsystem Peripherals 56800E CORE_RST Delay 32 sys clocks OCCS CLKGEN_RST PERIP_RST Delay 32 sys clocks pulse shaper pulse shaper SW Reset pulse shaper Delay 32 OSC_CLK Clock pulse shaper POR Power-On Reset (active low) External RESET IN (active low) RESET Delay 64 OSC_CLK Clock Delay blocks assert immediately and deassert only after the programmed number of clock cycles. COMBINED_RST COP_LOR (active low) COP_TOR (active low)

56F8037 Data Sheet, Rev. 3

124 Freescale Semiconductor

The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxa tion Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of th e POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an additional time period for the clock source and power to stabilize. 3. A Combined reset consists of the OR of the exte nded POR reset, the external reset, the COP reset and Software reset. The entire device, except for the POR extender, is held reset as long as Combined reset is asserted. The release of Combined reset permits operation of the CTRL register, the Synchronous reset generator, and the CLKGEN reset extender. 4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This provides a reasonable minimum duration to the reset for these specialized functions. 5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a window in which the SIM stabilizes the master clock inputs to the clock generator. 6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32 SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic remain clocked, but in reset, so that synchronous resets can be resolved. 7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender. The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the Peripheral reset. This provides a window in which critical peripheral start-up functions, such as Flash Security in the Flash memory, can be implemented. 8. The release of Core reset permits execution of c ode by the 56800E core and marks the end of the system start-up sequence. Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external reset, COP and Software reset). In the 56F8037, this signal will be stretched by the SIM for a period of time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock generation reset signal (CLKGEN_RST ). The SIM should deassert CLKGEN_RST synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of sy stem resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 125 Preliminary Figure 6-29 Timing Relationships of Reset Signal to Clocks

6.8 Interrupts

The SIM generates no interrupts. Part 7 Security Features The 56F8037 offers security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The 56F8037’s Flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the Flash array. Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s code that includes a subroutine to read and transfer the contents of the internal program to QSCI, QSPI or another peripheral, as this code would defeat the purpose of security. At the same time, the user may also wish to put a “backdoor” in his program. As an example, the user dow nloads a security key through the QSCI, allowing access to a programming routine that updates parameters stored in another section of the Flash.

7.1 Operation with Security Enabled

Once the user has programmed the Flash with his application c ode, the 56F8037 can be secured by programming the security bytes locate d in the FM configurat ion field, which are lo cated at the last nine words of Program Flash. These non-volatile bytes will keep the device secured through reset and through RST MSTR_OSC CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 PERIP_RST CORE_RST Switch on falling OSC_CLK

96 MSTR_OSC cycles

Switch on falling SYS_CLK

32 SYS_CLK cycles delay

Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension Switch on falling SYS_CLK

56F8037 Data Sheet, Rev. 3

126 Freescale Semiconductor

power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module chapter, the 56F8037 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.

7.2 Flash Access Lock and Unlock Mechanisms

The 56F8037 has several operating f unctional and debug modes. Effectiv e Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be read without explicit user permission.

7.2.1 Disabling EOnCE Access

On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the 56F8037 boots, the chip-l evel JTAG TAP (Test Access Port) is active and provides the chip’s boun dary scan capability and access to the ID register, but proper implementation of Flash s ecurity will block any a ttempt to access the internal Flash memory via the EOnCE port when security is enabled.

7.2.2 Flash Lockout Recovery Using JTAG

If a user inadvertently enables security on th e 56F8037, the only lockout reco very mechanism is the complete erasure of the internal Flash contents, including the configuration field, and thus disables security (the protection register is cleared). This does not compromise security, as the entire contents of the user’s secured code stored in Flash are erased before security is disabled on the 56F8037 on the next reset or power-up sequence. To start the lockout recovery sequence, the JTAG public inst ruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP c ontroller’s instruction register. Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. Refer to the 56F802x and 56F803x Peripheral Reference Manual for more details, or contact Freescale. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by advancing the TAP state machine to the reset state) and the 56F8037 (by asserting external chip reset) to return to normal unsecured operation.

7.2.3 Flash Lockout Recovery using CodeWarrior

CodeWarrior can unlock a device using the command sequence described in Section 7.2.2 by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built in to CodeWarrior using the device’s memory configuration file. The command “Unlock_Flash_on_Connect1” in the .cfg file accomplishes the same task as using the Debug menu.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 127 Preliminary

7.2.4 Product Analysis

The recommended method of unsecuring a programmed 56F8037 for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to acce ss the backdoor routine in the Flash. A dditionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a s ecured microcontroller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the 56F8037 during programming, it is recommended that the user program the backdoor access key first, the application code second, and the security bytes within the FM configuration field last. Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F802x and 56F803x Peripheral Reference Manual and contains only chip-specific information. This information supersedes the generic information in the 56F802x and 56F803x Peripheral Reference Manual.

8.2 Configuration

There are four GPIO ports defined on the 56F8037. The width of each port, the associated peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2. Additional details are shown in Tables 2-2 and 2-3. Table 8-1 GPIO Ports Configuration GPIO Port Available Pins in 56F8037 Peripheral Function Reset Function A1 5 PWM, Timer, QSPI, Comparator, Reset GPIO, RESET B1 4 QSPI, I2C, PWM, Clock, MSCAN, Comparator, Timer GPIO C1 6 ADC, Comparator, QSCI GPIO D8 Clock, Oscillator, DAC, JTAG GPIO, JTAG

56F8037 Data Sheet, Rev. 3

128 Freescale Semiconductor

Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 56 Defaults to A0 GPIOA1 PWM1 55 Defaults to A1 GPIOA2 PWM2 47 Defaults to A2 GPIOA3 PWM3 48 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 43 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 39 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2. Defaults to A5 GPIOA6 FAULT0 / TA0 34 SIM register SIM_GPS is used to select between FAULT0 and TA0. Defaults to A6 GPIOA7 RESET

31 Defaults to RESET

GPIOA8 FAULT1 / TA2 / CMPAI1 36 SIM register SIM_GPS is used to select between FAULT1, TA2, and CMPAI1. Defaults to A8 GPIOA9 FAULT2 / TA3 / CMPBI1 5 SIM register SIM_GPS is used to select between FAULT2, TA3, and CMPBI1. Defaults to A9 GPIOA10 TB2 / CMPAI2 35 SIM regi ster SIM_GPS is used to select between TB2 and CMPAI2. Defaults to A10 GPIOA11 TB3 / CMPBI2 6 SIM register SIM_GPS is used to select between TB3 and CMPBI2. Defaults to A11 GPIOA12 SCLK1 / TB1 / TA1 37 SIM register SIM_GPS is used to select between SCLK1, TB1, and TA1. Defaults to A12 GPIOA13 MISO1 / TB2 / TA2 44 SIM register SIM_GPS is used to select between MISO1, TB2, and TA2. Defaults to A13 GPIOA14 MOSI1 / TB3 / TA3 45 SIM register SIM_GPS is used to select between MOSI1, TB3, and TA3. Defaults to A14

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 129 Preliminary GPIOB0 SCLK0 / SCL 42 SIM register SIM_GPS is used to select between SCLK and SCL. Defaults to B0 GPIOB1 SS 0 / SDA 2 SIM register SIM_GPS is used to select between SS0 and SDA. Defaults to B1 GPIOB2 MISO0 / TA2 / PSRC0 33 SIM register SIM_GPS is used to select between MISO0, TA2, and PSRC0. Defaults to B2 GPIOB3 MOSI0 / TA3 / PSRC1 32 SIM register SIM_GPS is used to select between MOSI0, TA3 and PSRC1. Defaults to B3 GPIOB4 TA0 / CLKO / SS1 / TB0 / PSRC2

38 SIM register SIM_GPS is used to

select between TA0, CLKO, SS1, TB0, and PSRC2. Defaults to B4 GPIOB5 TA1 / FAULT3 / CLKIN 4 SIM register SIM_GPS is used to select between TA1, FAULT3, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B5 GPIOB6 RXD0 / SDA / CLKIN 1 SIM r egister SIM_GPS is used to select between RXD0, SDA, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B6 GPIOB7 TXD0 / SCL 3 SIM regist er SIM_GPS is used to select between TXD0 and SCL. Defaults to B7 GPIOB8 SCL / CANTX 54 SIM register SIM_GPS is used to select between SCL and CANTX. Defaults to B8 GPIOB9 SDA / CANRX 46 SIM register SIM_GPS is used to select between SDA and CANRX. Defaults to B9 Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes

56F8037 Data Sheet, Rev. 3

130 Freescale Semiconductor

GPIOB10 TB0 / CMPAO 30 SIM register SIM_GPS is used to select between TB0 and CMPAO. Defaults to B10 GPIOB11 TB1 / CMPBO 60 SIM register SIM_GPS is used to select between TB1 and CMPBO. Defaults to B11 GPIOB12 CANTX 57 Defaults to B12 GPIOB13 CANRX 58 Defaults to B13 GPIOC0 ANA0 / CMPAI3 24 SIM register SIM_GPS is used to select between ANA0 and CMPAI3. Defaults to C0 GPIOC1 ANA1 22 Defaults to C1 GPIOC2 ANA2 / V REFHA 20 SIM register SIM_GPS is used to select between ANA2 and VREFHA. Defaults to C2 GPIOC3 ANA3 / V REFLA 19 SIM register SIM_GPS is used to select between ANA3 and VREFLA. Defaults to C3 GPIOC4 ANB0 / CMPBI3 10 SIM register SIM_GPS is used to select between ANB0 and CMPBI3. Defaults to C4 GPIOC5 ANB1 11 Defaults to C5 GPIOC6 ANB2 / V REFHB 13 SIM register SIM_GPS is used to select between ANB2 and VREFHB. Defaults to C6 GPIOC7 ANB3 / V REFLB 14 SIM register SIM_GPS is used to select between ANB3 and VREFLB. Defaults to C7 GPIOC8 ANA4 / TXD1 26 SIM regi ster SIM_GPS is used to select between ANA4 and TXD1. Defaults to C8 GPIOC9 ANA5 21 Defaults to C9 GPIOC10 ANA6 23 Defaults to C10 GPIOC11 ANA7 25 Defaults to C11 GPIOC12 ANB4 / RXD1 9 SIM register SIM_GPS is used to select between ANB4 and RXD1. Defaults to C12 GPIOC13 ANB5 12 Defaults to C13 Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 131 Preliminary

8.3 Reset Values

Tables 8-1 and 8-2 detail registers for the 56F8037; Figures 8-1 through 8-4 summarize register maps and reset values. GPIOC14 ANB6 62 Defaults to C14 GPIOC15 ANB7 61 Defaults to C15 GPIOD0 TDI 59 Defaults to TDI GPIOD1 TDO 64 Defaults to TDO GPIOD2 TCK 29 Defaults to TCK GPIOD3 TMS 63 Defaults to TMS GPIOD4 EXTAL 53 Defaults to D4 GPIOD5 XTAL / CLKIN 52 SIM regi ster SIM_GPSCD is used to select between XTAL and CLKIN. Defaults to D5 GPIOD6 DAC0 18 Defaults to D6 GPIOD7 DAC1 15 Defaults to D7 Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes

56F8037 Data Sheet, Rev. 3

132 Freescale Semiconductor

Figure 8-1 GPIOA Register Map Summary Add. Offset R e g i s t e r A c r o n y m 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 $0 GPIOA_PUPEN R 0 PU[15:0]W RS 0 111111111111111 $1 GPIOA_DATA R .0 D[15:0]W RS 0 000000000000000 $2 GPIOA_DDIR R .0. DD[15:0]W RS 0 000000000000000 $3 GPIOA_PEREN R 0 PE[15:0]W RS 0 000000000000000 $4 GPIOA_IASSRT R 0 IA[15:0]W RS 0 000000000000000 $5 GPIOA_IEN R 0 IEN[15:0]W RS 000000000000000 $6 GPIOA_IEPOL R 0 IEPOL[15:0]W RS 0 000000000000000 $7 GPIOA_IPEND R 0 IPR[15:0] W RS 0 000000000000000 $8 GPIOA_IEDGE R 0 IES[15:0]W RS 0 000000000000000 $9 GPIOA_PPOUTM R 0 OEN[15:0]W RS 0 111111111111111 $A GPIOA_RDATA R 0 RAW DATA[15:0] W RS 0 XXXXXXXXXXXXXXX $B GPIOA_DRIVE R 0 DRIVE[15:0]W RS 0 000000000000000 R 0 Read as 0 W Reserved RS Reset

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 133 Preliminary Figure 8-2 GPIOB Register Map Summary Add. Offset R e g i s t e r A c r o n y m 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 $0 GPIOB_PUPEN R 0 0 PU[15:0]W RS 0 0 11111111111111 $1 GPIOB_DATA R 0 0 D[15:0]W RS 0 0 00000000000000 $2 GPIOB_DDIR R 0 0 DD[15:0]W RS 0 0 00000000000000 $3 GPIOB_PEREN R 0 0 PE[15:0]W RS 0 0 00000000000000 $4 GPIOB_IASSRT R 0 0 IA[15:0]W RS 0 0 00000000000000 $5 GPIOB_IEN R 0 0 IEN[15:0]W RS 0 0 00000000000000 $6 GPIOB_IEPOL R 0 0 IEPOL[15:0]W RS 0 0 00000000000000 $7 GPIOB_IPEND R 0 0 IPR[15:0] W RS 0 0 00000000000000 $8 GPIOB_IEDGE R 0 0 IES[15:0]W RS 0 0 00000000000000 $9 GPIOB_PPOUTM R 0 0 OEN[15:0]W RS 0 0 11111111111111 $A GPIOB_RDATA R 0 0 RAW DATA[15:0] W RS 0 0 XXXXXXXXXXXXXX $B GPIOB_DRIVE R 0 0 DRIVE[15:0]W RS 0 0 00000000000000 R 0 Read as 0 W Reserved RS Reset

56F8037 Data Sheet, Rev. 3

134 Freescale Semiconductor

Figure 8-3 GPIOC Register Map Summary Add. Offset R e g i s t e r A c r o n y m 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 $0 GPIOC_PUPEN R PU[15:0]W R S 1111111111111111 $1 GPIOC_DATA R D[15:0]W R S 0000000000000000 $2 GPIOC_DDIR R DD[15:0]W R S 0000000000000000 $3 GPIOC_PEREN R PE[15:0]W R S 0000000000000000 $4 GPIOC_IASSRT R IA[15:0]W R S 0000000000000000 $5 GPIOC_IEN R IEN[15:0]W R S 0000000000000000 $6 GPIOC_IEPOL R IEPOL[15:0]W R S 0000000000000000 $7 GPIOC_IPEND R IPR[15:0] W R S 0000000000000000 $8 GPIOC_IEDGE R IES[15:0]W R S 0000000000000000 $9 GPIOC_PPOUTM R OEN[15:0]W R S 1111111111111111 $A GPIOC_RDATA R RAW DATA[15:0] W R S XXXXXXXXXXXXXXXX $B GPIOC_DRIVE R DRIVE[15:0]W R S 0000000000000000 R 0 Read as 0 W Reserved RS Reset

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 135 Preliminary Figure 8-4 GPIOD Register Map Summary Add. Offset R e g i s t e r A c r o n y m 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 $0 GPIOD_PUPEN R PU[15:0]W RS 0 0 0 0 0 0 0 0 11111111 $1 GPIOD_DATA R D[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $2 GPIOD_DDIR R DD[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $3 GPIOD_PEREN R PE[15:0]W RS 0 0 0 0 0 0 0 0 00001111 $4 GPIOD_IASSRT R IA[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $5 GPIOD_IEN R IEN[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $6 GPIOD_IEPOL R IEPOL[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $7 GPIOD_IPEND R IPR[15:0] W RS 0 0 0 0 0 0 0 0 00000000 $8 GPIOD_IEDGE R IES[15:0]W RS 0 0 0 0 0 0 0 0 00000000 $9 GPIOD_PPOUTM R OEN[15:0]W RS 0 0 0 0 0 0 0 0 11111111 $A GPIOD_RDATA R RAW DATA[15:0] W RS 0 0 0 0 0 0 0 0 XXXXXXXX $B GPIOD_DRIVE R DRIVE[15:0]W RS 0 0 0 0 0 0 0 0 00000000 R 0 Read as 0 W Reserved RS Reset

56F8037 Data Sheet, Rev. 3

136 Freescale Semiconductor

Part 9 Joint Test Action Group (JTAG) 9.1 56F8037 Information Please contact your Freescale sales representative or authorized distributor fo r device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual. Part 10 Specifications

10.1 General Characteristics

The 56F8037 is fabricated in high-de nsity CMOS with 5V-tolerant TTL- compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-c ompatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to 125ºC ambient temperature over the following supply ranges: VSS =V SSA =0 V ,VDD =V DDA = 3.0–3.6V, CL < 50pF, fOP = 32MHz CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either V DD or VSS).

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 137 Preliminary Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC Analog Outputs Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.0 V Analog Input Voltage Range VINA Pin Group 3 - 0.3 4.0 V Input clamp current, per pin (VIN < 0)1 1. Continuous clamp current per pin is -2.0 mA VIC — -20.0 mA Output clamp current, per pin (VO < 0)1 VOC — -20.0 mA Output Voltage Range (Normal Push-Pull mode) VOUT Pin Group 1 - 0.3 4.0 V Output Voltage Range (Open Drain mode) VOUTOD Pin Group 2 - 0.3 6.0 V Output Voltage Range (DAC) VOUTDAC Pin Group 5 - 0.3 4.0 V Ambient Temperature Industrial TA - 40 105 °C Storage Temperature Range (Extended Industrial) TSTG - 55 150 °C

56F8037 Data Sheet, Rev. 3

138 Freescale Semiconductor

10.1.1 ElectroStatic Discharge (ESD) Model

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction to ambient thermal resistance, Theta-JA (RθJA), was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case thermal resistance, Theta-JC (RθJC), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is de- scribed by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Junction to board thermal resistance, Theta-JB (RθJB), is a metric of the thermal resistance from the junction to the printed circuit board determined per JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal Characterization Parameter, Psi-JT (YJT), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. YJT is a useful value to use to estimate junction temperature in steady state customer environments. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. See Section 12.1 for more details on thermal design considerations. Table 10-2 56F8037 ESD Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 750 — — V Table 10-3 LQFP Package Thermal Characteristics6 Characteristic Comments Symbol Value (LQFP) Unit Notes Junction to ambient Natural convection Single layer board (1s) RθJA 41 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA 34 °C/W 1, 2 Junction to ambient (@200 ft/min) Single layer board (1s) RθJMA 34 °C/W 2 Junction to ambient (@200 ft/min) Four layer board (2s2p) RθJMA 29 °C/W 1, 2 Junction to board R θJB 24 °C/W 4 Junction to case R θJC 8° C / W 3 Junction to package top Natural Convection ΨJT 2° C / W 5

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 139 Preliminary Note: Pin groups are detailed following Table 10-1 Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Symbol Notes Min Typ Max Unit Supply voltage VDD, VDDA 33 . 3 3 . 6 V ADC Reference Voltage High VREFHx 3.0 V DDA V Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 0 0.1 V Device Clock Frequency Using relaxation oscillator Using external clock source FSYSCLK MHz Input Voltage High (digital inputs) V IH Pin Groups 1, 2 2.0 5.5 V Input Voltage Low (digital inputs) VIL Pin Groups 1, 2 -0.3 0.8 V Oscillator Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source VIHOSC Pin Group 4 VDDA - 0.8 2.0 VDDA + 0.3 VDDA + 0.3 V Oscillator Input Voltage Low VILOSC Pin Group 4 -0.3 0.8 V DAC Output Load Resistance RLD 3K — ohms DAC Output Load Capacitance CLD — 400 pF Output Source Current High at VOH min.)1 When programmed for low drive strength When programmed for high drive strength 1. Total chip source or sink current cannot exceed 75mA IOH Pin Group 1 Pin Group 1 mA Output Source Current Low (at V OL max.)1 When programmed for low drive strength When programmed for high drive strength IOL Pin Groups 1, 2 Pin Groups 1, 2 mA Ambient Operating Temperature (Extended Industrial) TA -40 105 °C Flash Endurance (Program Erase Cycles) NF TA = -40°C to 125°C 10,000 — cycles Flash Data Retention TR TJ <= 85°C avg 15 — years Flash Data Retention with <100 Program/Erase Cycles tFLRET TJ <= 85°C avg 20 — — years

56F8037 Data Sheet, Rev. 3

140 Freescale Semiconductor

10.2 DC Electrical Characteristics

Note: Pin groups are detailed following Table 10-1 Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V I OH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V I OL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 μAV IN = 2.4V to 5.5V Comparator Input Current High IIHC Pin Group 3 — 0 +/- 2 μAV IN = VDDA Oscillator Input Current High IIHOSC Pin Group 3 — 0 +/- 2 μAV IN = VDDA Digital Input Current Low1 pull-up enabled pull-up disabled 1. See Figure 10-1 IIL Pin Groups 1, 2 -15 -30 -60 +/- 2.5 μAV IN = 0V Comparator Input Current Low IILC Pin Group 3 — 0 +/- 2 μAV IN = 0V Oscillator Input Current Low IILOSC Pin Group 3 — 0 +/- 2 μAV IN = 0V DAC Output Voltage Range VDAC Pin Group 5 Typically VSSA + 40mV — Typically VDDA - 40mV Output Current 1 High Impedance State IOZ Pin Groups 1, 2 — 0 +/- 2.5 μA— Schmitt Trigger Input Hysteresis VHYS Pin Groups 1, 2 — 0.35 — V — Input Capacitance CIN —1 0— p F — Output Capacitance COUT —1 0— p F —

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 141 Preliminary Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled) Table 10-6 Current Consumption per Power Supply Pin Mode Conditions Typical @ 3.3V, 25°C Maximum@ 3.6V, 25°C IDD

1 IDDA IDD

1 IDDA

Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled. TMR and PWM using 1X Clock ADC/DAC powered on and clocked Comparator powered on 48mA 18.8mA — — WAIT 32MHz Device Clock Relaxation Oscillator on PLL powered on Processor Core in WAIT state All Peripheral modules enabled. TMR and PWM using 1X Clock ADC/DAC/Comparator powered off 29mA 0 μA— — STOP 4MHz Device Clock Relaxation Oscillator on PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off 5.4mA 0μA— — 2.0 0.0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 µA Volt

56F8037 Data Sheet, Rev. 3

142 Freescale Semiconductor

10.2.1 Voltage Regulator Specifications

The 56F8037 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has no external pins and therefore has no external characteristics which must be guaranteed (other than proper operation of the device). The se cond regulator supplies approximately 2.5V to the 56F8037’s core logic. This regulator requires an external 4.4 μF, or greater, capacitor for prope r operation. Ceramic and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8. STANDBY > STOP 100kHz Device Clock Relaxation Oscillator in Standby mode PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off Voltage regulator in Standby mode 290μA0 μA 390 μA1 μA POWERDOWN Device Clock is off Relaxation Oscillator powered off PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC /DAC/Comparator powered off Voltage Regulator in Standby mode 190μA0 μA 250 μA1 μA 1. No Output Switching All ports configured as inputs All inputs Low No DC Loads Table 10-7 Power-On Reset Low-Voltage Parameters Characteristic Symbol Min Typ Max Unit Low-Voltage Interrupt for 3.3V supply1 1. When V DD drops below VEI3.3, an interrupt is generated. VEI3.3 2.58 2.7 — V Low-Voltage Interrupt for 2.5V supply2 2. When V DD drops below VEI32.5, an interrupt is generated. VE12.5 —2 . 1 5— V Low-Voltage Interrupt Recovery Hysteresis V EIH —5 0— m V Power-On Reset3 3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V 1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than V DD during ramp-up until 2.5V is reached, at which time it self-regulates. POR — 1.8 1.9 V Table 10-6 Current Consumption per Power Supply Pin (Continued) Mode Conditions Typical @ 3.3V, 25°C Maximum@ 3.6V, 25°C IDD

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 143 Preliminary

10.3 AC Electrical Characteristics

Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured fr om the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-2. Figure 10-2 Input Signal Measurement References Figure 10-3 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V OL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH Figure 10-3 Signal States

10.4 Flash Memory Characteristics

Table 10-8. Regulator Parameters Characteristic Symbol Min Typical Max Unit Short Circuit Current I SS — 450 650 mA Short Circuit Tolerance (VCAP shorted to ground) TRSC — — 30 minutes VIH VILFall Time Input Signal Note: The midpoint is VIL + (VIH – VIL)/2. Midpoint1 Low High 90% 50% 10% Rise Time Data Invalid State Data1 Data2 Valid Data Tri-stated Data3 Valid Data2 Data3 Data1 Valid Data Active Data Active

56F8037 Data Sheet, Rev. 3

144 Freescale Semiconductor

10.5 External Clock Operation Timing

Figure 10-4 External Clock Timing Table 10-9 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral Reference Manual for details. Tprog 20 — 40 μs Erase time 2 2. Specifies page erase time. There are 512 by tes per page in the Program Flash memory. Terase 20 — — ms Mass erase time Tme 100 — — ms Table 10-10 External Clock Operation Timing Requirements1 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 2. See Figure 10-4 for details on using the recommended connection of an external clock driver. fosc 488 M H z Clock Pulse Width3 3. The chip may not function if the high or low pulse width is smaller than 6.25ns. tPW 6.25 — — ns External Clock Input Rise Time4 4. External clock input rise time is measured from 10% to 90%. trise —— 3 n s External Clock Input Fall Time5 5. External clock input fall time is measured from 90% to 10%. tfall —— 3 n s External Clock VIH VIL Note: The midpoint is VIL + (VIH – VIL)/2. 90% 50% 10% 90% 50% 10% tPW tPW tfall trise

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 145 Preliminary

10.6 Phase Locked Loop Timing

10.7 Relaxation Oscillator Timing

Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input. fosc 48 — M H z Internal reference relaxation oscillator frequency for the PLL frosc —8— M H z PLL output frequency2 (24 x reference frequency) 2. The core system clock will operate at 1/6 of the PLL output frequency. fop 96 192 — MHz PLL lock time3 3. This is the time required after the PLL is enabled to ensure reliable operation. tplls —4 0 1 0 0 µ s Accumulated jitter using an 8MHz external crystal as the PLL source4 4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency and using an 8MHz oscillator frequency. JA — — 0.37 % Cycle-to-cycle jitter tjitterpll —3 5 0— p s Table 10-12 Relaxation Oscillator Timing Characteristic Symbol Minimum Typical Maximum Unit Relaxation Oscillator output frequency1 Normal Mode Standby Mode 1. Output frequency after application of 8MHz trim value, at 125°C. fop — 8.05 200 MHz kHz Relaxation Oscillator stabilization time2 2. This is the time required from Standby to Normal mode transition. troscs —1 3 m s Cycle-to-cycle jitter. This is measured on the CLKO signal (programmed prescaler_clock) over 264 clocks3 3. JA is required to meet QSCI requirements. tjitterrosc —4 0 0— p s Minimum tuning step size — .08 — % Maximum tuning step size — 40 — % Variation over temperature -40°C to 150ºC4 4. See Figure 10-5 Variation over temperature 0°C to 105ºC4 — 0 to +1 +2.0 to -2.0 %

56F8037 Data Sheet, Rev. 3

146 Freescale Semiconductor

Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim at 125°C 8.16 8.08 7.92 7.84 175-25-50 0 50 75 100 125 150 25 Degrees C (Junction) MHz

Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 147 Preliminary

10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Note: All address and data buses described here are internal. Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 1. In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Typical Min Typical Max Unit See Figure Minimum RESET Assertion Duration tRA 4T — ns — Minimum GPIO pin Assertion for Interrupt tIW 2T — ns 10-6 RESET deassertion to First Address Fetch3 3. During Power-On Reset, it is possible to use the 56F8037 internal reset stretching circuitry to extend this period to 2^21T. tRDA 96TOSC + 64T 97T OSC + 65T ns — Delay from Interrupt Assertion to Fetch of first instruction (exiting Stop) tIF —6 T n s — GPIO pin (Input) TIW

56F8037 Data Sheet, Rev. 3

148 Freescale Semiconductor

10.9 Serial Peripheral Interface (SPI) Timing

1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave tC 125 62.5 ns ns 10-7, 10-8, 10-9, 10-10 Enable lead time Master Slave t ELD ns ns 10-10 Enable lag time Master Slave tELG 125 ns ns 10-10 Clock (SCK) high time Master Slave tCH ns ns 10-7, 10-8, 10-9, 10-10 Clock (SCK) low time Master Slave t CL ns ns 10-10 Data set-up time required for inputs Master Slave tDS ns ns 10-7, 10-8, 10-9, 10-10 Data hold time required for inputs Master Slave tDH ns ns 10-7, 10-8, 10-9, 10-10 Access time (time to data active from high-impedance state) Slave t A 4.8 15 ns 10-10 Disable time (hold time to high-impedance state) Slave tD 3.7 15.2 ns 10-10 Data Valid for outputs Master Slave (after enable edge) tDV 4.5 20.4 ns ns 10-7, 10-8, 10-9, 10-10 Data invalid Master Slave t DI ns ns 10-7, 10-8, 10-9, 10-10 Rise time Master Slave tR 11.5 10.0 ns ns 10-7, 10-8, 10-9, 10-10 Fall time Master Slave tF 9.7 9.0 ns ns 10-7, 10-8, 10-9, 10-10

56F8037 Data Sheet, Rev. 3

150 Freescale Semiconductor

Figure 10-9 SPI Slave Timing (CPHA = 0) Figure 10-10 SPI Slave Timing (CPHA = 1) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 tC tCL tCL tF tCH tDI MSB in Bits 14–1 LSB in SS (Input) tCH tDH tR tELG tELD tF Slave LSB out tD tA tDS tDV tDI tR SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 tC tCL tCL tCH tDI MSB in Bits 14–1 LSB in SS (Input) tCH tDH tF tR Slave LSB out tDtA tELD tDV tF tR tELG tDV tDS

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 151 Preliminary

10.10 Quad Timer Timing

Table 10-15 Timer Timing1, 2 1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Timer input period P IN 2T + 6 — ns 10-11 Timer input high / low period P INHL 1T + 3 — ns 10-11 Timer output period P OUT 125 — ns 10-11 Timer output high / low period P OUTHL 50 — ns 10-11 POUT POUTHL POUTHL PIN PINHL PINHL Timer Inputs Timer Outputs

56F8037 Data Sheet, Rev. 3

152 Freescale Semiconductor

10.11 Queued Serial Communication Interface (QSCI) Timing

Figure 10-12 RXD Pulse Width Figure 10-13 TXD Pulse Width Table 10-16 QSCI Timing1 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Baud Rate2 2. f MAX is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8037 device. BR — (fMAX/16) Mbps — RXD3 Pulse Width 3. The RXD pin in QSCI0 is named RXD0 and the RXD pin in QSCI1 is named RXD1. RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width 4. The TXD pin in QSCI0 is named TXD0 and the TXD pin in QSCI1 is named TXD1. TXDPW 0.965/BR 1.04/BR ns 10-13 LIN Slave Mode Deviation of slave node clock from nominal clock rate before synchronization F TOL_UNSYNCH -14 14 % — Deviation of slave node clock relative to the master node clock after synchronization FTOL_SYNCH -2 2 % — Minimum break character length T BREAK 13 — Master node bit periods 11 — Slave node bit periods RXDPW RXD QSCI Receive data pin (Input) TXDPW TXD QSCI Receive data pin (Input)

Freescale’s Scalable Controller Area Network (MSCAN) Timing 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 153 Preliminary

10.12 Freescale’s Scalable Controller Area Network (MSCAN)

Figure 10-14 Bus Wake-up Detection

10.13 Inter-Integrated Circuit Interface (I2C) Timing

1. Parameters listed are guaranteed by design Characteristic Symbol Min Max Unit Baud rate BR CAN — 1 Mbps Bus wake-up detection T WAKEUP TIPBUS —µ s Table 10-18 I2C Timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency f SCL 01 0 004 0 0 k H z Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4.0 — 0.6 — μs LOW period of the SCL clock tLOW 4.7 — 1.3 — μs HIGH period of the SCL clock tHIGH 4.0 — 0.6 — μs Set-up time for a repeated START condition tSU; STA 4.7 — 0.6 — μs Data hold time for I2C bus devices tHD; DAT 01 3.452 01 0.92 μs Data set-up time t SU; DAT 2503 — 1003, 4 —n s TWAKEUP MSCAN_RX CAN receive data pin (Input)

56F8037 Data Sheet, Rev. 3

154 Freescale Semiconductor

Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I2C Bus Rise time of both SDA and SCL signals tr — 1000 20 +0.1Cb 5 300 ns Fall time of both SDA and SCL signals tf —3 0 0 20 +0.1Cb 5 300 ns Set-up time for STOP condition tSU; STO 4.0 — 0.6 — μs Bus free time between STOP and START condition t BUF 4.7 — 1.3 — μs Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum t HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 4. A Fast mode I 2C bus device can be used in a Standard mode I 2C bus system, but the requirement t SU; DAT >= 250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t rmax + tSU; DAT = 1000 + 250 = 1250ns (according to the Standard mode I 2C bus specification) before the SCL line is released. 5. C b = total capacitance of the one bus line in pF Table 10-18 I2C Timing (Continued) Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SDA SCL tHD; STA tHD; DAT tLOW tSU; DAT tHIGH tSU; STA SR P SS tHD; STA tSP tSU; STO tBUFtf tr tf tr

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 155 Preliminary

10.14 JTAG Timing

Figure 10-16 Test Clock Input Timing Diagram Figure 10-17 Test Access Port Timing Diagram Table 10-19 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 1. TCK frequency of operation must be less than 1/8 the processor rate. fOP DC SYS_CLK/8 MHz 10-16 TCK clock pulse width tPW 50 — ns 10-16 TMS, TDI data set-up time tDS 5— n s 10-17 TMS, TDI data hold time tDH 5— n s 10-17 TCK low to TDO data valid tDV —3 0n s 10-17 TCK low to TDO tri-state tTS —3 0n s 10-17 TCK (Input) VM VIL VM = VIL + (VIH – VIL)/2 tPW 1/fOP tPW VM VIH Input Data Valid Output Data Valid tDS tDH tDV tTS TCK (Input) TDI (Input) TDO (Output) TDO (Output) TMS

56F8037 Data Sheet, Rev. 3

156 Freescale Semiconductor

10.15 Analog-to-Digital Converter (ADC) Parameters

Table 10-20 ADC Parameters1 1. All measurements were made at V DD = 3.3V, VREFH = 3.3V, and VREFL = ground Parameter Symbol Min Typ Max Unit DC Specifications Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.33 MHz Conversion range RAD VREFL —V REFH V ADC power-up time2 2. Includes power-up of ADC and V REF tADPU —6 1 3 tAIC cycles3 3. ADC clock cycles Recovery from auto standby tREC —0 1 tAIC cycles3 Conversion time tADC —6 — tAIC cycles3 Sample time tADS —1 — tAIC cycles3 Accuracy Integral non-linearity4 (Full input signal range) 4. INL measured from V IN = VREFL to VIN = VREFH INL — +/- 3 +/- 5 LSB5 5. LSB = Least Significant Bit = 0.806mV Differential non-linearity DNL — +/- .6 +/- 1 LSB5 Monotonicity GUARANTEED Offset Voltage Internal Ref VOFFSET — +/- 4 +/- 9 mV Offset Voltage External Ref VOFFSET — +/- 6 +/- 12 mV Gain Error (transfer gain) EGAIN — .998 to 1.002 1.01 to .99 — ADC Inputs6 (Pin Group 3) 6. Pin groups are detailed following Table 10-1. Input voltage (external reference) VADIN VREFL —V REFH V Input voltage (internal reference) VADIN VSSA —V DDA V Input leakage IIA —0 + / - 2 μA VREFH current IVREFH —0 — μA Input injection current7, per pin 7. The current that can be injected or sourced from an unselec ted ADC signal input without impacting the performance of the ADC. IADI —— 3 m A Input capacitance CADI — See Figure 10-18 —p F Input impedance XIN — See Figure 10-18 —O h m s AC Specifications Signal-to-noise ratio SNR 60 65 dB Total Harmonic Distortion THD 60 64 dB Spurious Free Dynamic Range SFDR 61 66 dB Signal-to-noise plus distortion SINAD 58 62 dB Effective Number Of Bits ENOB — 10.0 Bits

Equivalent Circuit for ADC Inputs 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 157 Preliminary

10.16 Equivalent Circuit for ADC Inputs

Figure 10-18 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S 2 are closed and S3 is ope n, one input of the sample and hold circuit moves to (VREFHx - VREFLx) / 2, while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential vol tage centered about (V REFHx - VREFLx) / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF, and the ADC clock frequency. 1. Parasitic capacitance due to package, pin- to-pin and pin-to-package base coupling; 1.8pF 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF 3. Equivalent resistance for the channel select mux; 100 ohms 4. Sampling capacitor at the sample and hold circuit. Capaci tor C1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pF Figure 10-18 Equivalent Circuit for A/D Loading

10.17 Comparator (CMP) Parameters

Table 10-21 CMP Parameters Parameter Conditions/Comments Symbol Min Typ Max Unit Input Offset Voltage1 1. No guaranteed specification within 0.1V of V DDA or VSSA Within range of VDDA - .1V to VSSA + .1V VOFFSET — +/- 10 +/- 20 mV Input Propagation Delay t PD —3 54 5n s Power-up time t CPU —T B D T B D 1 2 3Analog Input 4 S/H C1 = C2 = 1pF(VREFHx - VREFLx ) / 2 125Ω ESD Resistor 8pF noise damping capacitor

56F8037 Data Sheet, Rev. 3

158 Freescale Semiconductor

10.18 Digital-to-Analog Converter (DAC) Parameters

Table 10-22 DAC Parameters Parameter Conditions/Comm ents Symbol Min Typ Max Unit DC Specifications Resolution 12 12 bits Conversion time TBD — 2 µS Conversion rate TBD — 500.000 conv/sec Power-up time Time from release of PWRDWN signal until DACOUT signal is valid t DAPU — — 11 µS Accuracy Integral non-linearity1 1. No guaranteed specification within 5% of V DDA or VSSA Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range INL — +/- 3 +/- 8.0 LSB2 2. LSB = 0.806mV Differential non-linearity1 Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range DNL — +/- .8 < - 1 LSB2 Monotonicity > 6 si gma monotonicity, < 3.4 ppm non-monotonicity guaranteed — Offset error1 Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range VOFFSET — +/- 25 +/- 40 mV Gain error1 Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range E DAC Output Output voltage range Within 40mV of either V REFLX or VREFHX VOUT VREFLX +.04V —V REFHX - .04V V Short circuit current DACOUT shorted to ground with input digital word = $FFF DACOUT shorted to V DDA with input digital word = $000 ISC ISC 100 mA AC Specifications Signal-to-noise ratio SNR — TBD — dB Spurious free dynamic range SFDR — TBD — dB Effective number of bits ENOB 9 — — bits

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 159 Preliminary

10.19 Power Consumption

See Section 10.1 for a list of IDD requirements for the 56F8037. This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage referen ces. These sources operate independent ly of processor state or operating frequency. B, the internal [state-dependent component], re flects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V 2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept. Power due to capacitive loading on output pins is (first order) a f unction of the capacitive load and frequency at which the outputs change. Table 10-23 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load. In these cases: TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz) where:

• Summation is performed over all ou tput pins with capacitive loads
• TotalPower is expressed in mW
• Cload is expressed in pF Total power = A: interna l [static component] +B: internal [state-d ependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component] Table 10-23 I/O Loading Coefficients at 10MHz Intercept Slope 8mA drive 1.3 0.11mW / pF 4mA drive 1.15mW 0.11mW / pF

56F8037 Data Sheet, Rev. 3

160 Freescale Semiconductor

Because of the low duty cycle on most device pins , power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive load s on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 161 Preliminary Part 11 Packaging 11.1 56F8037 Package and Pin-Out Information This section contains package and pin-out inform ation for the 56F8037. This de vice comes in a 64-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline, Figure 11-2 shows the mechanical parameters and Table 11-1 lists the pin-out. Figure 11-1 Top View, 56F8037 64-Pin LQFP Package 49GPIOB6 / RXD0 / SDA / CLKIN GPIOB7 / TXD0 / SCL GPIOB1 / SS0 / SDA GPIOB5 / TA1 / FAULT3 / CLKIN GPIOA9 / FAULT2 / TA3 / CMPBI1 GPIOA11 / TB3 / CMPBI2 VDD VSS GPIOC4 / ANB0 / CMPBI3 GPIOC5 / ANB1 GPIOC13 / ANB5 GPIOC6 / ANB2 / VREFHB GPIOC7 / ANB3 / VREFLB GPIOD7 / DAC1 VDDA VSSA GPIOC3 / ANA3 / VREFLx GPIOD6 / DAC0 GPIOC2 / ANA2 / VREFHA GPIOC9 / ANA5 GPIOC1 / ANA1 GPIOC10 / ANA6 GPIOC0 / ANA0 & CMPAI3 GPIOC11 / ANA7 GPIOC8 / ANA4 / TXD1 VSS VCAP TCK / GPIOD2 GPIOB10 / TB0 / CMPAO RESET / GPIOA7 GPIOB3 / MOSI0 / TA3 / PSRC1 GPIOA3 / PWM3 GPIOB9 / SDA / CANRX GPIOA2 / PWM2 GPIOA14 / MOSI1/ TB3 / TA3 GPIOA13 / MISO1/ TB2 / TA2 GPIOA4 / PWM4 / TA2 / FAULT1 GPIOB0 / SCLK0 / SCL VDD VSS GPIOA5 / PWM5 / TA3 / FAULT2 GPIOB4 / SS1 / TB0 / TA0 / PSRC2 / CLKO GPIOA12 / SCLK1 / TB1 / TA1 GPIOA8 / FAULT1 / TA2 / CMPAI1 GPIOA10 / TB2 / CMPAI2 GPIOA6 / FAULT0 / TA0 GPIOB2 / MISO0 / TA2 / PSRC0 Pin 1 Orientation Mark TDO / GPIOD1 GPIOC14 / ANB6 TMS / GPIOD3 GPIOC15 / ANB7 GPIOB11 / TB1 / CMPBO TDI / GPIOD0 GPIOB13 / CANRX GPIOB12 / CANTX GPIOA0 / PWM0 GPIOA1 / PWM1 GPIOB8 / SCL / CANTX GPIOD4 / EXTAL GPIOD5 / XTAL / CLKIN VSS VDD VCAP GPIOC12 / ANB4 / RXD1

56F8037 Data Sheet, Rev. 3

162 Freescale Semiconductor

Table 11-1 56F8037 64-Pin LQFP Package Identification by Pin Number1 Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name

1 GPIOB6

17 VSSA 33 GPIOB2

49 VCAP

2 GPIOB1

18 GPIOD6

34 GPIOA6

50 VDD

3 GPIOB7

19 GPIOC3

35 GPIOA10

51 VSS

4 GPIOB5

20 GPIOC2

36 GPIOA8

52 GPIOD5

5 GPIOA9

21 GPIOC9

37 GPIOA12

53 GPIOD4

6 GPIOA11

22 GPIOC1

38 GPIOB4

54 GPIOB8

7 VDD 23 GPIOC10

39 GPIOA5

55 GPIOA1

8 VSS 24 GPIOC0

ANA0 & CMPAI3

40 VSS 56 GPIOA0

9 GPIOC12

25 GPIOC11

41 VDD 57 GPIOB12

10 GPIOC4

ANB0 & CMPBI3

26 GPIOC8

42 GPIOB0

58 GPIOB13

11 GPIOC5

27 VSS 43 GPIOA4

59 TDI

12 GPIOC13

28 VCAP 44 GPIOA13

60 GPIOB11

13 GPIOC6

29 TCK

45 GPIOA14

61 GPIOC15

14 GPIOC7

30 GPIOB10

46 GPIOB9

62 GPIOC14

15 GPIOD7

31 RESET

47 GPIOA2

63 TMS

16 VDDA 32 GPIOB3

48 GPIOA3

64 TDO

56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 163 Preliminary Figure 11-2 56F8037 64-Pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. 1. Alternate signals are in italic AB AB e/2 e60X X=A, B OR D CL VIEW Y S0.05 q q q ( 2) 0.25 GAGE PLANE SEATING PLANE (S) R12X R (L1) (L2) LA1 VIEW AA SECTION AB-AB b c1c PLATING BASE METAL ROTATED 90 CLOCKWISE° A-BM0.08 D C

0.2 HA - B D

B E/2 EE1 D/2 D D1/2 VIEW Y A 4X VIEW AA 0.08 C q( 3)4X 4X 4X 16 TIPS

0.2 CA - B D

A D C H X DIM MIN MAX MILLIMETERS A --- 1.60 A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 12.00 BSC D1 10.00 BSC e 0.50 BSC E 12.00 BSC E1 10.00 BSC L 0.45 0.75 L1 1.00 REF L2 0.50 REF R1 0.10 0.20 S 0.20 REF q 0 7 q 0 --- q 12 REF q 12 REF NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE DATUM H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE DATUM C. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE DATUM C. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.35. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07.

56F8037 Data Sheet, Rev. 3

164 Freescale Semiconductor

Part 12 Design Considerations

12.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: The junction-to-ambient thermal resi stance is an industry-standard va lue that provides a quick and easy estimation of thermal perf ormance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where: RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface mate rial, the mounting arrange ment on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter ( ΨJT) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT x PD) where: TA = Ambient temperature for the package ( oC) RθJΑ = Junction-to-ambient thermal resistance ( oC/W) PD = Power dissipation in the package (W) RθJA = Package junction-to-ambient thermal resistance (°C/W) RθJC = Package junction-to-case thermal resistance (°C/W) RθCA = Package case-to-ambient thermal resistance (°C/W) TT = Thermocouple temperature on top of package ( oC) ΨJT = Thermal characterization parameter ( oC/W) PD = Power dissipation in package (W)

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 165 Preliminary The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top ce nter of the package case. The th ermocouple should be positioned so that the thermocouple junction re sts on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. From this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance.

12.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation of the 56F8037:

• Provide a low-impedance path from the board power supply to each VDD pin on the 56F8037 and from the board ground to each VSS (GND) pin
• The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated prin ted circuit traces that connect to the chip VDD and VSS (GND) pins are as short as possible
• Bypass the V DD and VSS with approximately 100µF, plus the number of 0.1µF ceramic capacitors
• PCB trace lengths should be mini mal for high-frequency signals
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

56F8037 Data Sheet, Rev. 3

166 Freescale Semiconductor

• Take special care to minimize noise levels on the V REF, VDDA, and VSSA pins
• Using separate power planes for V DD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces.
• It is highly desirable to physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces.
• Because the Flash memory is programmed through the JTAG/EOnCE port, QSPI, QSCI, or I 2C, the designer should provide an interface to this port if in-circuit Flash programming is desired
• If desired, connect an external RC circuit to the RESET pin. The Resistor value should be in the range of 4.7k—10k; the Capacitor value should be in the range of 0.22µf - 4.7µf.
• Add a 3.3k external pull-up on the TMS pin of the JT AG port to keep EOnce in a restate during normal operation if JTAG converter is not present
• During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pull-up enable. The typical value of internal pull-up is around 110K. These internal pull-ups can be disabled by software.
• To eliminate PCB trace impedance effect, each ADC input should have a 33pf-10 ohm RC filter
• Device GPIOs have only a down (substrate) diode on the GPIO circuit. Devices do not have a positive clamp diode because GPIOs use a floating gate structure to tolerate 5V input. The absolute maximum clamp current is -20mA at Vin less than 0V . The continuous clamp current is -2mA at Vin less than 0V . If positive voltage spikes are a concern, a positive clamp is recommended. Part 13 Ordering Information Table 13-1 lists the pertinent information needed to pl ace an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. * This package is RoHS compliant. Table 13-1 56F8037 Ordering Information Device Supply Voltage Package Type Pin Count Frequency (MHz) Ambient Temperature Range Order Number MC56F8037 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 64 32 -40° to + 105° C MC56F8037VLH*

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 167 Preliminary Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table. Table 14-1 Legacy and Revised Acronyms Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End Analog-to-Digital Converter (ADC) Module Control 1 Register CTRL1 ADCR1 ADC_CTRL1 ADC_ADCR1 ADC_ADCR1 0xF080 Control 2 Register CTRL2 ADCR2 ADC_CTRL2 ADC_ADCR2 ADC_ADCR2 0xF081 Zero Crossing Control Register ZXCTRL ADZCC ADC_ZXCTRL ADC_ADZCC ADC_ADZCC 0xF082 Channel List 1 Register CLIST1 ADLST1 ADC_CLIST1 ADC_ADLST1 ADC_ADLST1 0xF083 Channel List 2 Register CLIST2 ADLST2 ADC_CLIST2 ADC_ADLST2 ADC_ADLST2 0xF084 Channel List 3 Register CLIST3 ADC_CLIST3 ADC_ADCLST3 ADC_ADCLST3 0xF085 Channel List 4 Register CLIST4 ADC_CLIST4 ADC_ADCLST4 ADC_ADCLST4 0xF086 Sample Disable Register SDIS ADSDIS ADC_SDIS ADC_ADSDIS ADC_ADSDIS 0xF087 Status Register STAT ADSTAT ADC_STAT ADC_ADSTAT ADC_ADSTAT 0xF088 Conversion Ready Register RDY ADC_CNRDY ADC_ADCNRDY ADC_ADCNRDY 0xF089 Limit Status Register LIMSTAT ADLSTAT ADC_LIMSTAT ADC_ADLST A T ADC_ADLST A T 0xF08A Zero Crossing Status Register ZXSTAT ADZCSTAT ADC_ZXSTAT ADC_ADZCSTAT ADC_ADZCSTAT 0xF08B Result 0-7 Registers RSLT0-7 ADRSLT0-7 ADC_RSLT0-7 ADC_ADRSLT0-7 ADC_ADRSLT0-7 0xF08C 0XF093 Result 8-15 Registers RSLT8-15 ADC_RSLT8-15 ADC_ADRSLT8-15 ADC_ADRSLT8-15 0xF094 0XF09B Low Limit 0-7 Registers LOLIM0-7 ADLLMT0-7 ADC_LOLIM0-7 ADC_ADLLMT0-7 ADC_ADLLMT0-7 0XF09C 0XF0A3 High Limit 0-7 Registers HILIM0-7 ADHLMT0-7 ADC_HILIM0-7 ADC_ADHLMT0-7 ADC_ADHLMT0-7 0XF0A4 0XF0AB Offset 0-7 Registers OFFST0-7 ADOFS0-7 ADC_OFFST0-7 ADC_ADOFS0-7 ADC_ADOFS0-7 0XF0AC 0XF0B3 Power Control Register PWR ADPOWER ADC_PWR ADC_ADPOWER ADC_ADPOWER 0XF0B4 Calibration Register CAL ADC_CAL ADC_ADCAL ADC_ADCAL 0XF0B5 Computer Operating Properly (COP) Module Control Register CTRL COPCTL COP_CTRL COPCTL COPCTL 0XF120 Timeout Register TOUT COPTO COP_TOUT COPTO COPTO 0XF121 Counter Register CNTR COPCTR COP_CNTR COPCTR COPCTR 0XF122

56F8037 Data Sheet, Rev. 3

168 Freescale Semiconductor

Inter-Integrated Circuit Interface (I2C) Module Control Register CTRL IBCR I2C_CTRL I2C_IBCR I2C_IBCR 0xF280 Target Address Register TAR I2C_TAR I2CTAR I2C_TAR 0xF282 Slave Address Register SAR I2C_SAR I2CSAR I2C_SAR 0xF242 Data Buffer & Command Register DATA I2C_DATA I2C_DATACMD I2C_DATACMD 0xF288 Standard Speed Clock SCL High Count Register SSHCNT I2C_SS_SCL_HCNT I2C_SS_SCLHCNT I2C_SS_SCLHCNT 0xF28A Standard Speed Clock SCL Low Count Register SSLCNT I2C_SS_SCL_LCNT I2C_SS_SCLLCNT I2C_SS_SCLLCNT 0xF28C Fast Speed Clock SCL High Count Register FSHCNT I2C_FS_SCL_HCNT I2C_FS_SCLHCNT I2C_FS_SCLHCNT 0xF28E Fast Speed Clock SCL Low Count Register FSLCNT I2C_FS_SCL_LCNT I2C_FS_SCLLCNT I2C_FS_SCLLCNT 0xF290 Interrupt Status Register ISTAT I2C_INTR_STAT I2C_INTRSTAT I2C_INTRSTAT 0xF296 Interrupt Mask Register IENBL I2C_INTR_MASK I2C_INTRMASK I2C_INTRMASK 0xF298 Raw Interrupt Status Register RISTAT I2C_RAW_INTR_ STAT I2C_RAW_INTRSTAT I2C_RAW_INTRSTAT 0xF29A Receive FIFO Threshold Level Register RXFT I2C_RXTL I2C_RXTL 0xF29C Transmit FIFO Threshold Level Register TXFT I2C_TXTL I2C_TXTL 0xF29E Clear Combined & Individual Interrupts Register CLRINT I2C_CLRINTR I2C_CLRINTR 0xF2A0 Clear Receive Under Interrupt Register CLRRXUND I2C_CLR_RXUNDER I2C_CLR_RXUNDER 0xF2A2 Clear Receive Over Interrupt Register CLRRXOVR I2C_CLROVER I2C_CLROVER 0xF2A4 Clear Transmit Over Register CLRTXOVR I2C_CLR_TXOVER I2C_CLR_TXOVER 0xF2A6 Clear Read Required Interrupt Register CLRRDREQ I2C_CLR_RDREQ I2C_CLR_RDREQ 0xF2A8 Clear Transmit Abort Interrupt Register CLRTXABRT I2C_CLR_TXABRT I2C_CLR_TXABRT 0xF2AA Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 169 Preliminary Clear Receive Done Interrupt Register CLRRXDONE I2C_CLR_RXDONE I2C_CLR_RXDONE 0xF2AC Clear Activity Interrupt Register CLRACT I2C_CLRACTIVITY I2C_CLRACTIVITY 0xF2AE Clear Stop Detect Interrupt Register CLRSTPDET I2C_CLR_STOPDET I2C_CLR_STOPDET 0xF2B0 Clear Start Detect Interrupt Register CLRSTDET I2C_CLR_STAR_DET I2C_CLR_STAR_DET 0xF2B2 Clear General Call Interrupt Register CLRGC I2C_CLR_GENCALL I2C_CLR_GENCALL 0xF2B4 Enable Register ENBL I2C_ENABLE I2C_ENABLE 0xF2B6 Status Register STAT I2C_STAT I2C_STAT 0xF2B8 Transmit FIFO Level Register TXFLR I2C_TXFLR I2C_TXFLR 0xF2BA Receive FIFO Level Register RXFLR I2C_RXFLR I2C_RXFLR 0xF2BC Transmit Abort Source Register TXABRTSRC I2C_TX_ABRTSRC I2C_TX_ABRTSRC 0xF2C0 Component Parameter 1 Register COMPARM1 I2C_COMPARM1 I2C_COMPARM1 0xF2FA Component Parameter 2 Register COMPARM2 I2C_COMPARM2 I2C_COMPARM2 0xF2FB Component Version 1 Register COMVER1 I2C_COMVER1 I2C_COMVER1 0xF2FC Component Version 2 Register COMVER2 I2C_COMVER2 I2C_COMVER2 0xF2FD Component Type 1 Register COMTYP1 I2C_COMTYP1 I2C_COMTYP1 0xF2FE Component Type 2 Register COMTYP2 I2C_COMTYP2 I2C_COMTYP2 0xF2FF On-Clock Chip Synthesis (OCCS) Module Control Register CTRL PLLCR OCCS_CTRL PLLCR PLLCR 0xF130 Divide-By Register DIVBY PLLDB OCCS_DIVBY PLLDB PLLDB 0xF131 Status Register STAT PLLSR OCCS_STAT PLLSR PLLSR 0xF132 Oscillator Control Register OCTRL OSCTL OCCS_OCTRL OSCTL OSCTL 0xF135 Clock Check Register CLKCHK OCCS_CLCHK PLLCLCHK OCCS_CLCHK 0xF136 Protection Register PROT OCCS_PROT PLLPROT OCCS_PROT 0xF137 Clock Divider Register CLKDIV FMCLKD FM_CLKDIV FMCLKD FMCLKD 0xF400 Configuration Register CNFG FMCR FM_CNFG FMCR FMCR 0xF401 Security High Half Register SECHI FMSECH FM_SECHI FMSECH FMSECH 0xF403 Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

56F8037 Data Sheet, Rev. 3

170 Freescale Semiconductor

SECLO FMSECL FM_SECLO FMSECL FMSECL 0xF404 Protection Register PROT FMPROT FM_PROT FMPROT FMPROT 0xF410 User Status Register USTAT FMUSTAT FM_USTAT FMUSTAT FMUSTAT 0xF413 Command Register CMD FMCMD FM_CMD FMCMD FMCMD 0xF414 Data Buffer Register DATA FMDATA FM_DATA FMDATA FMDATA 0xF418 Info Optional Data 1 Register OPT1 FMOPT1 FM_OPT1 FMOPT1 FMOPT1 0xF41B Test Array Signature Register TSTSIG FMTST_SIG FM_TSTSIG FMTST_SIG FMTST_SIG 0xF41D General Purpose Input/Output (GPIO) Module x = A (n=0) B (n=1) C (n=2) D (n=3) Pull-Up Enable Register PUPEN PUR GPIO x_PUPEN GPIO x_PUR GPIO_ x_PUR 0xF1 n0 Data Register DATA DR GPIOx_DATA GPIOx_DR GPIO_x_DR 0xF1n1 Data Direction Register DDIR DDR GPIO x_DDIR GPIO x_DDR GPIO_ x_DDR 0xF1 n2 Peripheral Enable Register PEREN PER GPIOx_PEREN GPIOx_PER GPIO_x_PER 0xF1n3 Interrupt Assert Register IASSRT IAR GPIO x_IASSRT GPIO x_IAR GPIO_ x_IAR 0xF1 n4 Interrupt Enable Register IEN IENR GPIOx_IEN GPIOx_IENR GPIO_x_IENR 0xF1n5 Interrupt Polarity Register IPOL IPOLR GPIO x_IPOL GPIO x_IPOLR GPIO_ x_IPOLR 0xF1 n6 Interrupt Pending Register IPEND IPR GPIOx_IPEND GPIOx_IPR GPIO_x_IPR 0xF1n7 Interrupt Edge-Sensitive Register IEDGE IESR GPIO x_IEDGE GPIO x_IESR GPIO_ x_IESR 0xF1 n8 Push-Pull Mode Registers PPOUTM PPMODE GPIOx_PPOUTM GPIOx_PPMODE GPIO_x_PPMODE 0xF1n9 Raw Data Input Register RDATA RAWDATA GPIO x_RDATA GPIOx_RAWDATA GPIO_ x_RAWDATA 0xF1 nA Output Drive Strength Register DRIVE DRIVE GPIOx_DRIVE GPIOx_DRIVE GPIO_x_DRIVE 0xF1nB Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 171 Preliminary Pulse Width Modulator (PWM) Module Control Register CTRL PMCTL PWM_CTRL PWM_PMCTL PWM_PMCTL 0xF0C0 Fault Control Register FCTRL PMFCTL PWM_FCTRL PWM_PMFCTL PWM_PMFCTL 0xF0C1 Fault Status/Acknowledge Regis. FLTACK PMFSA PWM_FLTACK PWM_PMFSA PWM_PMFSA 0xF0C2 Output Control Register OUT PMOUT PWM_OUT PWM_PMOUT PWM_PMOUT 0xF0C3 Counter Register CNTR PMCNT PWM_CNTR PWM_PMCNT PWM_PMCNT 0xF0C4 Counter Modulo Register CMOD MCM PWM_CMOD PWM_MCM PWM_MCM 0xF0C5 Value 0-5 Registers VAL0-5 PMVAL0-5 PWM_VAL0-5 PWM_PMVAL0-5 PWM_PMVAL0-5 0xF0C6 0xF0CB Deadtime 0-1 Registers DTIM0-1 PMDEADTM0-1 PWM_DTIM0-1 PWM_PMDEADTM0-1PWM_PMDEADTM0-10xF0CC 0xF0CD Disable Mapping 1-2 Registers DMAP1-2 PMDISMAP1-2 PWM_DMAP1-2 PWM_PMDISMAP1-2 PWM_PMDISMAP1-2 0xF0CE 0xF0CF Configure Register CNFG PMCFG PWM_CNFG PWM_PMCFG PWM_PMCFG 0xF0D0 Channel Control Register CCTRL PMCCR PWM_CCTRL PWM_PMCCR PWM_PMCCR 0xF0D1 Port Register PORT PMPORT PWM_PORT PWM_PMPORT PWM_PMPORT 0xF0D2 Internal Correction Control Register ICCTRL PMICCR PWM_ICCTRL PWM_PMICCR PWM_PMICCR 0xF0D3 Source Control Register SCTRL PMSRC PWM_SCTRL PWM_PMSRC PWM_PMSRC 0xF0D4 Synchronization Window Register SYNC PWM_SYNC PWM_SYNC PWM_SYNC 0xF0D5 Fault Filter 0-3 Register FFILT0-3 PWM_FFILT0-3 PWM_FFILT0-3 PWM_FFILT0-3 0xF0D6 0xF0D9 Multi-Scalable Controller Area Network (MSCAN) Module Control 0 Register CTRL0 CAN_CTRL0 CANCTRL0 0XF800 Control 1 Register CTRL1 CAN_CTRL1 CANCTRL1 0XF801 Bus Timing 0 Register BTR0 CAN_BTR0 CANBTR0 0XF802 Bus Timing 1 Register BTR1 CAN_BTR1 CANBTR1 0XF803 Receive Flag Register RFLG CAN_RFLG CANRFLG 0XF804 Receiver Interrupt Enable Register RIER CAN_RIER CANRIER 0XF805 Transmitter Flag Register TFLG CAN_TFLG CANTFLG 0XF806 Transmitter Interrupt Enable Register. TIER CAN_TIER CANTIER 0XF807 Transmitter Msg Abort Request Register TARQ CAN_TARQ CANTARQ 0XF808 Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

56F8037 Data Sheet, Rev. 3

172 Freescale Semiconductor

TAAK CAN_TAAK CANTAAK 0XF809 Transmitter FIFO Selection Register TBSEL CAN_TBSEL CANTBSEL 0XF80A Identifier Acceptance Control Register IDAC CAN_IDAC CANIDAC 0XF80B Miscellaneous Register MISC CAN_MISC CANMISC 0XF80D Receive Error Register RXERR CAN_RXERR CANRXERR 0XF80E Transmit Error Register TXERR CAN_TXERR CANTXERR 0XF80F Identifier Acceptance 0-3 Registers IDAR0-3 CAN_IDAR0-3 CANIDAR0-3 0xF810 0xF813 Identifier Mask 0-3 Registers IDMR0-3 CAN_IDMR0-3 CANIDMR0-3 0xF814 0xF817 Identifier Acceptance 4-7 Register IDAR4-7 CAN_IDAR4-7 CANIDAR4-7 0xF818 0xF81B Identifier Mask 4-7 Registers IDMR4-7 CAN_IDMR4-7 CANIDMR4-7 0xF81C 0xF81F Foreground Receive FIFO Register RXFG CAN_RXFG CANRXFG 0xF82F 0xF820 Foreground Transmit FIFO Register TXFG CAN_TXFG CANTXFG 0xF830 0xF83F Power Supervisor (PS) Module Control Register CTRL LVICONTROL PS_CTRL LVICONTROL LVICTRL 0xF140 Status Register STAT LVISTATUS PS_STAT LVISTATUS LVISR 0xF141 Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 173 Preliminary Queued Serial Communications Interface (QSCI) Module n = 0, 1 Baud Rate Register RATE QSCI_RATE QSCI_SCIBR 0xF2 n0 Control 1 Register CTRL1 QSCI_CTRL1 QSCI_SCICR 0xF2n1 Control 2 Register CTRL2 QSCI_CTRL2 QSCI_SCICR2 0xF2 n2 Status Register STAT QSCI_STAT QSCI_SCISR 0xF2n3 Data Register DATA QSCI_DATA QSCI_SCIDR 0xF2 n4 Queued Serial Peripheral Interface (QSPI) Module Status and Control Register SCTRL QSPI_SCTRL QSPI_SPSCR 0xF2 n0 Data Size and Control Register DSCTRL QSPI_DSCTRL QSPI_SPDSR 0xF2n1 Data Receive Register DRCV QSPI_DRCV QSPI_SPDRR 0xF2 n2 Data Transmit Register DXMIT QSPI_DXMIT QSPI_SPDTR 0xF2n3 FIFO Control Register FIFO QSPI_FIFO QSPI_SPFIFO 0xF2 n4 Wait Register WAIT QSPI_WAIT QSPI_SPWAIT 0xF2n5 Quad-Timer (TMR) Module n = 0, 1, 2, 3 Compare 1 Register COMP1 TMRCMP1 TMR n_COMP1 TMR n_CMP1 TMR n_CMP1 0xF0 n0 Compare 2 Register COMP2 TMRCMP2 TMRn_COMP2 TMRn_CMP2 TMRn_CMP2 0xF0n1 Capture Register CAPT TMRCAP TMR n_CAPT TMR n_CAP TMR n_CAP 0xF0 n2 Load Register LOAD TMRLOAD TMRn_LOAD TMRn_LOAD TMRn_LOAD 0xF0n3 Hold Register HOLD TMRHOLD TMR n_HOLD TMR n_HOLD TMR n_HOLD 0xF0 n4 Counter Register CNTR TMRCNTR TMRn_CNTR TMRn_CNTR TMRn_CNTR 0xF0n5 Control Register CTRL TMRCTRL TMR n_CTRL TMR n_CTRL TMR n_CTRL 0xF0 n6 Status and Control Register SCTRL TMRSCR TMRn_SCTRL TMRn_SCR TMRn_SCR 0xF0n7 Comparator Load 1 Register CMPLD1 TMRCMPLD1 TMR n_CMPLD1 TMR n_CMPLD1 TMR n_CMPLD1 0xF0 n8 Comparator Load 2 Register CMPLD2 TMRCMPLD2 TMRn_CMPLD2 TMRn_CMPLD2 TMRn_CMPLD2 0xF0n9 Comparator Status/Control Register CSCTRL TMRCOMSCR TMR n_CSCTRL TMR n_COMSCR TMR n_COMSCR 0xF0 nA Input Filter Register FILT TMRn_FILT TMRn_FILT TMRn_FILT 0xF0nB Enable Register ENBL TMR n_ENBL TMR n_ENBL TMR n_ENBL 0xF0 nF Voltage Regulator (VREG) Module See SIM section Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

56F8037 Data Sheet, Rev. 3

174 Freescale Semiconductor

Programmable Interval Timer (PIT) Module n = 0, 1, 2 Control Register CTRL PIT n_CTRL PITCTRL0-2 PIT n_CTRL 0xF1 n0 Modulo Register MOD PITn_MOD PITMOD0-2 PITn_MOD 0xF1n1 Counter Register CNTR PIT n_CNTR PITCNTR0-2 PIT n_CNTR 0xF1 n2 n = 0, 1 Control Register CTRL DAC n_CTRL DACCTRL0-2 DAC n_CTRL 0xF1 n0 Data Register DATA DACn_DATA DACDATA0-2 DACn_DATA 0xF1n1 Step Register STEP DAC n_STEP DACSTEP0-2 DAC n_STEP 0xF1 n2 Minimum Value Register MINVAL DACn_MINVAL DACMINVAL0-2 DACn_MINVAL 0xF1n3 Maximum Value Register MAXVAL DAC n_MAXVAL DACMAXVAL0-2 DAC n_MAXVAL 0xF1 n4 Comparator (CMP) Module A x = E B x = F Control Register CTRL CMP_CTRL CMP x_CTRL CMP x_CTRL 0xF1 x0 Status Register STAT CMP_STAT CMPx_STAT CMPx_STAT 0xF1x1 Filter Register FILT CMP_FILT CMP x_FILT CMP x_FILT 0xF1 x2 Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 175 Preliminary Interrupt Controller (ITCN) Module Interrupt Priority 0-4 Registers N/A N/A ITCN_IPR0-4 ITCN_IPR0-4 INTC_IPR0-4 0XF060 0XF064 Vector Base Address Register N/A N/A ITCN_VBA ITCN_VBA INTC_VBA 0XF065 Fast Interrupt Match 0 Register N/A N/A ITCN_FIM0 ITCN_FIM0 INTC_FIM0 0XF066 Fast Interrupt Vector Address Low 0 N/A N/A ITCN_FIVAL0 ITCN_FIVAL0 INTC_FIVAL0 0XF067 Fast Interrupt Vector Address High 0 N/A N/A ITCN_FIVAH0 ITCN_FIVAH0 INTC_FIVAH0 0XF068 Fast Interrupt Match 1 Register N/A N/A ITCN_FIM1 ITCN_FIM1 INTC_FIM1 0xF069 Fast Interrupt Vector Address Low 1 N/A N/A ITCN_FIVAL1 ITCN_FIVAL1 INTC_FIVAL1 0xF06A Fast Interrupt Vector Address High 1 N/A N/A ITCN_FIVAH1 ITCN_FIVAH1 INTC_FIVAH1 0xF06B Interrupt Pending 0 Register N/A N/A ITCN_IRQP0 ITCN_IRQP0 INTC_IRQP0 0xF06C Interrupt Pending 1 Register N/A N/A ITCN_IRQP1 ITCN_IRQP1 INTC_IRQP1 0xF06D Interrupt Pending 2 Register N/A N/A ITCN_IRQP2 ITCN_IRQP2 INTC_IRQP2 0xF06E System Integration Module (SIM) Control Register N/A N/A SIM_CTRL SIM_CONTROL SIM_CONTROL 0xF100 Reset Status Register N/A N/A SIM_RSTAT SIM_RSTSTS SIM_RSTSTS 0xF101 Software Control 0-3 Registers N/A N/A SIM_SWC0-3 SIM_SCR0-3 SIM_SCR0-3 0xF102 0xF105 Most Significant Half JTAG ID N/A N/A SIM_MSHID SIM_MSH_ID SIM_MSH_ID 0xF106 Least Significant Half JTAG ID N/A N/A SIM_LSHID SIM_LSH_ID SIM_LSH_ID 0xF107 Power Control Register N/A N/A SIM_PWR SIM_POWER 0xF108 Clock Out Select Register N/A N/A SIM_CLKOUT SIM_CLKOSR SIM_CLKOSR 0xF10A Peripheral Clock Rate Register N/A N/A SIM_PCR SIM_PCR SIM_PCR 0xF10B Peripheral Clock Enable 0-1 Register N/A N/A SIM_PCE0-1 SIM_PCE0-1 SIM_PCE0-1 0xF10C 0xF10D Peripheral Stop Disable 0-1 Register N/A N/A SIM_SD0-1 SIM_SD0-1 SIM_SD0-1 0xF10E 0xF10F Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

56F8037 Data Sheet, Rev. 3

176 Freescale Semiconductor

N/A N/A SIM_ISALH SIM_ISALH SIM_ISALH 0xF110 I/O Short Address Location Low Register N/A N/A SIM_ISALL SIM_ISALL SIM_ISALL 0xF111 Protection Register N/A N/A SIM_PROT SIM_PROT SIM_PROT 0xF112 GPIOA Peripheral Select 0 Register N/A N/A SIM_GPISA0 SIM_GPISA0 SIM_GPISA0 0xF113 GPIOA Peripheral Select 0 Register N/A N/A SIM_GPSA1 SIM_GPSA1 SIM_GPSA1 0xF114 GPIOB Peripheral Select 0 Register N/A N/A SIM_GPSB0 SIM_GPSB0 SIM_GPSB0 0xF115 GPIOB Peripheral Select 1 Register N/A N/A SIM_GPSB1 SIM_GPSB1 SIM_GPSB1 0xF116 GPIO Perip. Select Register for GPIO C & D N/A N/A SIM_GPSCD SIM_GPSCD SIM_GPSCD 0xF117 Internal Peripheral. Select Register for PWM N/A N/A SIM_ISPWM SIM_ISPWM SIM_ISPWM 0xF118 Internal Peripheral Select Register for DAC N/A N/A SIM_IPSDAC SIM_IPSDAC SIM_IPSDAC 0xF119 Internal Peripheral Select Register for TMRA N/A N/A SIM_IPSTMRA SIM_IPSTMRA SIM_IPSTMRA 0xF11A Table 14-1 Legacy and Revised Acronyms (Continued) Register Name Peripheral Reference Manual Data Sheet Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym Start End

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 177 Preliminary

56F8037 Data Sheet, Rev. 3

178 Freescale Semiconductor

Electrical Design Considerations 56F8037 Data Sheet, Rev. 3 Freescale Semiconductor 179 Preliminary

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