56F803 MOTOROLA | Alldatasheet
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Technical content
© Motorola, Inc., 2004. All rights reserved.
- Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 3 1 . 5 K × 16-bit words Program Flash 512 × 16-bit words Program RAM 4 K × 16-bit words Data Flash 2 K × 16-bit words Data RAM 2 K × 16-bit words Boot Flash Up to 64K × 16-bit words each of external Program and Data memory 6-channel PWM module Two 4-channel 12-bit ADCs Quadrature Decoder CAN 2.0 B module Serial Communication Interface (SCI) Serial Peripheral Interface (SPI) Up to two General Purpose Quad Timers J T A G / O n C ETM port for debugging 16 shared GPIO lines 100–pin LQFP package
Figure 1. 56F803 Block Diagram
- • EXTBOOT Current Sense Inputs3 Quadrature Decoder 0 / Quad Timer A CAN 2.0A/B CLKO External Address Bus Switch Bus Control External Data Bus Switch External Bus Interface Unit RD Enable WR Enable DS Select PS Select A[00:05] D[00:15] A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 Quad Timer C VREF Quad Timer B *includes TCS pin which is reserved for factory use and is tied to VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
1.1 56F803 Features
1.1.1 Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface
1.1.2 Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution — 31.5K × 16-bit words of Program Flash — 512K × 16-bit words of Program RAM — 4K × 16-bit words of Data Flash — 2K × 16-bit words of Data RAM — 2K × 16-bit words of Boot Flash Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states — As much as 64K × 16 bits of Data memory — As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F803
Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes, supports Motorola’s patented dead time distortion correction Two 12-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and PWM modules can be synchronized Quadrature Decoder with four inputs (shares pins with Quad Timer ) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins CAN 2.0 B module with 2-pin ports for transmit and receive Serial Communication Interface (SCI) with two pins (or two additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins Sixteen multiplexed General Purpose I/O (GPIO) pins External reset input pin for hardware reset JTAG/On-Chip Emulation (OnCE™ ) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock
1.1.4 Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available 1.2 56F803 Description The 56F803 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F803 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Program and Data Flash memories can be independently bulk–erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal outputs (the module is also capable of supporting three independent PWM functions, for a total of six PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters and patented PWM waveform distortion correction circuit are also provided. The PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM module provides a reference output to synchronize the ADC. The 56F803 incorporates a separate Quadrature Decoder capable of capturing all four transitions on the two- phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include a Serial Communications Interface (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller are also included on the 56F803.
1.3 State of the Art Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to- use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
1.4 Product Documentation
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors. Table 1. 56F803 Chip Documentation
1.5 Data Sheet Conventions
807 User’s Manual
“asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
- Values for VIL, VOL , VIH, and VOH are defined by individual product specifications.
Freescale Semiconductor, Inc.
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 18, each table row describes the signal or signals present on a pin. Table 2. Functional Group Pin Allocations
Description
Power (VDD or VDDA )7 Table 3 Ground (VSS or VSSA )7 Table 4 Supply Capacitors 2 Table 5 PLL and Clock 3 Table 6 Address Bus1 16 Table 7 Data Bus 16 Table 8 Bus Control 4 Table 9 Interrupt and Program Control 4 Table 10 Pulse Width Modulator (PWM) Port 12 Table 11 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins
4 Table 12
- Alternately, Quad Timer pins
4 Table 13
Serial Communications Interface (SCI) Port1 2 Table 14 CAN Port 2 Table 15 Analog to Digital Converter (ADC) Port 9 Table 16 Quad Timer Module Port 2 Table 17 JTAG/On-Chip Emulation (OnCE) 6 Table 18 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 2. 56F803 Signals Identified by Functional Group1
- Alternate pin functionality is shown in parenthesis.
Freescale Semiconductor, Inc.
2.2 Power and Ground Signals
2.3 Clock and Phase Locked Loop Signals
Table 3. Power Inputs
6 VDD Power — These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
1 VDDA Analog Power— This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low noise 3.3V supply. Table 4. Grounds
5 VSS GND — These pins provide grounding for the internal structures of the chip, and
should all be attached to VSS. 1 VSSA Analog Ground— This pin supplies an analog ground.
1 TCS TCS — This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS. Table 5. Supply Capacitors Table 6. PLL and Clock
1 EXTAL Input Input External Crystal Oscillator Input— This input should be
more information, please refer to Section 3.5.
1 XTAL Input/
information, please refer to Section 3.5. more information, please refer to Section 3.5.3. Freescale Semiconductor, Inc.
2.4 Address, Data, and Bus Control Signals
CLKOSEL[4:0] bits in CLKOSR. Table 7. Address Bus Signals
6 A0–A5 Output Tri-stated Address Bus— A0–A5 specify the address for external Program
2 A6 –A7
pins that can be individually programmed as input or output pins. After reset, the default state is Address Bus.
8 A8 –A15
Program or Data memory accesses. pins that can be individually programmed as input or output pins. After reset, the default state is Address Bus. Table 8. Data Bus Signals
16 D0 –D15 Input/
external bus is inactive. Internal pull-ups may be active. Table 6. PLL and Clock (Continued) Freescale Semiconductor, Inc.
2.5 Interrupt and Program Control Signals
Table 9. Bus Control Signals
1 PS Output Tri-stated Program Memory Select— PS is asserted low for external Program
1 DS Output Tri-stated Data Memory Select— DS is asserted low for external Data memory
1 WR Output Tri-stated Write Enable— WR is asserted during external memory write cycles. connected directly to the WE pin of a Static RAM. 1 RD Output Tri-stated Read Enable— RD is asserted during external memory read cycles. Table 10. Interrupt and Program Control Signals
1 IRQA Input
to be level-sensitive or negative-edge- triggered.
1 IRQB Input
sensitive or negative-edge-triggered. Freescale Semiconductor, Inc.
2.6 Pulse Width Modulator (PWM) Signals
1 RESET Input
fixed number of internal clocks. module. In this case, assert RESET, but do not assert TRST.
1 EXTBOOT Input
boot from off-chip memory. Otherwise, it is tied to VSS . Table 11. Pulse Width Modulator (PWMA) Signals 6 PWMA0 –5 Output Tri-stated PWMA0 –5— These are six PWMA output pins.
3 ISA0–2 Input
3 FAULTA0 –2 Input
conditions originate off-chip. Table 10. Interrupt and Program Control Signals (Continued) Freescale Semiconductor, Inc.
2.7 Serial Peripheral Interface (SPI) Signals
Table 12. Serial Peripheral Interface (SPI) Signals
1 MISO
input to a master device and an output from a slave device. impedance state if the slave device is not selected. individually programmed as an input or output pin. After reset, the default state is MISO.
1 MOSI
output from a master device and an input to a slave device. individually programmed as an input or output pin. After reset, the default state is MOSI.
1 SCLK
serves as the data clock input. individually programmed as an input or output pin. After reset, the default state is SCLK. individually programmed as an input or output pin. After reset, the default state is SS. Freescale Semiconductor, Inc.
2.8 Quadrature Decoder Signals Serial Communications
2.9 Interface (SCI) Signals
2.10 CAN Signals
Table 13. Quadrature Decoder (Quad Dec0) Signals
1 PHASEA0
1 PHASEB0
1 INDEX0
1 HOME0
Table 14. Serial Communications Interface (SCI0) Signals
1 TXD0
be individually programmed as an input or output pin. After reset, the default state is SCI output.
1 RXD0
be individually programmed asan input or output pin. After reset, the default state is SCI input. Table 15. CAN Module Signals
1 MSCAN_ RX Input
pin has an internal pull-up resistor. open-drain output and a pull-up resistor is needed. Freescale Semiconductor, Inc.
2.11 Analog-to-Digital Converter (ADC) Signals
2.12 Quad Timer Module Signals
2.13 JTAG/OnCE
Table 16. Analog to Digital Converter Signals
4 ANA0 –3 Input Input ANA0 –3— Analog inputs to ADC channel 1
4 ANA4 –7 Input Input ANA4 –7— Analog inputs to ADC channel 2
VDDA -0.3V for optimal performance. Table 17. Quad Timer Module Signals
2 TD1 –2 Input/Output Input TD1 –2— Timer D Channel 1–2
Table 18. JTAG/On-Chip Emulation (OnCE) Signals
1 TCK Input
port. The pin is connected internally to a pull-down resistor.
1 TMS Input
edge of TCK and has an on-chip pull-up resistor.
1 TDI Input
of TCK and has an on-chip pull-up resistor.
1 TDO Output Tri-stated Test Data Output— This tri-statable output pin provides a serial
1 TRST Input
assert RESET, but do not assert TRST.
1 DE Output Output Debug Event— DE provides a low pulse on recognized debug
Freescale Semiconductor, Inc.
3.1 General Characteristics
of 3.3V I/O levels while being able to receive 5V levels without being damaged. enhanced if unused inputs are tied to an appropriate voltage level. Table 19. Absolute Maximum Ratings Freescale Semiconductor, Inc.
- Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
- Junction to ambient thermal resistance, Theta-JA (R θJA) was simulated to be equivalent to the
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
- Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the
is being used with a heat sink.
- Thermal Characterization Parameter, Psi-JT (Ψ JT ), is the “resistance” from junction to reference
estimate junction temperature in steady state customer environments. Table 20. Recomended Operating Conditions Table 21. Thermal Characteristics6 Freescale Semiconductor, Inc.
- Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
- See Section 5.1 from more details on thermal design considerations.
3.2 DC Electrical Characteristic
Table 22. DC Electrical Characteristics Freescale Semiconductor, Inc.
- Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS,
- Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
- PWM pin output source current measured with 50% duty cycle.
- PWM pin output sink current measured with 50% duty cycle.
- I DDT = IDD + IDDA (Total supply current for VDD + VDDA )
- Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
- Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail;
linearly affects wait IDD ; measured with PLL enabled.
- This low-voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same
V EIO interrupt is generated).
- This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal
interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V).
- Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While
reached, at which time it self-regulates. Table 22. DC Electrical Characteristics (Continued) Freescale Semiconductor, Inc.
Figure 3. Maximum Run IDD vs. Frequency (see Note 6. in Table 16)
3.3 AC Electrical Characteristics
table. In Figure 4 the levels of VIH and VIL for an input signal are shown. Figure 4. Input Signal Measurement References Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data V alid state, when a signal level has reached VOL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
3.4 Flash Memory Characteristics
Figure 5. Signal States Table 23. Flash Memory Truth Table
- X address enable, all rows are disabled when XE = 0
- Y address enable, YMUX is disabled when YE = 0
- Output enable, tri-state Flash data out bus when OE = 0
- Defines mass erase cycle, erase whole block
- Defines non-volatile store cycle
Table 24. IFREN Truth Table Freescale Semiconductor, Inc.
Figure 8. Flash Mass Erase Cycle
3.5 External Clock Operation
3.5.1 Crystal Oscillator
external load capacitors should be used. Freescale Semiconductor, Inc.
frequency of operation of the crystal oscillator circuit. Figure 9. Connecting to a Crystal Oscillator
3.5.2 Ceramic Resonator
design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown. Figure 9 no external load capacitors should be used. Figure 10. Connecting a Ceramic Resonator resonators (which contain an internal bypass capacitor to ground).
3.5.3 External Clock Source
source is connected to XTAL and the EXTAL pin is grounded. Figure 11. Connecting an External Clock Signal Freescale Semiconductor, Inc.
Figure 12. External Clock Timing
3.5.4 Phase Locked Loop Timing
Table 26. External Clock Operation Timing Requirements3
- See Figure 11 for details on using the recommended connection of an external clock driver.
- The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
- Parameters listed are guaranteed by design.
Table 27. PLL Timing
- An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
- ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter
- This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
3.6 External Bus Asynchronous Timing
Table 28. External Bus Asynchronous Timing1, 2
- Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Figure 13. External Bus Asynchronous Timing Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Freescale Semiconductor, Inc.
Figure 19. Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Table 30. SPI Timing1 Freescale Semiconductor, Inc.
Figure 23. SPI Slave Timing (CPHA = 1)
3.9 Quad Timer Timing
Table 31. Timer Timing1, 2
- In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.10 Quadrature Decoder Timing
Figure 24. Timer Timing Table 32. Quadrature Decoder Timing1,2
- Parameters listed are guaranteed by design.
Figure 25. Quadrature Decoder Timing Freescale Semiconductor, Inc.
3.11 Serial Communication Interface (SCI) Timing
Figure 26. RXD Pulse Width Figure 27. TXD Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 33. SCI Timing4
- f MAX is the frequency of operation of the system clock in MHz.
- The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
- The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
- Parameters listed are guaranteed by design.
Table 34. ADC Characteristics Freescale Semiconductor, Inc.
Figure 28. Equivalent Analog Input Circuit
- Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
- Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
- Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
- Sampling capacitor at the sample and hold circuit. (1pf)
- For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to
- V REF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF
- Measured in 10-90% range.
- LSB = Least Significant Bit.
- Guaranteed by characterization.
Table 34. ADC Characteristics (Continued) Freescale Semiconductor, Inc.
Figure 29. Bus Wakeup Detection
3.13 Controller Area Network (CAN) Timing
Table 35. CAN Timing2
- If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.14 JTAG Timing
Table 36. JTAG Timing1, 3
- Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
- TCK frequency of operation must be less than 1/8 the processor rate.
- Parameters listed are guaranteed by design.
Figure 30. Test Clock Input Timing Diagram Freescale Semiconductor, Inc.
4.1 Package and Pin-Out Information 56F803
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803. Figure 34. Top View, 56F803 100-pin LQFP Package Freescale Semiconductor, Inc.
Table 37. 56F803 Pin Identification By Pin Number
1 D10 26 A14 51 AN2 76 TXD0
2 D11 27 A15 52 AN3 77 RXD0
3 D12 28 V SS 53 AN4 78 EXTBOOT
4 D13 29 WR 54 AN5 79 RESET
5 D14 30 RD 55 AN6 80 DE
6 D15 31 IRQA 56 AN7 81 CLKO
10 A1 35 TMS 60 V DDA 85 MISO
11 A2 36 TDI 61 V DD 86 MOSI
12 A3 37 TDO 62 V DD 87 SCLK
13 A4 38 TRST 63 V SS 88 VCAPC
14 A5 39 VCAPC 64 PHASEA0 89 D0
15 A6 40 ISA0 65 PHASEB0 90 D1
16 A7 41 ISA1 66 V DD 91 D2
17 A8 42 ISA2 67 V SS 92 V DD
18 A9 43 FAULTA0 68 INDEX0 93 V SS
19 A10 44 MSCAN_TX 69 HOME0 94 D3
20 A11 45 FAULTA1 70 PWMA0 95 D4
21 A12 46 MSCAN_RX 71 PWMA1 96 D5
22 A13 47 FAULTA2 72 PWMA2 97 D6
23 V DD 48 VREF 73 PWMA3 98 D7
24 PS 49 AN0 74 PWMA4 99 D8
25 DS 50 AN1 75 PWMA5 100 D9
Freescale Semiconductor, Inc.
Figure 35. 100-pin LQPF Mechanical Information
- DIMENSIONING AND TOLERANCING PER
- CONTROLLING DIMENSION: MILLIMETER.
- DATUM PLANE -AB- IS LOCATED AT BOTTOM
- DA TUMS -T-, -U-, AND -Z- TO BE DETERMINED
- DIMENSIONS S AND V TO BE DETERMINED
AT S E AT IN G P LA N E -A C -.
- DIMENSIONS A AND B DO NOT INCLUDE
PROTRUSION IS 0.250 (0.010) PER SIDE.
- DIMENSION D DOES NOT INCLUDE DAMBAR
ON THE LOWER RADIUS OR THE FOOT. AND AN ADJACENT LEAD IS 0.070 (0.003).
- MINIMUM SOLDER PLATE THICKNESS
- EXACT SHAPE OF EACH CORNER MAY V ARY
Freescale Semiconductor, Inc.
Thermal Design Considerations 56F803 Technical Data 43 Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: Where: TA = ambient temperature °C R θJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: R θJA = package junction-to-ambient thermal resistance °C/W R θJC = package junction-to-case thermal resistance °C/W R θCA = package case-to-ambient thermal resistance °C/W R θJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA . For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. T J T A PD R θJA×()+= R θJA R θJC R θCA+= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Electrical Design Considerations 56F803 Technical Data 45
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation: Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD /VSS pairs, including VDDA /VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and V SS (GND) pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a high- grade capacitor such as a tantalum capacitor. Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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Electrical Design Considerations 56F803 Technical Data 47 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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