56F801 MOTOROLA | Alldatasheet
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Technical content
© Motorola, Inc., 2004. All rights reserved.
- Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes Hardware DO and REP loops 6-channel PWM Module Two 4-channel, 12-bit ADCs Serial Communications Interface (SCI) 8 K × 16-bit words Program Flash 1 K × 16-bit words Program RAM 2 K × 16-bit words Data Flash 1 K × 16-bit words Data RAM 2 K × 16-bit words Boot Flash Serial Peripheral Interface (SPI) General Purpose Quad Timer J T A G / O n C ETM port for debugging On-chip relaxation oscillator 1 1 s h a r e d G P I O 48-pin LQFP Package
Figure 1. 56F801 Block Diagram
- • VREF *includes TCS pin which is reserved for factory use and is tied to VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
1.1 56F801 Features
1.1.1 Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface
1.1.2 Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution — 8K × 16 bit words of Program Flash — 1K × 16-bit words of Program RAM — 2K × 16-bit words of Data Flash — 1K × 16-bit words of Data RAM — 2K × 16-bit words of Boot Flash Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces (JTAG , SPI)
1.1.3 Peripheral Circuits for 56F801
Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime insertion; supports both center- and edge-aligned modes Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two 4-multiplexed inputs; ADC and PWM modules can be synchronized General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines) Serial Communication Interface (SCI) with two pins (or two additional GPIO lines) Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Eleven multiplexed General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) watchdog timer One dedicated external interrupt pin External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™ ) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for lower system cost and two additional GPIO lines
1.1.4 Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available 1.2 56F801 Description The 56F801 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F801 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
PWM modules provide a reference output to synchronize the Analog-to-Digital Converters. in the choice of either on-chip or externally supplied frequency reference for chip timing operations. Application code is used to select which source is to be used.
1.3 State of the Art Development Environment
use component-based software application creation with an expert knowledge system. complete, scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors. Table 1. 56F801 Chip Documentation Freescale Semiconductor, Inc.
1.5 Data Sheet Conventions
This data sheet uses the following conventions: Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 13, each table row describes the signal or signals present on a pin. OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 1. Values for VIL, VOL , VIH, and VOH are defined by individual product specifications. PIN True Asserted V IL/VOL PIN False Deasserted V IH/VOH PIN True Asserted V IH/VOH PIN False Deasserted V IL/VOL Table 2. Functional Group Pin Allocations
Description
Power (VDD or VDDA )5 Table 3 Ground (VSS or VSSA )6 Table 4 Supply Capacitors 2 Table 5 PLL and Clock 2 Table 6 Interrupt and Program Control 2 Table 7 Pulse Width Modulator (PWM) Port 7 Table 8 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins
4 Table 9
Serial Communications Interface (SCI) Port1 2 Table 10 Analog-to-Digital Converter (ADC) Port 9 Table 11 Quad Timer Module Port 3 Table 12 JTAG/On-Chip Emulation (OnCE) 6 Table 13 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 2. 56F801 Signals Identified by Functional Group1
- Alternate pin functionality is shown in parenthesis.
Freescale Semiconductor, Inc.
2.2 Power and Ground Signals
2.3 Clock and Phase Locked Loop Signals
Table 3. Power Inputs
4 VDD Power — These pins provide power to the internal structures of the chip, and should
1 VDDA Analog Power— This pin is a dedicated power pin for the analog portion of the chip
and should be connected to a low noise 3.3V supply. Table 4. Grounds
4 VSS GND — These pins provide grounding for the internal structures of the chip,
and should all be attached to VSS. 1 VSSA Analog Ground— This pin supplies an analog ground.
1 TCS TCS — This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS. Table 5. Supply Capacitors and VPP proper chip operation). For more information, refer to Section 5.2. Table 6. PLL and Clock
1 EXTAL
information, please refer to Section 3.5. Freescale Semiconductor, Inc.
2.4 Interrupt and Program Control Signals
2.5 Pulse Width Modulator (PWM) Signals
1 XTAL
please refer to Section 3.5. information, please refer to Section 3.5.3. Table 7. Interrupt and Program Control Signals
1 IRQA Input
level-sensitive or negative-edge- triggered.
1 RESET Input
Input Reset— This input is a direct hardware reset on the processor. internal clocks, after a fixed number of internal clocks. assert RESET, but do not assert TRST. Table 8. Pulse Width Modulator (PWMA) Signals 6 PWMA0-5 Output Tri-stated PWMA0-5 — These are six PWMA output pins.
1 FAULTA0 Input
Table 6. PLL and Clock (Continued) Freescale Semiconductor, Inc.
2.6 Serial Peripheral Interface (SPI) Signals
Table 9. Serial Peripheral Interface (SPI) Signals
1 MISO
input to a master device and an output from a slave device. impedance state if the slave device is not selected. that can be individually programmed as input or output pin. After reset, the default state is MISO.
1 MOSI
output from a master device and an input to a slave device. that can be individually programmed as input or output pin. After reset, the default state is MOSI.
1 SCLK
serves as the data clock input. that can be individually programmed as an input or output pin. After reset, the default state is SCLK. that can be individually programmed as an input or output pin. After reset, the default state is SS. Freescale Semiconductor, Inc.
2.7 Serial Communications Interface (SCI) Signals
2.8 Analog-to-Digital Converter (ADC) Signals
2.9 Quad Timer Module Signals
Table 10. Serial Communications Interface (SCI0) Signals
1 TXD0
After reset, the default state is SCI output.
1 RXD0
After reset, the default state is SCI input. Table 11. Analog to Digital Converter Signals
4 ANA0-3 Input Input ANA0-3 — Analog inputs to ADC, channel 1
4 ANA4-7 Input Input ANA4-7 — Analog inputs to ADC, channel 2
VDDA -0.3V for optimal performance. Table 12. Quad Timer Module Signals
3 TD0-2
After reset, the default state is the quad timer input. Freescale Semiconductor, Inc.
2.10 JTAG/OnCE
3.1 General Characteristics
of 3.3V I/O levels while being able to receive 5V levels without being damaged. Table 13. JTAG/On-Chip Emulation (OnCE) Signals
1 TCK Input
synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.
1 TMS Input
and has an on-chip pull-up resistor.
1 TDI Input
an on-chip pull-up resistor.
1 TDO Output Tri-stated Test Data Output— This tri-statable output pin provides a serial output
Shift-DR controller states, and changes on the falling edge of TCK.
1 TRST Input
module. In this case, assert RESET, but do not assert TRST. 1 DE Output Output Debug Event— DE provides a low pulse on recognized debug events. Freescale Semiconductor, Inc.
damage due to high static voltage or electrical fields. Table 14. Absolute Maximum Ratings Table 15. Recommended Operating Conditions Freescale Semiconductor, Inc.
- Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
- Junction to ambient thermal resistance, Theta-JA (R θJA) was simulated to be equivalent to the
for forced convection or with the non-single layer boards is Theta-JMA.
- Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured
values using the cold plate technique with the cold plate temperature used as the "case" temperature.
- Thermal Characterization Parameter, Psi-JT (Ψ JT ), is the "resistance" from junction to reference
estimate junction temperature in steady state customer environments.
- Junction temperature is a function of on-chip power dissipation, package thermal resistance,
components on the board, and board thermal resistance.
- See Section 5.1 from more details on thermal design considerations.
Table 16. Thermal Characteristics6 Freescale Semiconductor, Inc.
3.2 DC Electrical Characteristics
Table 17. DC Electrical Characteristics Freescale Semiconductor, Inc.
- Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
- Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
- Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
- PWM pin output source current measured with 50% duty cycle.
- PWM pin output sink current measured with 50% duty cycle.
- I DDT = IDD + IDDA (Total supply current for VDD + VDDA )
- Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
- Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC
wait IDD ; measured with PLL enabled.
- This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential
- This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is
be generated unless the external power supply drops below the minimum specified value (3.0V).
- Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
Table 17. DC Electrical Characteristics (Continued) Freescale Semiconductor, Inc.
Figure 3. Maximum Run IDD vs. Frequency (see Note 7. in Table 17)
3.3 AC Electrical Characteristics
table. In Figure 4 the levels of VIH and VIL for an input signal are shown. Figure 4. Input Signal Measurement References Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data V alid state, when a signal level has reached VOL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
Figure 5. Signal States
3.4 Flash Memory Characteristics
Table 18. Flash Memory Truth Table
- X address enable, all rows are disabled when XE = 0
- Y address enable, YMUX is disabled when YE = 0
- Output enable, tri-state Flash data out bus when OE = 0
- Defines mass erase cycle, erase whole block
- Defines non-volatile store cycle
Table 19. IFREN Truth Table Freescale Semiconductor, Inc.
Figure 8. Flash Mass Erase Cycle
3.5 External Clock Operation
conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator. determines the speed at which chip operations occur. relaxation oscillator is selected, and this is the default value of the bit when power is first applied.
3.5.1 Crystal Oscillator
Freescale Semiconductor, Inc.
frequency of operation of the crystal oscillator circuit. Figure 9. External Crystal Oscillator Circuit
3.5.2 Ceramic Resonator
design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown. Figure 9 no external load capacitors should be used. Figure 10. Connecting a Ceramic Resonator resonators (which contain an internal bypass capacitor to ground).
3.5.3 External Clock Source
source is connected to XTAL and the EXTAL pin is grounded. Freescale Semiconductor, Inc.
Figure 11. Connecting an External Clock Signal Figure 12. External Clock Timing
3.5.4 Use of On-Chip Relaxation Oscillator
switched until the desired clock is enabled and stable. allowing incremental adjustment until the desired frequency accuracy is achieved. Table 21. External Clock Operation Timing Requirements3
- See Figure 11 for details on using the recommended connection of an external clock driver.
- May not exceed 60MHz for the DSP56F801FA60 device.
- The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
- Parameters listed are guaranteed by design.
Note: The midpoint is VIL + (VIH – VIL)/2. Freescale Semiconductor, Inc.
Figure 13. Typical Relaxation Oscillator Frequency vs. Temperature Table 22. Relaxation Oscillator Characteristics
- Over full temperature range.
Freescale Semiconductor, Inc.
Figure 14. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC
3.5.5 Phase Locked Loop Timing
Table 23. PLL Timing
- An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
- ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter
- Will not exceed 60MHz for the DSP56F801FA60 device.
- This is the minimum time required after the PLL setup is changed to ensure reliable operation.
Freescale Semiconductor, Inc.
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 24. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
- In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
- Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
- The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
- The interrupt instruction fetch is visible on the pins only in Mode 3.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.7 Serial Peripheral Interface (SPI) Timing
Table 25. SPI Timing1
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
3.8 Quad Timer Timing
3.9 Serial Communication Interface (SCI) Timing
Table 26. Timer Timing1, 2
- In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
- Parameters listed are guaranteed by design.
Figure 25. Timer Timing Table 27. SCI Timing4
- f MAX is the frequency of operation of the system clock in MHz.
- The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
- The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
- Parameters listed are guaranteed by design.
Freescale Semiconductor, Inc.
Figure 26. RXD Pulse Width Figure 27. TXD Pulse Width
3.10 Analog-to-Digital Converter (ADC) Characteristics
Table 28. ADC Characteristics Freescale Semiconductor, Inc.
Figure 28. Equivalent Analog Input Circuit
- Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
- Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
- Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
- Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input
- For optimum ADC performance, keep the minimum VADCIN value > 250mV. Inputs less than 250mV volts may
convert to a digital output code of 0 or cause erroneous conversions.
- V REF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF
- Measured in 10-90% range.
- LSB = Least Significant Bit.
- Guaranteed by characterization.
Table 28. ADC Characteristics (Continued) Freescale Semiconductor, Inc.
3.11 JTAG Timing
Table 29. JTAG Timing1, 3
- Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
- TCK frequency of operation must be less than 1/8 the processor rate.
- Parameters listed are guaranteed by design.
Figure 29. Test Clock Input Timing Diagram Freescale Semiconductor, Inc.
4.1 Package and Pin-Out Information 56F801
This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801. Figure 33. Top View, 56F801 48-pin LQFP Package Freescale Semiconductor, Inc.
Table 30. 56F801 Pin Identification by Pin Number
1 TD0 13 TCS 25 RESET 37 ANA5
6 MOSI 18 VCAPC2 30 FAULTA0 42 V DD
10 V DD 22 XTAL 34 VREF 46 PWMA3
11 RXD0 23 TDO 35 ANA3 47 PWMA4
12 DE 24 TRST 36 ANA4 48 PWMA5
Freescale Semiconductor, Inc.
Figure 34. 48-pin LQFP Mechanical Information
- DIMENSIONING AND TOLERANCING PER
- CONTROLLING DIMENSION: MILLIMETER.
- DA TUM PLANE AB IS LOCA TED AT BOTTOM
- DATUMS T, U, AND Z TO BE DETERMINED AT
- DIMENSIONS S AND V TO BE DETERMINED
- DIMENSIONS A AND B DO NOT INCLUDE
ARE DETERMINED AT DA TUM PLANE AB.
- DIMENSION D DOES NOT INCLUDE DAMBAR
- MINIMUM SOLDER PLA TE THICKNESS
- EXACT SHAPE OF EACH CORNER IS
7.000 BSC
Freescale Semiconductor, Inc.
Thermal Design Considerations 56F801 Technical Data 39 Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: Where: TA = ambient temperature °C R θJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: R θJA = package junction-to-ambient thermal resistance °C/W R θJC = package junction-to-case thermal resistance °C/W R θCA = package case-to-ambient thermal resistance °C/W R θJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA . For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. T J T A PD R θJA×()+= R θJA R θJC R θCA+= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation: Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD /VSS pairs, including VDDA /VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and V SS (GND) pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a high- grade capacitor such as a tantalum capacitor. Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Electrical Design Considerations 56F801 Technical Data 41 Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
office or authorized distributor to determine availability and to order parts. Table 31. DSP56F801 Ordering Information Freescale Semiconductor, Inc.
Electrical Design Considerations 56F801 Technical Data 43 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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