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16-bit Digital Signal Controllers freescale.com 56F827 Evaluation Module User Manual DSP56F827EVMUM Rev. 2

Table of Contents, Rev. 2 Freescale Semiconductor i Preface vii Chapter 1 Introduction Chapter 2 Technical Summary

56F827EVM User Manual, Rev. 2 ii Freescale Semiconductor Appendix A 56F827EVM Schematics Appendix B 56F827EVM Bill of Material

List of Figures, Rev. 2 Freescale Semiconductor iii

56F827EVM User Manual, Rev. 2 iv Freescale Semiconductor

List of Tables, Rev. 2 Freescale Semiconductor v

56F827EVM User Manual, Rev. 2 vi Freescale Semiconductor

Preface, Rev. 2 Freescale Semiconductor vii Preface This reference manual describes in detail the hardware on the 56F827 Evaluation Module. Audience This document is intended for application developers who are creating software for devices using the 56F827 part. Organization This manual is organized into two chapters and two appendixes.

• Chapter 1, Introduction - provides an overview of the EVM and its features.
• Chapter 2, Technical Summary - describes in detail the 56F827 hardware.
• Appendix A, "56F827EVM Schematics" contains the schematics of the DSP56F827EVM.
• Appendix B, 56F827EVM Bill of Material - provides a list of the materials used on the DSP56F827EVM board. Suggested Reading More documentation on the 56F827 and the DSP56F827EVM kit may be found at URL: www.freescale.com

DSP56F827EVM User Manual, Rev. 2 viii Freescale Semiconductor Notation Conventions This manual uses the following notational conventions: Term or Value Symbol Examples Exceptions Active High Signals (Logic One) No special symbol attached to the signal name CLKO Active Low Signals (Logic Zero) Noted with an overbar in text and in most figures WE OE In schematic drawings, Active Low Signals may be noted by a backslash: /WE Hexadecimal Values Begin with a “$” symbol $0FF0 $80 Decimal Values No special symbol attached to the number Binary Values Begin with the letter “b” attached to the number b1010 b0011 Numbers Considered positive unless specifically noted as a negative value -10 Voltage is often shown as positive: +3.3V Blue Text Linkable on-line ...refer to Figure 1-1 Bold Reference sources, paths, emphasis ...see:

Preface, Rev. 2 Freescale Semiconductor ix Definitions, Acronyms, and Abbreviations Definitions, acronyms and abbreviations for terms used in this document are defined below for reference. Codec COder/DECoder; a part used to convert analog signals to digital (Coder) and digital signals to analog (Decoder) EEPROM Electrically Erasable Programmable Read Only Memory EVM Evaluation Module; a hardware platform which allows a customer to evaluate the silicon and develop their application GPIO General Purpose Input and Output Port; does not share pin functionality with any other peripheral on the chip and can only be set as an input, output or level-sensitive interrupt input IC Integrated Circuit JTAG Joint Test Action Group; a bus protocol/interface used for test and debug LQFP Low-profile Quad Flat Pack MPIO Multi-Purpose Input/Output Port; shares package pins with other peripherals on the chip and can function as a GPIO OnCE TM On-Chip Emulation, a debug bus and port created by Freescale to enable designers to create a low-cost hardware interface for a professional quality debug environment PCB Printed Circuit Board PLL Phase Locked Loop RAM Random Access Memory ROM Read-Only Memory SCI Serial Communications Interface Port SPI Serial Peripheral Interface Port SRAM Static Random Access Memory SSI Synchronous Serial Interface Port WS Wait State

DSP56F827EVM User Manual, Rev. 2 x Freescale Semiconductor References The following sources were referenced to produce this manual: [1] DSP56800 Family Manual , DSP56800FM, Freescale Semiconductor [2] DSP56F826/827 Digital Signal Processor User’ s Manual , DSP56F826_827UM, Freescale Semiconductor [3] DSP56F827 Technical Data , DSP56F827, Freescale Semiconductor

Introduction, Rev. 2 Freescale Semiconductor 1-1 Chapter 1 Introduction The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a hardware tool allowing the development of applications that use the 56F827. The 56F827EVM is an evaluation module board that includes a 56F827 part, 16-bit stereo codec, external memory and a daughter card expansion interface. The daughter card expansion connectors are for signal monitoring and user feature expandability. The 56F827EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800 architecture. The tools and examples provided with the 56F827EVM facilitate evaluation of the feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables the user to develop and simulate routines, download the software to on-chip or on-board RAM, run it, and debug it using a debugger via the JTAG/OnCE TM port. The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user-developed software at full-speed, until the break conditions are satisfied. The ability to examine and modify all user accessible registers, memory and peripherals through the OnCE port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables the user to connect external hardware peripherals. The on-board peripherals can be disabled, providing the user with the ability to reassign any and all of the controller's peripherals. The OnCE port's unobtrusive design means that all of the memory on the board and on the controller chip are available to the user. 1.1 56F827EVM Architecture The 56F827EVM facilitates the evaluation of various features present in the 56F827 part. The 56F827EVM can be used to develop real-time software and hardware products based

56F827EVM User Manual, Rev. 2 1-2 Freescale Semiconductor on the 56F827. The 56F827EVM provides the features necessary for a user to write and debug software, demonstrate the functionality of that software and interface with the customer's application-specific device(s). The 56F827EVM is flexible enough to allow a user to fully exploit the 56F827's features to optimize the performance of his product, as shown in Figure 1-1. 56F827 RESET MODE Address, Data & Control JTAG/OnCE XTAL/EXTAL SPI SCI SSI GPIO & GND Peripheral Daughter Card Connector RESET LOGIC MODE LOGIC Program Memory 64Kx16-bit SRAM Memory Daughter Card Connector JTAG Connector Parallel JTAG Interface 4.00MHz Crystal DSub 25-Pin Data Memory 64Kx16-bit SRAM Debug LEDs Stereo 16-bit Codec RS-232 Interface SPI EEPROM 1M-bit Power Supply IRQ InterfaceIRQ Amp Stereo Line Out Headphone Jack Stereo Line In +2.5V, +3.3V A/D DSub 9-Pin Figure 1-1. Block Diagram of the 56F827EVM 1.2 56F827EVM Configuration Jumpers Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various features on the 56F827EVM board. Table 1-1 describes the default jumper group settings.

Introduction, Rev. 2 Freescale Semiconductor 1-3 Figure 1-2. 56F827EVM Jumper Reference Table 1-1. 56F827EVM Default Jumper Options Jumper Group Comment Jumpers Connections JG1 Enable on-board Parallel JTAG Host/Target Interface NC JG2 Enable RS-232 output NC JG3 Enable on-board SRAM 1–2 JG4 Use on-board EXTAL crystal input for controller oscillator 2–3 JG5 Use on-board XTAL crystal input for controller oscillator 1–2 JG6 Selects controller’s Mode 0 operation upon exit from reset 1-2 JG7 Enable SPI EEPROM 1–2, 3–4, 5–6 & 7–8 1.3 56F827EVM Connections An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12.0V DC power supply or external +5.0V DC lab power supply to the 56F827EVM board.

+12.0V Power P1Connect cable to Parallel/Printer port with 2.1mm, receptacle connector +5.0V Lab Supply TB1 or 56F827EVM User Manual, Rev. 2 1-4 Freescale Semiconductor Figure 1-3. Connecting the 56F827EVM Cables Perform the following steps to connect the 56F827EVM cables: 1. Connect the parallel extension cable to the parallel port of the host computer. 2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the 56F827EVM board. This provides the connection which allows the host computer to control the board. 3. Make sure that the external +12.0V DC 1.2A switching power supply or the external +5.0V DC 1.0A lab power supply is not plugged into a 120V AC power source. 4. Connect the 2.1mm output power plug from the external switching power supply into P1, shown in Figure 1-3, on the 56F827EVM board. Optionally, attach an external +5.0V DC lab power supply via the 2-pin terminal block, TB1. 5. Apply power to the external power supply. The green Power-On LED, LED7, will illuminate when power is correctly applied.

Technical Summary, Rev. 2 Freescale Semiconductor 2-1 Chapter 2 Technical Summary The 56F827EVM is designed as a versatile controller development card for developing real-time software and hardware products to support a new generation of applications in digital and wireless messaging, digital answering machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F827 controller, combined with the on-board 64K u16-bit external program static RAM (SRAM), 64K u16-bit external data SRAM, RS-232 interface, stereo 16-bit codec interface, Daughter Card Expansion interface and parallel JTAG interface, makes the 56F827EVM ideal for developing and implementing many audio and voice algorithms, as well as for learning the architecture and instruction set of the 56F827 processor. The main features of the 56F827EVM, with board and schematic reference designators include:

• 56F827 16-bit +2.5V/+3.3V controller operating at 80MHz [U1]
• External fast static RAM (FSRAM) memory [U2], configured as: — 64K u16 bits of program memory with 0 wait states at 70MHz — 64K u16 bits of data memory with 0 wait states at 70MHz
• 1M-bit Serial EEPROM [U4]
• 4.00MHz crystal oscillator for controller frequency generation [Y1]
• Optional external oscillator frequency input connector [JG4 and JG5]
• Joint Test Action Group (JTAG) port interface connector for an external debug Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port cable [P2]
• RS-232 interface for easy connection to a host processor [U3 and P3]
• 16-bit stereo codec interface [U5, P4 and P5]
• Stereo headphone interface [U6 and P6]

56F827EVM User Manual, Rev. 2 2-2 Freescale Semiconductor

• Codec sample rate selector [S4]
• Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI, SSI, SPI or GPIO-compatible peripheral to the controller[J2]
• Memory Daughter Card Expansion Connector, to allow the user to connect his own memory or memory device to the controller[J1]
• On-board power regulation from an external +12V DC-supplied power input [P1]
• On-board power regulation from an optional +5V DC-supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3] 2.1 56F827 The 56F827EVM uses a Freescale DSP56F827FG80 part, designated as U1 on the board and in the schematics. This part will operate at a maximum speed of 80MHz. A full description of the 56F827, including functionality and user information, is provided in these documents:
• DSP56F827 Technical Data, (DSP56F827): Provides features list and specifications including signal descriptions, DC power requirements, AC timing requirements and available packaging.
• DSP56F826/827 16-Bit Digital Signal Processor User’s Manual, (DSP56F826_827UM): Provides an overview description of the controller and detailed information about the on-chip components including the memory and I/O maps, peripheral functionality, and control/status register descriptions for each subsystem.
• DSP56800 Family Manual , (DSP56800FM): Provides a detailed description of the core processor, including internal status and control registers and a detailed description of the family instruction set. Refer to these documents for detailed information about chip functionality and operation. They can be found on this URL: www.freescale.com

Technical Summary, Rev. 2 Freescale Semiconductor 2-3

2.2 Program and Data Memory

The 56F827EVM uses one bank of 128Ku16-bit Fast Static RAM (GSI GS72116, labelled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical memory bank is split into two logical memory banks of 64Kx16-bits: one for program memory and the other for data memory. By using the controller’s program strobe, PS , signal line along with the memory chip’s A0 signal line, half of the memory chip is selected when program memory accesses are requested and the other half of the memory chip is selected when data memory access are requested. This memory bank will operate with zero wait-state accesses while the 56F827 is running at 70MHz. However, when running at 80MHz, the memory bank operates with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG3. 56F827 GS72116 A0-A15 PS D0-D15 RD WR A1-A16 DQ0-DQ15 OE WE CE JG3 +3.3V Jumper Pin 1-2: Enable SRAM Jumper Removed: Disable SRAM Figure 2-1. Schematic Diagram of the External Memory Interface

56F827EVM User Manual, Rev. 2 2-4 Freescale Semiconductor

2.3 SPI EEPROM Memory

A 1M-bit +3.3V SPI serial EEPROM Memory, Atmel AT45DB011-SC, is provided on the 56F827EVM, reference Figure 2-2. This memory connects directly to the SPI Port through a header on the 56F827. It can be used to load program code and data into the 56F827’s internal or external memory spaces. A jumper block is provided, JG7, to allow the user to disconnect the on-board SPI EEPROM from the SPI port and allow him to connect his own SPI port peripheral. The header details are shown in Table 2-1. 56F827 MOSI MISO SCLK GPIOF7 Serial EEPROM SDI SDO SCK CS EEPROM Enable (SPI Port Connector) Figure 2-2. SPI EEPROM Memory Block Diagram Table 2-1. SPI Port Connector Description JG7 Pin # Signal Pin # Signal 1S S / GPIO7 2 CS

3 MISO 4 SDO

5 MOSI 6 SDI

7 SCLK 8 SCK

RS-232 Serial Communications Technical Summary, Rev. 2 Freescale Semiconductor 2-5

2.4 RS-232 Serial Communications

The 56F827EVM provides an RS-232 interface by the use of an RS-232 level converter, (Maxim MAX3245EEAI, designated as U3). Refer to the RS-232 schematic diagram in Figure 2-3. The RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232 compatible signal levels and connects to the host’s serial port via connector P3. Flow control is not provided, but could be implemented using uncommitted GPIO signals. The pinout of connector P3 is listed in Table 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG2. 56F827 RS-232 Level Converter Interface TXDO RXDO R1in T1outT1in R1out FORCEOFF JG2 x 9+3.3V Jumper Removed: Enable RS-232 Jumper Pin 1-2: Disable RS-232 Figure 2-3. Schematic Diagram of the RS-232 Interface Table 2-2. RS-232 Serial Connector Description Pin # Signal Pin # Signal

1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 Jumper to 8

3 RXD 8 Jumper to 7

4 Jumper to 1 & 6 9 N/C

56F827EVM User Manual, Rev. 2 2-6 Freescale Semiconductor

2.5 Clock Source

The 56F827EVM uses a 4.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL and XTAL. The 56F827 uses its internal PLL to multiply the input frequency by 20, achieving its 80MHz maximum operating frequency. An external oscillator source can be connected to the controller by using the oscillator bypass connectors, JG4 and JG5; see Figure 2-4. If the input frequency is above 4MHz, then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 2 and 3. The input frequency would then be injected on JG5’s pin 2. If the controller needs to be synchronized to the codec’s sample frequency, then the controller’s input frequency should be jumpered using the 12.2280MHz codec frequency. If the input frequency is below 4MHz, then the input frequency can be injected on JG4’s pin 2. 56F827 EXTERNAL OSCILLATOR HEADERS JG4 EXTAL XTAL JG5 10M4.00MHz 12.2880MHz Figure 2-4. Schematic Diagram of the Clock Interface

Technical Summary, Rev. 2 Freescale Semiconductor 2-7

2.6 Operating Mode

The 56F827EVM provides a boot-up MODE selection jumper, JG6. This jumper is used to select the operating mode of the controller as it exits RESET. Refer to the DSP56F827 User’s Manual for a complete description of the chip’s operating modes. Table 2-3 shows the two operation modes available on the 56F827. Table 2-3. Operating Mode Selection Operating Mode JG6 Comment 0 1–2 Bootstrap from internal memory

3 No Jumper Bootstrap from external memory

56F827EVM User Manual, Rev. 2 2-8 Freescale Semiconductor

2.7 Debug LEDs

Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging for user programs. These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging; refer to Figure 2-5. User LED1 is controlled by Port B’s PB0 signal. User LED2 is controlled by PB1. User LED3 is controlled by PB2. User LED4 is controlled by PB3. User LED5 is controlled by PB4. User LED6 is controlled by PB5. Setting PB0, PB1, PB2, PB3, PB4 or PB5 to a Logic One value will turn on the associated LED. 56F827 INVERTING BUFFER PB0 PB1 PB2 GREEN LED YELLOW LED RED LED +3.3V GREEN LED YELLOW LED RED LED PB3 PB4 PB5 Figure 2-5. Schematic Diagram of the Debug LED Interface

2.8 Debug Support

The 56F827EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support. Two interface connectors are provided to support each of these debugging approaches. These two connectors are designated the JTAG connector and the Host Parallel Interface Connector.

Technical Summary, Rev. 2 Freescale Semiconductor 2-9

2.8.1 JTAG Connector

The JTAG connector on the 56F827EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F827’s registers. This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program. Table 2-4 shows the pin-out for this connector. Table 2-4. JTAG Connector Description Pin # Signal Pin # Signal

1 TDI 2 GND

3 TDO 4 GND

5 TCK 6 GND

7 NC 8 KEY

9 RESET

10 TMS

11 +3.3V 12 NC

13 NC 14 TRST

When this connector is used with an external Host Target Interface, the parallel JTAG interface should be disabled by placing a jumper in jumper block JG1. See Table 2-5 for this jumper’s selection options. Table 2-5. Parallel JTAG Interface Disable Jumper Selection JG1 Comment No jumpers On-board Parallel JTAG Interface Enabled 1–2 Disable on-board Parallel JTAG Interface

56F827EVM User Manual, Rev. 2 2-10 Freescale Semiconductor

2.8.2 Parallel JTAG Interface Connector

The Parallel JTAG Interface Connector, P2, allows the 56F827 to communicate with a Parallel Printer Port on a Windows PC; reference Figure 2-6. By using this connector, the user can download programs and work with the 56F827’s registers. Table 2-6 shows the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG1 should be removed, as shown in Table 2-5. DB-25 Connector Parallel JTAG Interface 56F827 TDI TDO P_TRST TMS TCK P_RESET OUT OUT OUT OUT OUT OUTIN IN IN IN IN IN EN TDI TDO TRST TMS TCK RESET JG1 +3.3V Jumper Removed: Enable JTAG I/F Jumper Pin 1-2: Disable JTAG I/F Figure 2-6. Block Diagram of the Parallel JTAG Interface

Table 2-6. Parallel JTAG Interface Connector Description Pin # Signal Pin # Signal 1N C1 4 N C

2 PORT_RESET 15 PORT_IDENT

3 PORT_TMS 16 NC

4 PORT_TCK 17 NC

5 PORT_TDI 18 GND

6 PORT_

7 NC 20 GND

8 PORT_IDENT 21 GND

9 PORT_VCC 22 GND

10 NC 23 GND

11 PORT_TDO 24 GND

12 NC 25 GND

13 PORT_CONNECT

Technical Summary, Rev. 2 Freescale Semiconductor 2-11

56F827EVM User Manual, Rev. 2 2-12 Freescale Semiconductor

2.9 External Interrupts

Two on-board push-button switches are provided for external interrupt generation, as shown in Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user to generate interrupts for his user-specific programs. 56F827 IRQA IRQB +3.3V +3.3V 10K 10K SW2 SW3 0.1µF 0.1µF Figure 2-7. Schematic Diagram of the User Interrupt Interface

Technical Summary, Rev. 2 Freescale Semiconductor 2-13

2.10 Reset

Logic is provided on the 56F827 to generate an internal Power-On RESET. Additional reset logic is provided to support the RESET signals from the JTAG connector, the Parallel JTAG Interface and the user RESET push-button; refer to Figure 2-8. RESET PUSHBUTTON MANUAL RESET JTAG_TAP_RESET JTAG_RESET RESET TRST Figure 2-8. Schematic Diagram of the RESET Interface

56F827EVM User Manual, Rev. 2 2-14 Freescale Semiconductor

2.11 Power Supply

The main power input, +12.0V DC, to the 56F827EVM is through a 2.1mm coax power jack, P1. An optional +5.0V DC power supply input is available through a 2-pin terminal block, TB1. A 1.2A power supply is provided with the 56F827EVM; however, less than 500mA is required by the EVM. The remaining current is available for user daughter card applications when connected to the daughter card interface. The power regulation on the 56F827EVM provides +5.0V DC voltage regulation for the codec’s analog circuits and to the additional voltage regulation logic on the EVM. The additional voltage regulation logic provides +2.5V DC voltage regulation for the controller’s core and +3.3V DC voltage regulation for the controller’s I/O, memory, parallel JTAG interface and supporting logic; refer to Figure 2-9. Power applied to the 56F827EVM is indicated with a Power-On LED, referenced as LED7. +5.0V DC Analog+12.0V DC Power Condition Codec 56F827+3.3V Regulator TB1 +5.0V DC GND +2.5V Regulator 56F827EVM Parts 56F827 Core +3.3V DC +2.5V DC +5.0V Regulator Figure 2-9. Schematic Diagram of the Power Supply

2.12 Stereo Codec

A 16-bit audio quality stereo codec, Crystal Semiconductor CS4218, is connected to the 56F827’s SSI port to support audio, voice and signal analysis applications. The codec is clocked with a 12.288MHz oscillator. This allows the codec to operate between a sample frequency of 8kHz and 48kHz. The sample rate can be manually set by setting the appropriate switch positions on dip switch S4. The sample rate selections possible using this three-position dip switch are detailed in Table 2-7. The codec supports +3.3V digital levels, eliminating the need for voltage-level translation circuitry. Additionally, a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on-board codec from the SSI port and to connect his own codec to the SSI port; refer to Figure 2-11. The on-board codec has analog signal conditioning

Technical Summary, Rev. 2 Freescale Semiconductor 2-15 logic, allowing direct connection to its line-level input and line-level output signals through two 1/8” stereo jacks; see Figure 2-10. Table 2-7. Codec Sample Rate Selector SW 4 Position 3 (MF6) SW 4 Position 2 (MF7) SW 4 Position 1 (MF8) Sample Rate ON ON ON 48.00kHz ON ON OFF 32.00kHz ON OFF ON 24.00kHz ON OFF OFF 19.20kHz OFF ON ON 16.00kHz OFF ON OFF 12.00KHz OFF OFF ON 9.60kHz OFF OFF OFF 8.00kHz Line-level Output RIN1 LIN1 LOUTL LOUTR A A A Line-level Output Headphone Input CS4218 LM4880 P4 P5 Figure 2-10. Codec Analog Connections

56F827EVM User Manual, Rev. 2 2-16 Freescale Semiconductor Figure 2-11. CS4218 Stereo Audio Codec

2.12.1 Analog Input/Output

The 56F827EVM uses jacks for line-level stereo input, line-level stereo output and stereo headphone output. A National Semiconductor LM4880 is used to provide the drive required for the use of headphones. This device offers a THD, which is superior to the CS4218’s on-chip headphone drive circuitry by a factor of two. The basic Analog codec connections are shown in Figure 2-10.

2.12.2 Digital Interface

The serial interface of the codec transfers digital audio data and control data into and out of the device. The SSI port, which consists of independent transmitter and receiver sections, is used for serial communication with the codec. On the controller side, the Serial Transmit Data pin, STD, is an output when data is being transmitted to the codec. The Serial Receive Data pin, SRD, is an input when data is being received from the codec. These two pins are connected to the codec’s Serial Data Input pin, SDIN, and Serial Data Output pin, SDOUT. The controller’s Transmit Serial Clock pin, STCK, provides the serial bit rate clock for the SSI interface. It is connected to the codec’s Serial Port Clock pin, SCLK. Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK.

Technical Summary, Rev. 2 Freescale Semiconductor 2-17 The device’s GPIO PORT D Bit 0 pin, PD0, is programmed to control the codec’s Active Low Reset signal, RESET. The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec’s Frame Sync signal, FSYNC. FSYNC is sampled by SCLK, with a rising edge indicating a new frame is about to start. The FSYNC frequency is always the system’s sample rate. It may be an input to the codec, or it may be an output from the codec in data mode. The basic codec digital connections are shown in Figure 2-11. The codec’s MODE is set by the three MODE selection resistors, R96-R98. In the factory default setting of MODE 4, the codec is set to be the Master of the SPI bus with its data word set at 32 bits per frame; i.e., a 16-bit Left channel and a 16-bit Right channel. The sample rate is selected on Sample Rate Selector switch S4; reference Table 2-7 for selection options. Codec control information is sent over a separate serial port using: PD1 as the Control Chip Select signal, CCS; PD2 as the Control Data Input signal, CDIN; and PD3 as the Control Clock signal, CCLK.

2.13 Daughter Card Connectors

The EVM board contains two daughter card expansion connectors. One connector, J1, contains the controller’s external memory bus signals. The other connector, J2, contains the device’s peripheral port signals.

2.13.1 Memory Daughter Card Expansion Connector

The controller’s external memory bus signals are connected to the Memory Daughter Card Expansion connector, J1. Table 2-8 shows the port signal to pin assignments. Table 2-8. Memory Daughter Card Connector Description Pin # Signal Pin # Signal

1 A10 2 A11

5 A8 6 A15

7 A7 8 A14

9 GND 10 PCS7

56F827EVM User Manual, Rev. 2 2-18 Freescale Semiconductor

2.13.2 Peripheral Daughter Card Expansion Connector

The controller’s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector, J2. Table 2-9 shows the port signal to pin assignments.

11 WR 12 A13

13 D0 14 A12

15 D1 16 D8

17 D2 18 D9

19 GND 20 GND

21 D3 22 D10

23 D4 24 D11

25 D5 26 D12

27 D6 28 D13

29 PCS6 30 PCS5

31 D7 32 D14

34 D15

35 A0 36 RD

37 A1 38 A6

39 PCS4 40 GND

41 A2 42 A5

43 A3 44 A4

45 PCS3 46 PCS2

47 +3.3V 48 +3.3V

49 GND 50 GND

51 GND

Table 2-8. Memory Daughter Card Connector Description Pin # Signal Pin # Signal

Technical Summary, Rev. 2 Freescale Semiconductor 2-19 Table 2-9. Peripheral Daughter Card Connector Description Pin # Signal Pin # Signal

1 PB0 2 PB1

3 CLKO 4 PB2

5 TA0 6 TA1

7 PB3 8 PB4

9 TA2 10 TA3

11 PB5 12 PB6

13 ANA0 14 ANA1

15 SRD 16 PB7

17 SRFS 18 PD0

19 SCLK 20 PD1

21 ANA2 22 ANA3

23 MOSI 24 PD2

25 MISO 26 PD3

27 ANA4 28 ANA5

30 PD4

31 SRCK 32 PD5

33 STFS 34 PD6

35 RESET

36 PD7

37 ANA6 38 ANA7

39 STD 40 RXD1

41 STCK 42 TXD1

43 IRQB

44 RXD0

45 IRQA 46 TXD0

47 +3.3V 48 +3.3V

56F827EVM User Manual, Rev. 2 2-20 Freescale Semiconductor

2.14 SCI Port #2

A separate connector, J4, is provided to allow the easy connection of SCI Port #2 signals along with a reference GND signal. Table 2-10. SCI Port #2 Connector J4 Signal Description

1 TXD2

2 RXD2

2.15 Test Points

The 56F827EVM board has a total of seven test points. Three digital GND test points are located in corners of the board. The +5.0VA and AGND test points are located in the bottom right, analog corner, of the board. The +2.5V and +3.3V test points are located in the upper right, power supply section, of the board.

49 ANA8 50 ANA9

Table 2-9. Peripheral Daughter Card Connector Description (Continued) Pin # Signal Pin # Signal

Appendix A, Rev. 2 Freescale Semiconductor A-1 Appendix A 56F827EVM Schematics

A A B B C C D D E E 4 4 3 3 2 2 1 1 RED LED YELLOW LED GREEN LED RED LED YELLOW LED GREEN LED DSPD Design DSP56F827 Processor and DEBUG LE DS DSP56F827EVM. DSN 1.0 1 10Monday, April 09, 2001B DSP Standard Pro ducts Division

2100 East Elliot Road

Tempe, Arizona 85284 Titl e Docum ent Date : Size Design er: Sheet of Rev.Numb er (480) 413-5090 FAX: (480) 413-2510 TCK TDI TMS /DE TCS PB0 PB1 PB2 PB3 PB4 PB5 TXD2 RXD2 A1 3 D11 A1 2 D15 A1 1 A1 4 TXD2 RXD2 D12 A1 5 D14 D10 D13 A1 0 A[0..15]D[0..15] MIS O SC LK RXD0 TXD1 MOS I /SS TXD0 RXD1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB0 PB1 PB2 /WR /RD /PS /DS EXTA L XTAL CLK O /IRQA /IRQB TA0 TA1 TA2 TA3 ST D SRFS SRD STFS STCK SRCK /RES ET XBOO T AN A0 AN A1 AN A3 AN A2 AN A5 AN A4 AN A7 AN A6 AN A8 /TR ST TMS TD O TC K TDI TC S /DE PC S2 PC S3 PC S4 PC S5 PC S6 PC S7 AN A9 +3.3V +3.3V +3.3VA +3 .3VA +3 .3V +2 .5V R80 10K DNP R81 10K DNP R79 10K DNP R92 10K R93 10K R11 27 0 U11D MC 74AC04AD 9 8 R13 27 0 U1 1E MC 74AC04AD 11 10 R14 27 0 U11F MC 74AC04AD 13 12 27 0 U1 1A MC 74AC04AD 1 2 27 0 U1 1B MC 74AC04AD 3 4 27 0 U11C MC 74AC04AD 5 6 47 K 47 K 47 K 47 K R1 0 47 K R1 2 47 K LE D1 LE D2 LE D3 LE D4 LE D5 LE D6 T1 91 T1 81 DSP56 F827FG80 125 126 127 128 124 123 122 121 120 119 118 117 100 101 102 108 107 106 105 115 116 112 110 111 109 104 103 113114 D10 D11 D12 D13 D14 D15 A0/PE0 A1/PE1 A2/PE2 A3/PE3 A4/PE4 A5/PE5 A6/PE6 A7/PE7 A8/PA0 A9/PA1 A10/PA2 A11/PA3 A12/PA4 A13/PA5 A14/PA6 A15/PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 MISO/PF6 MOSI/PF5 SCLK/PF4 SS/PF7 TXD0/SCLK0 RXD0/MOSI0 TXD1/MISO0 RXD1/SS0 SRD/PC0 STD/PC3 STFS/PC4 STCK/PC5 SRCK/PC2 RESET IRQA IRQB TDI TDO TCK TMS TRST TCS GND3 GND5 GND7 GND10 GNDC1 GNDC2 GNDC3 WR RD PS/PCS0 DS/PCS1 CLKO EXTAL XTAL VDDA_PLL VSSA_PLL VDD3 VDD5 VDD7 VDD10 VDDC1 VDDC2 SRFS/PC1 DE VDDC3 XBOOT TA0/PF0 TA2/PF2 TA1/PF1 TA3/PF3 VSSA_ADC VREFP VREFN VREFHI VREFMID ANA0 ANA1 ANA2 ANA3 ANA4 VREFLO VDDA_ADC ANA5 ANA6 ANA8 ANA7 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 VPP TXD2 RXD2 VDD1GND1 ANA9 T1 61 T1 71 56F827EVM User Manual, Rev. 2 A-2 Freescale Semiconductor Figure A-1. 56F827 Processor and Debug LEDS

A A B B C C D D E E 4 4 3 3 2 2 1 1 IRQA PUSHBUTTON OSC BYPASS IRQB PUSHBUTTON RESET PUSHBUTTON BOOT MODE JUMPER INT BOOT EXT BOOT NC 1 - 2 DS1818 EXT OSC >8MHZ DSPD Design RESET, CLOCK, BOOT MODE & IRQS DSP56F8 27EVM.DSN 1.02 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 /POR /POR /IRQA /IRQB XBO OT 12.288MHZ XTA L EX TAL +3.3V +3.3V +3.3V +3.3V JG4 4.00MHz R72 10K R71 10K R70 10K 10M JG6 U12 DS1818 DNP Vcc RST GND C30 0.1uF C31 0.1uF C32 0.1uF JG5 Appendix A, Rev. 2 Freescale Semiconductor A-3 Figure A-2. Reset, Clock, Boot Mode & IRQs

A A B B C C D D E E 4 4 3 3 2 2 1 1 64Kx16-bit Program and 64Kx16-bit Data Memory SRAM ENABLE JUMPER OPTION JG3 SRAM ENABLE SRAM DISABLE 1-2 NC DSPD Design PROGRAM and DATA SRAM MEMORY DSP56F8 27EVM.DSN 1.0 3 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 D13 D15 D11 D10 D12 D14 A11 A10 A15 A14 A13 A12 /RD /WR D[0..15] A[0..15] /PS +3.3V +3.3V GS72116TP-12 102 19 37 DQ1 DQ2 DQ3 DQ4A3 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 A15 DQ13 DQ14 A14 DQ15 DQ16 A13 A12 A11 A10 UB LB OE WE CE A16 VSS VSS VDD VDD JG3 R67 10K R69 R68 56F827EVM User Manual, Rev. 2 A-4 Freescale Semiconductor Figure A-3. Program & Data SRAM Memory

A A B B C C D D E E 4 4 3 3 2 2 1 1 EEPROM Enable DSPD Design SPI Serial 1M-Bit EEPROM MEMORY DSP56F8 27EVM.DSN 1.0 4 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 /RES /WP /RES /WP EE_SO EE_SI EE_SCK /EE_CS/SS MISO MOSI SCLK +3.3V +3.3V R90 10K R91 10K JG7 AT45DB011-SC 4 6 SI SO CS VCC RESET WP GNDSCK Appendix A, Rev. 2 Freescale Semiconductor A-5 Figure A-4. SPI Serial 1M-bit Serial EEPROM Memory

A A B B C C D D E E 4 4 3 3 2 2 1 1 RS-2 32 ENABLE 1 - 2 N/CRS-232 ENABLE RS-232 DISABLE CONNECTOR CTS DSR DTR RXD TXD RTS DCD SCI RS-232 RI GND DSPD Design SCI PORT, RS-232 AND CO NNECTOR DSP56F8 27EVM.DSN 1.0 5 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 R4IN R5IN R2IN R3IN T3IN /EN T2IN T2IN T3IN /EN R3IN R4IN R5IN R2IN TXD0 RXD0 +3.3V +3.3V +3.3V R61 1K R62 1K R60 1K R59 1K R56 1K R58 1K R55 1K JG2 R57 T11 1 T12 1 T13 1 T14 1 T91 T81 T151 T10 1 MAX3245EEAI 15 8 C2+ VCC C2- FORCEON C1+ T1IN T2IN T3IN R1OUT R2OUT R3OUT R4OUT R5OUT R5IN R4IN R3IN R2IN R1IN T3OUT T2OUT T1OUT FORCEOFF C1- GND R2OUTB INVALID R88 0 Ohm R89 0 Ohm C27 C28 1.0uF C26 1.0uF C29 1.0uF 56F827EVM User Manual, Rev. 2 A-6 Freescale Semiconductor Figure A-5. SCI Port, RS-232 and Connector

A A B B C C D D E E 4 4 3 3 2 2 1 1 MF6 MF7 MF8 FS (KHZ) 000 111 48.00 32.00 24.00 19.20 16.00 12.00 9.60 8.00 SERIAL MODE 4 SELECTED MASTER, 32BITS PER FRAME Line Out Stereo Jack Line-I nput Stereo Jack Sample Select Headphone Out Stereo Jack DSPD Design SSI 16-BIT STEREO CODEC DSP56F827EVM. DSN 1.0 6 10Monday, April 09, 2001B DSP Standard Pro ducts Division Tempe, Arizona 85284 Titl e Docum ent Date : Size Design er: Sheet of Rev.Numb er (480) 413-5090 FAX: (480) 413-2510 MF 1 CODEC_FSYNC CODEC_SDO UT RING_IN CDIN /PDN TIP_IN CODEC_SC LK 12 .288MHZ LO UT RING_OUTROU T CCLK CODEC_SDIN MF 5 /CCS /CODEC_RE SET /CODEC_RE SET /CCS CDIN CCLK CODEC_SC LK CODEC_SDIN CODEC_SDO UT CODEC_FSYNC /CCS MF 5 MF 1 MF 8 MF 7 MF 6 MODE 3 MODE 2 MODE 1 /PDN MF 6 MF 7 MF 8 MODE 3 MODE 2 MODE 1 SHUTDN LOUT ROU T SHUTDN BYPASS MF7 MF8 MF6 TIP _OUT RING_PHN TIP_PH N MOD E1 MOD E2 MOD E3 SRD STD STCK STFS PD 0 PD 1 PD 2 PD 3 12. 288MHZ +5.0VA +3.3V +3 .3V +3 .3V +3.3V +5.0VA R31 5. 62K C17 0.47 uF R34 39 .2K R32 5. 62K C21 0.47 uF C10 47 0pF R33 5.6 2K 1% C1 5 0.00 22uF R35 39. 2K C14 0.33u F C12 47 0pF C16 0.00 22uF R30 5.6 2K C18 0.47 uF 0.33u F R5 3

0 Oh m

12.288M HZ OSC 5EN VCC GND OUT R4 1 R4 7 0.1u F + C7 47 uF 10VD C R8 7 10 K C1 1 1u F 25 V C1 3 1u F 25 V C25 1u F 25 V 1/ 8" 10 P5 1/ 8" 1/8 " C20 1u F 25 V C19 1u F 25 V R39 20. 0K R38 20. 0K R46 20 .0K 1% R40 20 .0K 1% C2 4 47 uF 10VD C C2 3 47 uF 10VD C LM4880 M IN_A IN_B OUT_A OUT_B VDD GNDSHUTDN BYPASS R96

0 O hm

Appendix A, Rev. 2 Freescale Semiconductor A-7 Figure A-6. SSI 16-Bit Stereo Codec

A A B B C C D D E E 4 4 3 3 2 2 1 1 Parallel JTAG Interface KEY JTAG Connector On-Board Host Target Interface Disable PORT_ VCC PORT _DE DSPD Design PARALLE L JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR DSP56F827EVM. DSN 1.0 7 10Monday, April 09, 2001B DSP Standard Pro ducts Division Tempe, Arizona 85284 Titl e Docum ent Date : Size Design er: Sheet of Rev.Numb er (480) 413-5090 FAX: (480) 413-2510 /J_RE SET P_RESET /J_T RST /J_RE SET TDO P_RESET TMS TC K TDI /J_T RST TD O PO RT_TDO PORT _TMS /PO RT_TRST PO RT_TCK PORT_ TDI PORT_CON NECT PO RT_RESET PORT_I DENT /J_T RST /J_RE SET /J_T RST /POR TDI TD O TC K TMS /RE SET /T RST /POR +3.3V +3.3V +3.3V +3 .3V +3.3V R2 1

51 O hm

1. 1K R24 5.1 K R26 47 K R2 8 47 K R15 27 0 R17 27 0 R16 27 0 R19 27 0 R18 27 0 R23 5.1 K JG 1 MC74LCX244A DW 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 VCC GND T7 1 R2 0 5.1 K DB2 5M

13 R2 2

74 AC00

56F827EVM User Manual, Rev. 2 A-8 Freescale Semiconductor Figure A-7. Parallel JTAG Host Target Interface and JTAG Connector

A A B B C C D D E E 4 4 3 3 2 2 1 1 Daughter Address/Data Connector Daughter Peripheral Port Connector A16/GND A17/GNDA18/GND A19/GNDA20 CS2/GNDCS3/GND /CS0 /CS1 GND GND GND GND GND GND GND GND GND GND DSPD Design DAUGHTER CARD EXPANSION CONNECTORS DSP56F8 27EVM.DSN 1.0 8 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 GNDGND GND GND GNDGND GND GND GND D14 A14 /RD /WR D13 D15 A13 A15 /PS /DS A10 A11 A12 A3 A4 D10 D11 D12 MISO SCLK TXD1 SRD SRFS SRCK /RESET /IRQA PB2 PB0 PB4 PB6 PD6 PD4 PD0 PD2MOSI /SS RXD0 RXD1STD STFS STCK /IRQB CLKO PB1 PB3 PB5 PB7 PD1 PD3 PD5 PD7 TXD0 TA0 TA2 TA1 TA3 PCS3 PCS2 PCS4 PCS5PCS6 PCS7 ANA0 ANA2 ANA4 ANA6 ANA1 ANA3 ANA5 ANA7 ANA8 ANA9 Appendix A, Rev. 2 Freescale Semiconductor A-9 Figure A-8. Daughter Card Expansion Connectors

A A B B C C D D E E 4 4 3 3 2 2 1 1 EXTERNAL POWER INPUT7-12VDC/AC 123 MC33269 5.0V, 3.3V & Adj REGULATOR POWER GOOD LED Vout = 1.25( 1 + (Rhigh/Rlow)) Rhigh = 243 1% for 2.5V Rlow Rhigh INPUT +5VDC + DSPD Design POW ER SUPPLIES DSP56F8 27EVM.DSN 1.0 9 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 +5.0V +5.0VA +3.3V +3.3V +2.5V +5.0V +5.0V +3.3VA V CC 0.1uF 0.1uF U10 MC33269DT-3.3 3 2 VIN VOUT VOUTGND FERRITE BEAD FERRITE BEAD FERRITE BEAD + C5 47uF 10VDC 470 C55 0.1uF U13 MC33269DT-ADJ 3 2 VIN VOUT VOUTGND R94 243 R95 243 +C57 47uF 10VDC FERRITE BEAD + C56 47uF 10VDC TB1 LED7 U14 MC33269DT-5 3 2 VIN VOUT VOUTGND+ C3 470uF 16VDC FM4001 FM4001 FM4001 FERRITE BEAD + C58 47uF 10VDC 56F827EVM User Manual, Rev. 2 A-10 Freescale Semiconductor Figure A-9. Power Supplies

A A B B C C D D E E 4 4 3 3 2 2 1 1 DSP56F827 74AC04 74AC00GS72116 DS1818 MAX3245AT45DB011 74LCX244 CS4218 OSC LM4880 TEST POINTSGROUND ANALOG GROUND TEST POINT TEST POINT TEST POINT+5.0VA +3.3V TEST POINT+2.5V DSPD Design BYP ASS CAPS DSP56F8 27EVM.DSN 1.0 10 10Monday, April 09, 2001A DS P Standard Products Division Tempe, Arizona 85284 Tit le Docu ment Date: Siz e Design er: Shee t of Rev.Numbe r (480) 413-5090 FAX: (480) 413-2510 +3.3V +3.3V +3.3V +5.0VA +5.0VA +3.3V +2.5V +3.3VA C41 0.01uF C42 0.1uF C39 0.01uF C35 0.01uF C37 1.0uF C33 0.01uF C36 0.1uF C34 0.1uF C38 0.1uF C40 1.0uF C49 0.01uF DNP C45 0.01uF C43 0.01uF C46 0.1uF C44 0.1uF C48 0.1uF C50 0.1uF C51 0.1uF C52 0.01uF C53 0.1uF C54 0.01uF C22 0.1uF TP3 1 TP4 1 TP5 1 TP 2 1TP 1

1 TP6

1 TP 7

1.0uF Appendix A, Rev. 2 Freescale Semiconductor A-11 Figure A-10. Bypass Caps

56F827EVM User Manual, Rev. 2 A-12 Freescale Semiconductor

Appendix B, Rev. 2 Freescale Semiconductor B-1 Appendix B 56F827EVM Bill of Material Qty. Description Ref. Designators Vendor Part #s Integrated Circuits

1 DSP56F827FG80 U1 Freescale, DSP56F827FG80

1 GS72116 U2 GSI, GS72116TP-12

1 MAX3245 U3 Maxim, MAX3245EEAI

1 AT45DB011 U4 Atmel, AT45DB011-SC

1 CS4218 U5 Crystal Semiconductor, CS4218-KQ

1 LM4880 U6 National Semiconductor, LM4880M

1 12.288MHZ OSC U7 Epson, SG-531P-12.288MC 1 74LCX244 U8 ON Semiconductor, MC74LCX244ADW 1 74AC00 U9 Fairchild, 74AC00SC 1 +3.3V Voltage Regulator U10 ON Semiconductor, MC33269DT-3.3 1 74AC04 U11 ON Semiconductor, MC74AC04AD 1 +2.5V Voltage Regulator U13 ON Semiconductor, MC33269DT-ADJ 1 +5.0V Voltage Regulator U14 ON Semiconductor, MC33269DT-5 Resistors 11 0 M : R1 SMEC, RC73L2A10MOHMJT 1 470 : R2 SMEC, RC73L2A470OHMJT 11 270 : R3, R6, R9, R11, R13 - R19 SMEC, RC73L2A270OHMJT 10 47K : R4, R5, R7, R8, R10, R12, R26 - R29 SMEC, RC73L2A47KOHMJT 4 5.1K : R20, R23 - R25 SMEC, RC73L2A5.1KOHMJT

56F827EVM User Manual, Rev. 2 B-2 Freescale Semiconductor Resistors (Continued) 25 1 : R21, R22 SMEC, RC73L2A51OHMJT 4 5.62K : R30 - R33 SMEC, RC73L2A5.62KOHMFT 2 39.2K : R34, R35 SMEC, RC73L2A39.2KOHMFT 19 10K : R36, R37, R42 - R45, R67, R70 - R72, R82 - R85, R87, R90 - R93 SMEC, RC73L2A10KOHMJT 4 20.0K : R38 - R40, R46 SMEC, RC73L20.0KOHMFT 12 1K : R41, R55 - R62, R68, R69, R86 SMEC, RC73L2A1KOHMJT 12 : R47 - R54, R88, R89, R96, R97 SMEC, RC73JP2A 22 4 3 :1% R94, R95 SMEC, RC73L243OHMFT Inductors 4 1.0mH FERRITE BEAD L1, L2, L3, L4 Panasonic, EXC-ELSA35V LEDs

2 Red LED LED1, LED4 Hewlett-Packard, HSMS-C650

2 Yellow LED LED2, LED5 Hewlett-Packard, HSMY-C650

3 Green LED LED3, LED6, LED7 Hewlett-Packard, HSMG-C650

2 S2B-FM401 D1, D2, D3 Vishay, DL4001DICT

1 1Amp Bridge Rectifier D4 General Semiconductor, DF02S Capacitors 14 7 0 PF, +16V DC C3 ELMA, RV-16V471MH10R 18 0.1 PF C4, C6, C9, C22, C30 - C32, C34, C36, C38, C42, C44, C46, C48, C50, C51, C53, C55 SMEC, MCCE104K2NR-T1 74 7 PF, +16V DC C5, C7, C23, C24, C56, C57, C58 ELMA, RV2-16V470M-R 2 0.33 PF C8, C14 SMEC, MCCE334K3NR-T1 2 470pF C10, C12 SMEC, MCCE471J2NO-T1 12 1.0 PF, +25V DC C11, C13, C19, C20, C25 - C29, C37, C40, C59 SMEC, MCCE105K3NR-T1 Qty. Description Ref. Designators Vendor Part #s

Appendix B, Rev. 2 Freescale Semiconductor B-3 Capacitors (Continued) 2 0.0022 PF C15, C16 SMEC, MCCE222K2NR-T1 3 0.47 PF C17, C18, C21 SMEC, MCCE474K3NR-T1 9 0.01 PF C33, C35, C39, C41, C43, C45, C49, C52, C54 SMEC, MCCE103K2NR-T1 Jumpers 41 u 2, 2mm Header JG1 - JG3, JG6 SAMTEC, TMM-102-03-S-S 23 u 1, 2mm Header JG4, JG5 SAMTEC, TMM-103-03-S-S 14 u 2, 2mm Header JG7 SAMTEC, TMM-104-03-S-D Test Points 71 u 1, Pin TP1 - TP7 Samtec, TSW-101-06-S-S Crystals 1 4.00MHz Crystal Y1 CTS, ATS04ASM-T Connectors 1 2.1mm coax Power Connector P1 Switchcraft, RAPC-722

1 DB25M Connector P2 AMPHENOL, 617-C025P-AJ121

1 DE9S Connector P3 AMPHENOL, 617-C009S-AJ120

3 1/8” Stereo Jack P4 - P6 Switchcraft, 35RAPC4BHN2 2 51-Pin HD Connector J1, J2 FCI Framatome Conn, 91930-21151 1 7 x 2 Bergstick J3 SAMTEC, TSW-107-07-S-D 1 2-Pin Terminal Block TB1 On-Shore Technology, ED500/2DS Switches

3 SPST Pushbutton S1 - S3 Panasonic, EVQ-PAD05R

1 3-Position DIP SW S4 CTS, 209-3LPST Transistors 1 2N2222A Q1 ZETEX, FMMT2222ACT Qty. Description Ref. Designators Vendor Part #s

56F827EVM User Manual, Rev. 2 B-4 Freescale Semiconductor Miscellaneous 8 2mm Shunt SH1–SH8 Samtec, 2SN-BK-T

4 Rubber Feet RF1–RF4 3M, SJ5018BLKC

Qty. Description Ref. Designators Vendor Part #s

Index, Rev. 2 Freescale Semiconductor Index - i Numerics 1.2A power supply 2-14 16-bit 2.5V/3.3V hybrid controller 2-1 16-bit stereo codec interface 2-1 1M-bit Serial EEPROM 2-1 4.00MHz crystal oscillator 2-1 64Kx16 bits of data memory 2-1 64Kx16 bits of program memory 2-1 C Codec Preface-ix D Data memory 2-3 Daughter Card Expansion interface 2-1 Debugging 2-8 Development Card 2-1 E EEPROM EEPROM Preface-ix Electrically Erasable Programmable Read Only Memory Preface-ix Evaluation Module Preface-ix EVM EVM Preface-ix External oscillator frequency input 2-1 F FSRAM 2-1, 2-3 G General Purpose Input/Output port Preface-ix GPIO 2-2 GPIO Preface-ix H Host Parallel Interface Connector 2-8 Host Target Interface 2-8 I IC IC Preface-ix Integrated Circuit Preface-ix J Joint Test Action Group Preface-ix JTAG 1-1, 2-1 connector 2-9 JTAG Preface-ix JTAG port interface 2-1 Jumper Group 1-3 JG1 1-3 JG2 1-3 JG3 1-3 JG4 1-3 JG5 1-3 JG6 1-3 JG7 1-3 L Low-profile Quad Flat Pack Preface-ix LQFP LQFP Preface-ix M MPIO MPIO Preface-ix Multi-Purpose Input/Output port Preface-ix O On-board power regulation 2-2 OnCE 1-1 OnCE(TM) OnCE Preface-ix On-Chip Emulation Preface-ix Operating Mode 2-7

DSP56F827EVM User Manual, Rev. 2 Index - ii Freescale Semiconductor P Parallel JTAG Host Target Interface 2-1 PCB PCB Preface-ix Phase Locked Loop Preface-ix PLL PLL Preface-ix Printed Circuit Board Preface-ix Program memory 2-3 R RAM RAM Preface-ix Random Access Memory Preface-ix Read-Only Memory Preface-ix Real-time debugging 2-8 ROM ROM Preface-ix RS-232 interface 2-1, 2-5 level converter 2-5 schematic diagram 2-5 RS-232 interface 2-1 S SCI SCI Preface-ix SCI-compatible peripheral 2-2 Serial Communications Interface port Preface-ix Serial Peripheral Interface port Preface-ix SPI 2-2 SPI Preface-ix SRAM external data 2-1 external program 2-1 SRAM Preface-ix SSI 2-2 SSI Preface-ix Static Random Access Memory Preface-ix Stereo 16-bit codec interface 2-1 Stereo headphone interface 2-1 Synchronous Serial Interface port Preface-ix W Wait State Preface-ix WS WS Preface-ix

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Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F827EVMUM Rev. 2 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.