56800EFM

56F801 FREESCALE | Alldatasheet

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16-bit Digital Signal Controllers freescale.com 56F801 Data Sheet Preliminary Technical Data DSP56F801 Rev. 16

56F801 Technical Data, Rev. 16 Freescale Semiconductor 3

• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communicatio ns Interface (SCI)
• Serial Peripheral Interface (SPI)
• 8 K × 16-bit words (16KB) Program Flash
• 1 K × 16-bit words (2KB) Program RAM
• 2 K × 16-bit words (4KB) Data Flash
• 1 K × 16-bit words (2KB) Data RAM
• 2 K × 16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCE TM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package 56F801 General Description 56F801 Block Diagram JTAG/ OnCE Port Digital Reg Analog Reg Low Voltage Supervisor Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Address Generation Unit Bit Manipulation Unit PLL Clock Gen or Optional Internal Relaxation Osc. 16-Bit 56800 Core PAB PDB XDB2 CGDB XAB1 XAB2 GPIOB3/XTAL GPIOB2/EXTAL INTERRUPT CONTROLS IPBB CONTROLS IPBus Bridge (IPBB) MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] COP RESET RESET IRQA Applica- tion-Specific Memory & Peripherals Interrupt Controller Program Memory 8188 x 16 Flash 1024 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 1024 x 16 SRAM COP/ Watchdog SPI or GPIO SCI0 or GPIO Quad Timer D or GPIO Quad Timer C A/D1 A/D2 ADC PWM Outputs Fault Input PWMA 16 16 VCAPC V DD VSS VDDA VSSA 6 24 5 *
• •
• • VREF *includes TCS pin which is reserved for factory use and is tied to VSS

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1.1 56F801 Features

1.1.1 Digital Signal Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Pe r Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with un ique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stac k with depth limited only by memory
• JTAG/OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution —8 K × 16 bit words of Program Flash —1 K × 16-bit words of Program RAM —2 K × 16-bit words of Data Flash —1 K × 16-bit words of Data RAM —2 K × 16-bit words of Boot Flash
• Programmable Boot Flash supports customized boot co de and field upgrades of stored code through a variety of interfaces (JTAG , SPI)

1.1.3 Peripheral Circuits for 56F801

• Pulse Width Modulator (PWM) with six PWM outputs, tw o Fault inputs, fault-tolerant design with deadtime insertion; supports both center- and edge-aligned modes
• Two 12-bit, Analog-to-Digital Conv erters (ADCs), which support two simultaneous conversions with two 4-multiplexed inputs; ADC and PWM modules can be synchronized
• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurab le four-pin port (or four additional GPIO lines)

56F801 Technical Data, Rev. 16 Freescale Semiconductor 5

• Eleven multiplexed General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) watchdog timer
• One dedicated external interrupt pin
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusi ve, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Oscillator flexibility between either an external crys tal oscillator or an on-chip relaxation oscillator for lower system cost and two additional GPIO lines

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available 1.2 56F801 Description The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost , configuration flexibility, and compact program code , the 56F801 is well-sui ted for many applications . The 56F801 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit sw itches, power supply a nd control, automotive control, engine management, noise suppression, remo te utility metering, a nd industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architectur e consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instru ction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F801 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruct ion cycle. The 56F801 also provides one external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F801 controller includes 8K wo rds (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased.

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A key application-specific feature of the 56F801 is the inclusion of a Puls e Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functi onality. Complementary operation permits programmable dead-time insertion, and separate top and bot tom output polarity control. The up- counter value is programmable to support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0% to 100% modulation) are supported. The devi ce is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a refere nce output to synchronize the Analog-to-Digital Converters. The 56F801 incorporates an 8 input, 12-bit Analog-to-D igital Converter (ADC). A full set of standard programmable peripherals is provide d that include a Serial Communicat ions Interface (SCI), a Serial Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility in the choice of either on-chip or externally supplied frequency reference for chip timing operations. Application code is used to select which source is to be used.

1.3 State of the Art Development Environment

• Processor Expert TM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environm ent is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

56F801 Technical Data, Rev. 16 Freescale Semiconductor 7

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F801. Documentation is available from local Frees cale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

1.5 Data Sheet Conventions

This data sheet uses the following conventions: Table 1-1 56F801 Chip Documentation Topic Description Order Number 56800E Family Manual Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set 56800EFM DSP56F801/803/805/807 User’s Manual Detailed description of memory, peripherals, and interfaces of the 56F801, 56F803, 56F805, and 56F807 DSP56F801-7UM 56F801 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56F801 56F801 Errata Details any chip issues that might be present 56F801E OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 1. Values for V IL, VOL, VIH, and VOH are defined by individual product specifications. PIN True Asserted V IL/VOL PIN False Deasserted V IH/VOH PIN True Asserted V IH/VOH PIN False Deasserted V IL/VOL

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Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Detailed

Description

Power (VDD or VDDA)5 Table 2-2 Ground (VSS or VSSA)6 Table 2-3 Supply Capacitors 2 Table 2-4 PLL and Clock 2 Table 2-5 Interrupt and Program Control 2 Table 2-6 Pulse Width Modulator (PWM) Port 7 Table 2-7 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins

4 Table 2-8

Serial Communications Interface (SCI) Port1 2 Table 2-9 Analog-to-Digital Converter (ADC) Port 9 Table 2-10 Quad Timer Module Port 3 Table 2-11 JTAG/On-Chip Emulation (OnCE) 6 Table 2-12

56F801 Technical Data, Rev. 16 Freescale Semiconductor 9 Figure 2-1 56F801 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. 56F801 Power Port Ground Port Power Port Ground Port PLL and Clock or GPIO SCI0 Port or GPIO VDD VSS VDDA VSSA VCAPC EXTAL (GPIOB2) XTAL (GPIOB3) TCK TMS TDI TDO TRST DE JTAG/OnCE™ Port PWMA0-5 FAULTA0 SCLK (GPIOB4) MOSI (GPIOB5) MISO (GPIOB6) SS (GPIOB7) TXD0 (GPIOB0) RXD0 (GPIOB1) ANA0-7 VREF TD0-2 (GPIOA0-2) IRQA RESET Quad Timer D or GPIO ADCA Port Other Supply Port Interrupt/ Program Control SPI Port or GPIO *includes TCS pin which is reserved for factory use and is tied to VSS

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2.2 Power and Ground Signals

2.3 Clock and Phase Locked Loop Signals

No. of Pins Signal Na me Signal Description

4 VDD Power—These pins provide power to the internal structures of the chip, and should all be

attached to VDD.

1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and

should be connected to a low noise 3.3V supply. Table 2-3 Grounds No. of Pins Signal Name Signal Description

4 VSS GND—These pins provide grounding for the internal structures of the chip, and should all

be attached to VSS. 1 VSSA Analog Ground—This pin supplies an analog ground. 1 TCS TCS —This Schmitt pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. Table 2-4 Supply Capacitors and VPP No. of Pins Signal Name Signal Type State During Reset Signal Description 2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 μFor greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, refer to Section 5.2. Table 2-5 PLL and Clock No. of Pins Signal Name Signal Type State During Reset Signal Description

1 EXTAL

External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the EXTAL pin is not needed.

Interrupt and Program Control Signals 56F801 Technical Data, Rev. 16 Freescale Semiconductor 11

2.4 Interrupt and Program Control Signals

2.5 Pulse Width Modulator (PWM) Signals

1 XTAL

Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.3. Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the XTAL pin is not needed. Table 2-6 Interrupt and Program Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

1 IRQA Input

(Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered.

1 RESET

(Schmitt) Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET , but do not assert TRST. Table 2-7 Pulse Width Modulator (PWMA) Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 6 PWMA0-5 Output Tri-stated PWMA0-5— These are six PWMA output pins.

1 FAULTA0 Input

(Schmitt) Input FAULTA0— This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Table 2-5 PLL and Clock (Continued) No. of Pins Signal Name Signal Type State During Reset Signal Description

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2.6 Serial Peripheral Interface (SPI) Signals

Table 2-8 Serial Peripheral Interface (SPI) Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

1 MISO

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. After reset, the default state is MISO.

1 MOSI

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. After reset, the default state is MOSI.

1 SCLK

SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCLK. 1 SS GPIOB7 Input Input/Output Input Input SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SS.

Serial Communications Interface (SCI) Signals 56F801 Technical Data, Rev. 16 Freescale Semiconductor 13

2.7 Serial Communications Interface (SCI) Signals

2.8 Analog-to-Digital Converter (ADC) Signals

2.9 Quad Timer Module Signals

Table 2-9 Serial Communications Interface (SCI0) Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

1 TXD0

Transmit Data (TXD0)—SCI0 transmit data output Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCI output.

1 RXD0

Receive Data (RXD0)—SCI0 receive data input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCI input. Table 2-10 Analog to Digital Converter Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

4 ANA0-3 Input Input ANA0-3—Analog inputs to ADC, channel 1

4 ANA4-7 Input Input ANA4-7—Analog inputs to ADC, channel 2

1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance. Table 2-11 Quad Timer Module Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

3 TD0-2

TD0-2—Timer D Channel 0-2 Port A GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is the quad timer input.

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2.10 JTAG/OnCE

3.1 General Characteristics

The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type State During Reset Signal Description

1 TCK Input

(Schmitt) Input, pulled low internally Test Clock Input—This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.

1 TMS Input

(Schmitt) Input, pulled high internally Test Mode Select Input—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: Always tie the TMS pin to VDD through a 2.2K resistor.

1 TDI Input

(Schmitt) Input, pulled high internally Test Data Input—This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK.

1 TRST Input

(Schmitt) Input, pulled high internally Test Reset—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. 1 DE Output Output Debug Event—DE provides a low pulse on recognized debug events.

56F801 Technical Data, Rev. 16 Freescale Semiconductor 15 The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published af ter complete characterization a nd device qualificat ions have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 3-1 Absolute Maximum Ratings Characteristic Symbol Min Max Unit Supply voltage V DD VSS – 0.3 V SS + 4.0 V All other input voltages, excluding Analog inputs V IN VSS – 0.3 V SS + 5.5V V Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V Analog inputs ANA0-7 and VREF V IN VSSA– 0.3 V DDA+ 0.3 V Analog inputs EXTAL, XTAL V IN VSSA– 0.3 V SSA+ 3.0 V Current drain per pin excluding VDD, VSS, & PWM ouputs I — 10 mA Table 3-2 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Supply voltage, digital V DD 3.0 3.3 3.6 V Supply Voltage, analog V DDA 3.0 3.3 3.6 V Voltage difference VDD to VDDA ΔVDD -0.1 - 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V ADC reference voltage1 1. VREF must be 0.3 below V DDA. VREF 2.7 – 3.3V V Ambient operating temperature T A –40 – 85 °C

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Notes: 1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction to ambient therma l resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case therma l resistance, Theta-JC (R θJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Thermal Characterization Parameter, Psi-JT ( ΨJT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady state customer environments. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Section 5.1 from more details on thermal design considerations. 7. TJ = Junction Temperature TA = Ambient Temperature Table 3-3 Thermal Characteristics6 Characteristic Comments Symbol Value Unit Notes 48-pin LQFP Junction to ambient Natural convection RθJA 50.6 °C/W 2 Junction to ambient (@1m/sec) R θJMA 47.4 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) R θJMA (2s2p) 39.1 °C/W 1,2 Junction to ambient (@1m/sec) Four layer board (2s2p) R θJMA 37.9 °C/W 1,2 Junction to case R θJC 17.3 °C/W 3 Junction to center of case ΨJT 1.2 °C/W 4, 5 I/O pin power dissipation P I/O User Determined W Power dissipation P D P D = (IDD x VDD + P I/O)W Junction to center of case P DMAX (TJ - TA) /RθJA W7

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3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) V IHC 2.25 — 2.75 V Input low voltage (XTAL/EXTAL) V ILC 0— 0 . 5 V Input high voltage [GPIOB(2:3)]1 VIH[GPIOB(2:3)] 2.0 — 3.6 V Input low voltage [GPIOB(2:3)]1 VIL[GPIOB(2:3)] -0.3 — 0.8 V Input high voltage (Schmitt trigger inputs)2 VIHS 2.2 — 5.5 V Input low voltage (Schmitt trigger inputs)2 VILS -0.3 — 0.8 V Input high voltage (all other digital inputs) V IH 2.0 — 5.5 V Input low voltage (all other digital inputs) V IL -0.3 — 0.8 V Input current high (pullup/pulldown resistors disabled, VIN=VDD)I IH -1 — 1 μA Input current low (pullup/pulldown resistors disabled, VIN=VSS)I IL -1 — 1 μA Input current high (with pullup resistor, VIN=VDD)I IHPU -1 — 1 μA Input current low (with pullup resistor, VIN=VSS)I ILPU -210 — -50 μA Input current high (with pulldown resistor, VIN=VDD)I IHPD 20 — 180 μA Input current low (with pulldown resistor, VIN=VSS)I ILPD -1 — 1 μA Nominal pullup or pulldown resistor value R PU, RPD 30 K Ω Output tri-state current low I OZL -10 — 10 μA Output tri-state current high I OZH -10 — 10 μA Input current high (analog inputs, VIN=VDDA)3 IIHA -15 — 15 μA Input current low (analog inputs, VIN=VSSA)3 IILA -15 — 15 μA Output High Voltage (at IOH)V OH VDD – 0.7 — — V Output Low Voltage (at IOL)V OL —— 0 . 4 V Output source current I OH 4— — m A Output sink current I OL 4— — m A PWM pin output source current4 IOHP 10 — — mA PWM pin output sink current5 IOLP 16 — — mA Input capacitance C IN —8 — p F Output capacitance C OUT —1 2 — p F

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Run7 (80MHz operation) —1 2 0 1 3 0 m A Run7 (60MHz operation) —1 0 2 1 1 1 m A Wait8 —9 6 1 0 2 m A Stop —6 2 7 0 m A Low Voltage Interrupt, external power supply9 VEIO 2.4 2.7 3.0 V Low Voltage Interrupt, internal power supply10 VEIC 2.0 2.2 2.4 V Power on Reset11 VPOR —1 . 7 2 . 0 V 1. Since the GPIOB[2:3] signals are shared with the XTAL/E XTAL function, these inputs are not 5.5 volt tolerant. 2. Schmitt Trigger inputs are: FAULTA0, IRQA , RESET, TCS, TCK, TMS, TDI, and TRST. 3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 4. PWM pin output source current measured with 50% duty cycle. 5. PWM pin output sink current measured with 50% duty cycle. 6. I DDT = IDD + IDDA (Total supply current for VDD + VDDA) 7. Run (operating) I DD measured using 8MHz clock source . All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 8. Wait I DD measured using external square wave clock source (f osc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. C L = 20pF on EXTAL; all ports configured as input s; EXTAL capacitance linearly affects wait I DD; measured with PLL enabled. 9. This low voltage interrupt monitors the V DDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). 11. Power –on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. T he internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates. Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit

56F801 Technical Data, Rev. 16 Freescale Semiconductor 19 Figure 3-1 Maximum Run IDD vs. Frequency (see Note 7. in Table 3-15)

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown. Figure 3-2 Input Signal Measurement References Figure 3-3 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.
• Tri-stated, when a bus or signal is placed in a high impedance state.
• Data Valid state, when a signal level has reached V OL or VOH.
• Data Invalid state, when a signal level is in transition between VOL and VOH. 120 160 10 20 30 40 50 60 70 80 Freq. (MHz) IDD (mA) IDD Digital IDD Analog IDD Total VIH VILFall Time Input Signal Note: The midpoint is VIL + (VIH – VIL)/2. Midpoint1 Low High 90% 50% 10% Rise Time

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3.4 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table Mode XE1 1. X address enable, all rows are disabled when XE = 0 YE2 2. Y address enable, YMUX is disabled when YE = 0 SE3 3. Sense amplifier enable OE4 4. Output enable, tri-state Flash data out bus when OE = 0 PROG5 5. Defines program cycle ERASE6 6. Defines erase cycle MAS17 7. Defines mass erase cyc le, erase whole block NVSTR8 8. Defines non-volatile store cycle Standby L L L L L L L L R e a d H HHH L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H Table 3-6 IFREN Truth Table Mode IFREN = 1 IFREN = 0 Read Read information block Read main memory block Word program Program information block Program main memory block Page erase Erase information block Erase main memory block Mass erase Erase both block E rase main memory block Data Invalid State Data1 Data2 Valid Data Tri-stated Data3 Valid Data2 Data3 Data1 Valid Data Active Data Active

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22 Freescale Semiconductor

Figure 3-4 Flash Program Cycle Figure 3-5 Flash Erase Cycle XADR YADR YE DIN PROG NVSTR Tnvs Tpgs Tadh Tprog Tads Tpgh Tnvh Trcv Thv IFREN XE XADR YE=SE=OE=MAS1=0 ERASE NVSTR Tnvs Tnvh TrcvTerase IFREN XE

56F801 Technical Data, Rev. 16 Freescale Semiconductor 23 Figure 3-6 Flash Mass Erase Cycle

3.5 External Clock Operation

The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator. To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external these methods of clocking. Whichever type of clock derivati on is used provides a reference signal to a phase-locked loop (PLL) within the 56F801. In turn, the PLL generates a master reference frequency that determines the speed at which chip operations occur. Application code can be set to cha nge the frequency source between the relaxation oscillator and crystal oscillator or external source, and power down the relaxation oscillator if desired. Selection of which clock is used is determined by setting the PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal relaxation oscillator is selected, and this is the default value of the bit when power is first applied.

3.5.1 Crystal Oscillator

The internal oscillator is also designed to interfac e with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-10. Figure 3-7 shows a recommended crystal oscillator circuit. Follow the crys tal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry XADR YE=SE=OE=0 ERASE NVSTR Tnvs Tnvh1 TrcvTme MAS1 IFREN XE

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is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors should be used. The 56F80x components internally are modeled as a pa rallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. Figure 3-7 External Crystal Oscillator Circuit

3.5.2 Ceramic Resonator

It is also possible to drive the in ternal oscillator with a ceramic re sonator, assuming the overall system design can tolerate the re duced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is shown. Refer to supplier’s recomm endations when selecting a ce ramic resonator and associated components. The resonator and com ponents should be mounted as clos e as possible to the EXTAL and XTAL pins. The internal 56F80x os cillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-7 no external load capacitors should be used. Figure 3-8 Connecting a Ceramic Resonator Note: Freescale recommends only two term inal ceramic resonators vs . three terminal resonators (which contain an internal bypass capacitor to ground). CL = CL1 * CL2 CL1 + CL2 + Cs = + 3 = 6 + 3 = 9pF 12 * 12 12 + 12 Recommended External Crystal Parameters: Rz = 1 to 3 MΩ fc = 8MHz (optimized for 8MHz) EXTAL XTAL Rz fc Recommended Ceramic Resonator Parameters: R z = 1 to 3 MΩ fc = 8MHz (optimized for 8MHz) EXTAL XTAL Rz fc

56F801 Technical Data, Rev. 16 Freescale Semiconductor 25

3.5.3 External Clock Source

The recommended method of connecting an external clock is given in Figure 3-9. The external clock source is connected to XTAL and the EXTAL pin is grounded. Figure 3-9 Connecting an External Clock Signal Figure 3-10 External Clock Timing

3.5.4 Use of On-Chip Re laxation Oscillator

An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default, and the PRECS bit in the PLLCR word is set to 0 (Section 3.5). If an external oscillator is connected, the relaxation oscillator can be desele cted instead by setting the PRECS bit in the PLLCR to 1. When this occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a changeover between internal and exte rnal oscillators is required at startup, internal device circuits Table 3-8 External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 1. See Figure 3-9 for details on using the recommended connection of an external clock driver. fosc 0— 802 2. May not exceed 60MHz for the DSP56F801FA60 device. 3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. 4. Parameters listed are guaranteed by design. MHz Clock Pulse Width3, 4 tPW 6.25 — — ns 56F801 XTAL EXTAL External Clock VSS External Clock VIH VIL Note: The midpoint is VIL + (VIH – VIL)/2. 90% 50% 10% 90% 50% 10% tPWtPW

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26 Freescale Semiconductor

compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within ±0.25% of 8MHz by trimming an inte rnal capacitor. Bits 0-7 of the IOSCTL (internal oscillator contro l) word allow the user to set in an additional offset (trim) to this preset value to increase or decrea se capacitance. The default value of this trim is 128 units, making the power-up default capacito r size 432 units. Each unit added or deleted changes the output frequency by about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved. Table 3-9 Relaxation Oscillator Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit Frequency Accuracy1 1. Over full temperature range. Δf—+ 2+ 5% Frequency Drift over Temp Δf/Δt—+ 0.1 — %/oC Frequency Drift over Supply Δf/ΔV— 0 . 1 — % / V Trim Accuracy ΔfT —+ 0.25 — %

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3.5.5 Phase Locked Loop Timing

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 1. An externally supplied reference cl ock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f out/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. Will not exceed 60MHz for the DSP56F801FA60 device. 4. This is the minimum time required after the PLL setup is changed to ensure reliable operation. fosc 48 1 0 M H z PLL output frequency2 fout/2 40 — 803 MHz PLL stabilization time4 0o to +85oC tplls —1 0—m s PLL stabilization time4 -40o to 0oC tplls — 100 200 ms

Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F801 Technical Data, Rev. 16 Freescale Semiconductor 29

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF 1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns. Characteristic Symbol Min Max Unit See RESET Assertion to Address, Data and Control Signals High Impedance tRAZ —2 1 n s Figure 3-13 Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset
• When recovering from Stop state tRA 275,000T 128T ns ns Figure 3-13 RESET De-assertion to First External Address Output tRDA 33T 34T ns Figure 3-13 Edge-sensitive Interrupt Request Width t IRW 1.5T — ns Figure 3-14 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM 15T — ns Figure 3-15 IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine t IG 16T — ns Figure 3-15 IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. tIRI 13T — ns Figure 3-16 IRQA Width Assertion to Recover from Stop State4 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. tIW 2T — ns Figure 3-17 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tIF 275,000T 12T ns ns Figure 3-17 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 t IRQ 275,000T 12T ns ns Figure 3-18 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tII 275,000T 12T ns ns Figure 3-18

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Figure 3-13 Asynchronous Reset Timing Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive) Figure 3-15 External Level-Sensitive Interrupt Timing First FetchA0–A15, D0–D15 PS, DS, RD, WR RESET First Fetch tRAZ tRA tRDA IRQA, IRQB tIRW A0–A15, PS, DS, RD, WR IRQA, IRQB First Interrupt Instruction Execution a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA, IRQB b) General Purpose I/O tIDM tIG

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3.7 Serial Peripheral Interface (SPI) Timing

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave t C ns ns Figures 3-19, 3-20, 3-21, 3-22 Enable lead time Master Slave t ELD ns ns Figure 3-22 Enable lag time Master Slave t ELG 100 ns ns Figure 3-22 Clock (SCK) high time Master Slave t CH 17.6 12.5 ns ns Figures 3-19, 3-20, 3-21, 3-22 Clock (SCK) low time Master Slave t CL 24.1 ns ns Figures 3-19, 3-20, 3-21, 3-22 Data setup time required for inputs Master Slave t DS ns ns Figures 3-19, 3-20, 3-21, 3-22 Data hold time required for inputs Master Slave t DH ns ns Figures 3-19, 3-20, 3-21, 3-22 Access time (time to data active from high-impedance state) Slave t A 4.8 15 ns Figure 3-22 Disable time (hold time to high-impedance state) Slave tD 3.7 15.2 ns Figure 3-22 Data Valid for outputs Master Slave (after enable edge) tDV 4.5 20.4 ns ns Figures 3-19, 3-20, 3-21, 3-22 Data invalid Master Slave tDI ns ns Figures 3-19, 3-20, 3-21, 3-22 Rise time Master Slave tR 11.5 10.0 ns ns Figures 3-19, 3-20, 3-21, 3-22 Fall time Master Slave tF 9.7 9.0 ns ns Figures 3-19, 3-20, 3-21, 3-22

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Figure 3-21 SPI Slave Timing (CPHA = 0) Figure 3-22 SPI Slave Timing (CPHA = 1) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 MSB in Bits 14–1 LSB in SS (Input) Slave LSB out tC tCL tF tELG tR tDS tELD tCH tCL tA tCH tR tF tD tDItDV tDH tDI SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 MSB in Bits 14–1 LSB in SS (Input) Slave LSB out tDI tD tR tDV tDH tF tDS tELG tF tR tCH tDV tA tELD tCL tCL tCH tC

56F801 Technical Data, Rev. 16 Freescale Semiconductor 35

3.8 Quad Timer Timing

3.9 Serial Communication Interface (SCI) Timing

Table 3-13 Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit Timer input period P IN 4T+6 — ns Timer input high/low period P INHL 2T+3 — ns Timer output period P OUT 2T — ns Timer output high/low period P OUTHL 1T — ns Table 3-14 SCI Timing4 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit Baud Rate1 1. f MAX is the frequency of operation of the system clock in MHz. BR — (fMAX*2.5)/(80) Mbps RXD2 Pulse Width 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. TXDPW 0.965/BR 1.04/BR ns Timer Inputs Timer Outputs POUTHLPOUTHLPOUT PIN PINHL PINHL

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Figure 3-24 RXD Pulse Width Figure 3-25 TXD Pulse Width

3.10 Analog-to-Digital Converter (ADC) Characteristics

Table 3-15 ADC Characteristics Characteristic Symbol Min Typ Max Unit ADC input voltages V ADCIN 01 — VREF 2 V Resolution R ES 12 — 12 Bits Integral Non-Linearity3 INL — +/- 4 +/- 5 LSB4 Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB4 Monotonicity GUARANTEED ADC internal clock5 fADIC 0.5 — 5 MHz Conversion range R AD VSSA —V DDA V Conversion time t ADC —6 — tAIC cycles6 Sample time t ADS —1 — tAIC cycles6 Input capacitance C ADI —5 — pF6 Gain Error (transfer gain)5 EGAIN 1.00 1.10 1.15 — Offset Voltage5 VOFFSET +10 +230 +325 mV RXD SCI receive data pin (Input) RXDPW TXD SCI receive data pin (Input) TXDPW

Analog-to-Digital Converter (ADC) Characteristics 56F801 Technical Data, Rev. 16 Freescale Semiconductor 37 1. Parasitic capacitance due to package, pin to pi n, and pin to package base coupling. (1.8pf) 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf) 3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) 4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) Figure 3-26 Equivalent Analog Input Circuit Total Harmonic Distortion5 THD 55 60 — dB Signal-to-Noise plus Distortion5 SINAD 54 56 — dB Effective Number of Bits5 ENOB 8.5 9.5 — bit Spurious Free Dynamic Range5 SFDR 60 65 — dB Bandwidth BW — 100 — KHz ADC Quiescent Current (both ADCs) I ADC —5 0 — m A VREF Quiescent Current (both ADCs) I VREF —1 2 1 6 . 5 m A 1. For optimum ADC performance, keep the minimum V ADCIN value > 250mV. Inputs less than 250mV volts may convert to a digital output code of 0 or cause erroneous conversions. 2. V REF must be equal to or less than VDDA - 0.3V and must be greater than 2.7V. 3. Measured in 10-90% range. 4. LSB = Least Significant Bit. 5. Guaranteed by characterization. 6. tAIC = 1/fADIC Table 3-15 ADC Characteristics (Continued) Characteristic Symbol Min Typ Max Unit 1 2 ADC analog input

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3.11 JTAG Timing

Figure 3-27 Test Clock Input Timing Diagram Table 3-16 JTAG Timing 1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. Characteristic Symbol Min Max Unit TCK frequency of operation2 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. fOP DC 10 MHz TCK cycle time t CY 100 — ns TCK clock pulse width t PW 50 — ns TMS, TDI data setup time t DS 0.4 — ns TMS, TDI data hold time t DH 1.2 — ns TCK low to TDO data valid t DV — 26.6 ns TCK low to TDO tri-state t TS — 23.5 ns TRST assertion time t TRST 50 — ns DE assertion time t DE 8T — ns TCK (Input) VM VIL VM = VIL + (VIH – VIL)/2 VM VIH tPW tPW tCY

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4.1 Package and Pin-Out Information 56F801

This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801. Figure 4-1 Top View, 56F801 48-pin LQFP Package PIN 1 ORIENTATION MARKTDO TD1 TD2 /SS MISO MOSI SCLK TXDO VSS VDD RXD0 DE TCS TCK TMS IREQA TDI VCAPC2 VSS VDD EXTAL XTAL TDO TRST ANA4 ANA3 VREF ANA2 ANA1 ANA0 FAULTA0 V SS VDD VSSA VDDA RESET PWMA5 PWMA4 PWMA3 PWMA2 PWMA1 V SS VDD VCAPC1 PWMA0 ANA7 ANA6 ANA5 PIN 13 PIN 37 PIN 25

Package and Pin-Out Information 56F801 56F801 Technical Data, Rev. 16 Freescale Semiconductor 41 Table 4-1 56F801 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 TD0 13 TCS 25 RESET 37 ANA5

2T D 1 1 4 T C K 2 6 V DDA 38 ANA6 3T D 2 1 5 T M S 2 7 V SSA 39 ANA7 4S S 16 IREQA 28 V DD 40 PWMA0 5M I S O 1 7 T D I 2 9 V SS 41 VCAPC1

6 MOSI 18 VCAPC2 30 FAULTA0 42 V DD

7S C L K 1 9 V SS 31 ANA0 43 V SS 8T X D 0 2 0V DD 32 ANA1 44 PWMA1 9V SS 21 EXTAL 33 ANA2 45 PWMA2

10 V DD 22 XTAL 34 VREF 46 PWMA3

11 RXD0 23 TDO 35 ANA3 47 PWMA4

12 DE 24 TRST 36 ANA4 48 PWMA5

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42 Freescale Semiconductor

Figure 4-2 48-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. A Z0.200 AB T-U Z0.200 AC T-U B 13 24 3748 S V P AE AE T, U, Z DETAIL Y DETAIL Y BASE METAL N J F D T-UM0.080 Z AC SECTION AE-AE AD G 0.080 AC TOP & BOTTOM L ° W K AA EC H 0.250 R DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. CASE 932-03 ISSUE F T U Z AB AC GAUGE PLANE DIM A MIN MAX

7.000 BSC

A1 3.500 BSC B 7.000 BSC B1 3.500 BSC C 1.400 1.600 D 0.170 0.270 E 1.350 1.450 F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 M 12 REF N 0.090 0.160 P 0.250 BSC L 0 7 R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC V1 4.500 BSC W 0.200 REF AA 1.000 REF

Thermal Design Considerations 56F801 Technical Data, Rev. 16 Freescale Semiconductor 43 Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting ar rangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area su rrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the PCB, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages:

• Measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. TJ TA PD RθJA×()+= RθJA RθJC RθCA+=

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44 Freescale Semiconductor

• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (T J – TT)/PD where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top ce nter of the package case. The th ermocouple should be positioned so that the thermocouple junction re sts on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. From this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each V DD pin on the controller, and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances.
• Ensure that capacitor leads and associated prin ted circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

Electrical Design Considerations 56F801 Technical Data, Rev. 16 Freescale Semiconductor 45

• Bypass the V DD and VSS layers of the PCB with approximately 100 μF, preferably with a high-grade capacitor such as a tantalum capacitor.
• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits.
• Take special care to minimize noise levels on the VREF, V DDA and VSSA pins.
• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low.
• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming.

56F801 Technical Data, Rev. 16

46 Freescale Semiconductor

Part 6 Ordering Information Table 6-1 lists the pertinent information needed to pl ace an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. *This package is RoHS compliant. Table 6-1 56F801 Ordering Information Part Supply Voltage Package Type Pin Count Ambient Frequency (MHz) Order Number 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80E* 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60E*

Electrical Design Considerations 56F801 Technical Data, Rev. 16 Freescale Semiconductor 47

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