ICS557-06_12 IDT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Features
- Packaged in 20-pin TSSOP
- Pb (lead) free packaging
- Operating voltage of 3.3 V
- Low power consumption
- Input differential clock of up to 200 MHz
- Jitter 60 ps (cycle-to-cycle)
- Output-to-output skew of 50 ps
- Available in industrial temperature range (-40 to +85°C) For PCIe Gen2/3 applications, see the 5V41067A Block Diagram VDD CLKA CLKA Rr (IREF) CLKB CLKB CLKC CLKC CLKD CLKD SEL GND IN1 IN1 IN2 IN2 MUX 2 to 1 OE PD
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 2 ICS557-06 REV M 070512 Pin Assignment Select Table Pin Descriptions IN2 GND OE CLKC CLKD GND CLKD IREF 3IN1 IN1 CLKB
18 CLKB
20 CLKA
20-pin (173 mil) TSSOP SEL Input Pair selected 0I N2/ IN2 1I N1/ IN1 Pin Pin Name Pin Type Pin Description 1 SEL Input SEL=1 selects IN1/IN1 . SEL =0 selects IN2/ IN2. Internal pull-up resistor. 2 VDDIN Power Connect to +3.3 V. Supply voltage for Input clocks. 3 IN1 Input HCSL true input signal 1. 4 IN1 Input HCSL complimentary input signal 1. 5 PD Input Powers down the chip and tri-states outputs when low. Internal pull-up 6 IN2 Input HCSL true input signal 2. 7 IN2 Input HCSL complimentary input signal 2.
8 OE Input Provides fast output on, tri-states output (High = enable outputs; Low =
disable). Internal pull-up resistor outputs. 9 GND Power Connect to ground.
10 Rr(IREF) Output Precision resistor attached to this pin is connected to the internal current
11 CLKD Output Differential Comp limentary output clock D. 12 CLKD Output Differential True output clock D. 13 CLKC Output Differential Comp limentary output clock C. 14 CLKC Output Differential True output clock C. 15 VDDOUT Power Connect to +3.3 V. Supply Voltage for Output Clocks. 16 GND Power Connect to ground. 17 CLKB Output Differential Complimentary output clock B. 18 CLKB Output Differential True output clock B. 19 CLKA Output Differential Complimentary output clock A. 20 CLKA Output Differential True output clock A.
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 3 ICS557-06 REV M 070512
Application Information
As with any high-performance mixed-signal IC, the ICS557-06 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-06. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 µF should be connected between VDD and GND pairs (2,9 and 15,16) as close to the device as possible. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF . Load Resistors RL Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-06 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-06 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 4 ICS557-06 REV M 070512 Output Structures General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-06.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. RR 475 6*IREF =2.3 mA IREF See Output Termination Sections - Pages 3 ~ 5Ω
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 5 ICS557-06 REV M 070512 PCI-Express Layout Guidelines PCI-Express Device Routing Typical PCI-Express (HCSL) Waveform Common Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch R S 33 ohm R T 49.9 ohm Differential Routing on a Single PCB Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express Connector Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch RS RS RT RT PCI-Express Load or Connector L1 L2 L3’ L1’ L2’ L4’ ICS557-06 Output Clock 0.175 V 0.52 V 0.175 V 0.52 V tOR tOF500 ps 500 ps 700 mV
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 6 ICS557-06 REV M 070512 LVDS Compatible Layout Guidelines LVDS Device Routing Typical LVDS Waveform Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signal s HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 1150 mV 1250 mV tOR tOF500 ps 500 ps 1325 mV 1000 mV 1150 mV 1250 mV
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 7 ICS557-06 REV M 070512 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70 ° C Ambient Operating Temperature (industrial) -40 to +85 ° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) Parameter Symbol Conditions Min. Typ. Max. Units Supply Voltage V 3.135 3.465 Input High Voltage1 VIH OE, SEL, PD 2.0 VDD +0.3 V Input Low Voltage1 VIL OE, SEL, PD VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD -5 5 µA Operating Supply Current I DD 50Ω, 2pF 55 mA IDDOE OE =Low 20 mA IDDPD No load, PD =Low 400 µA Input Capacitance C IN Input pin capacitance 7 pF Output Capacitance C OUT Output pin capacitance 6 pF Pin Inductance L PIN 5n H Output Resistance R OUT CLK outputs 3.0 k Ω Pull-up Resistor R PUP SEL, OE, PD 110 k Ω
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 8 ICS557-06 REV M 070512 Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C 1 Test setup is RL=50 ohms with 2 pF , Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its PD = low. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 200 MHz Output Frequency HCSL termination 200 MHz LVDS termination 100 Input High Voltage1,2 VIH HCSL 660 700 850 mV Input Low Voltage1,2 VIL HCSL -150 0 mV Differential Input Voltages (VID) LVDS 250 350 450 mV Input Offset Voltage (V IS) LVDS 1.125 1.25 1.375 V Output High Voltage1,2 VOH HCSL 660 700 850 mV Output Low Voltage1,2 VOL HCSL -150 0 27 mV Crossing Point Voltage1,2 Absolute 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 60 ps Rise Time1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V 175 344 700 ps Rise/Fall Time Variation1,2 125 ps Skew between Outputs Measured at crossing point 50 ps Duty Cycle1,3 45 55 % Output Enable Time5 All outputs 10 us Output Disable Time5 All outputs 10 us Input to Output Delay Input differential clock to output differential clock delay measured at mid point of input levels to mid pint of output levels 4.5 ns
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 9 ICS557-06 REV M 070512 Thermal Characteristics Marking Diagrams (ICS557G-06LF) (ICS557GI-06LF) Notes: 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” denotes Pb free package. 4. “I” denotes industrial temperature. 5. Bottom marking: (origin). Origin = country of origin if not USA. Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 93 ° C/W θJA 1 m/s air flow 78 ° C/W θJA 3 m/s air flow 65 ° C/W Thermal Resistance Junction to Case θJC 20 ° C/W 20 11 YYWW 557G06LF IC S 1 10 20 11 YYWW 557GI06LF IC S
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 10 ICS557-06 REV M 070512 Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 557G-06LF See Page 9 Tubes 20-pin TSSOP 0 to +70 ° C 557G-06LFT Tape and Reel 20-pin TSSOP 0 to +70 ° C 557GI-06LF Tubes 20-pin TSSOP -40 to +85 ° C 557GI-06LFT Tape and Reel 20-pin TSSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A1 .20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 D 6.40 6.60 0.252 0.260 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0.45 0.75 0.018 0.030 a0 ° 8° 0° 8°
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 11 ICS557-06 REV M 070512
Revision History
Rev. Date Originator Description of Change M 07/05/12 — Changed the typical value of the "Input to Output Delay" parameter in the "AC Electrical Characteristics - CLKOUTA/CLKOUTB" table from 3ns to 4.5ns.
© 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without no tice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All ot her brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: w w w.IDT.com ICS557-06