ICS557-05A RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 13

Technical content

Features

  • Packaged in 20-pin TSSOP
  • RoHS 5 (green) or RoHS 6 (green and lead free) complaint package
  • Supports PCI-Express applications
  • Four differential spread spectrum clock outputs
  • Spread spectrum for EMI reduction
  • Uses external 25 MHz clock or crystal input
  • Power down pin turns off chip
  • OE control tri-states outputs
  • Spread and frequency selection via external pins
  • Spread Bypass option available
  • Industrial temperature range available
  • For PCIe Gen2 applications, see the 5V41066
  • For PCIe Gen3 applications, see the 5V41236 Block Diagram Spread Spectrum/ Output clock selection CLKOUTA CLKOUTA Rr(IREF) PLL Clock Synthesis GND VDD Clock Oscillator SEL[2:0] Spread Spectrum Circuitry CLKOUTB CLKOUTD

25 MHz

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 2 ICS557-05A REV O 112111 Pin Assignment Spread Spectrum Selection Table GNDODA OE CLKC CLKD GNDXD CLKD IREF 3S1 S2 CLKB

18 CLKB

20 CLKA

20-pin (173 mil) TSSOP S2 S1 S0 Spread% Spread Type Output Frequency 0 0 0 -0.5 Down 100 0 0 1 -1.0 Down 100 0 1 0 -1.5 Down 100 0 1 1 No Spread Not Applicable 100 1 0 0 -0.5 Down 200 1 0 1 -1.0 Down 200 1 1 0 -1.5 Down 200 1 1 1 No Spread Not Applicable 200

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 3 ICS557-05A REV O 112111 Pin Descriptions Pin Pin Name Pin Type Pin Description 1 VDDXD Power Connect to +3.3 V digital supply. 2 S0 Input Spread spectrum select pin #0. See table above. Internal pull-up resistor. 3 S1 Input Spread spectrum select pin #1. See table above Internal pull-up resistor. 4 S2 Input Spread spectrum select pin #2. See table above. Internal pull-up resistor. 5 X1 Input Crystal connection. Connect to a fundamental mode crystal or clock input. 6 X2 Output Crystal connection. Connect to a fundamental mode crystal or leave open. 7 PD Input Powers down all PLL ’s and tri-states outputs when low. Internal pull-up resistor. 8 OE Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. 9 GND Power Connect to digital ground. 10 IREF Output Precision resistor attached to this pi n is connected to the internal current reference. 11 CLKD Output Selectable 100/200 MHz spread spectrum differential Compliment output clock D. 12 CLKD Output Selectable 100/200 MHz spread spectrum differential True output clock D. 13 CLKC Output Selectable 100/200 MHz spread spectrum differential Compliment output clock C. 14 CLKC Output Selectable 100/200 MHz spread spectrum differential True output clock C. 15 VDDODA Power Connect to +3.3 V analog supply. 16 GND Power Connect to analog ground. 17 CLKB Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B. 18 CLKB Output Selectable 100/200 MHz spread spectrum differential True output clock B. 19 CLKA Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A. 20 CLKA Output Selectable 100/200 MHz spread spectrum differential True output clock A.

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 4 ICS557-05A REV O 112111

Application Information

As with any high-performance mixed-signal IC, the ICS557-05A must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. An op timum layout is one with all components on the sam e side of the board, minimizing vias through other signal la yers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed a way from the ICS557-05A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 μF should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (C L-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF . [(16-12)x2]=8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF . Load Resistors RL Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-05A are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-05A can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 5 ICS557-05A REV O 112111 Output Structures General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-05A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. RR 475 6*IREF =2.3 mA IREF See Output Termination Sections - Pages 3 ~ 5Ω

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 6 ICS557-05A REV O 112111 PCI-Express Layout Guidelines PCI-Express Device Routing Typical PCI-Express (HCSL) Waveform Common Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch RS 33 ohm RT 49.9 ohm Differential Routing on a Single PCB Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express Connector Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch RS RS RT RT PCI-Express Load or Connector L1 L2 L3’ L1’ L2’ L4’ ICS557-05A Output Clock 0.175 V 0.52 V 0.175 V 0.52 V tOR tOF500 ps 500 ps 700 mV

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 7 ICS557-05A REV O 112111 LVDS Compatible Layout Guidelines LVDS Device Routing Typical LVDS Waveform Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signals HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 1150 mV 1250 mV tOR tOF500 ps 500 ps 1325 mV 1000 mV 1150 mV 1250 mV

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 8 ICS557-05A REV O 112111 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) Parameter Symbo l Conditions Min. Typ. Max. Units Supply Voltage V 3.135 3.465 Input High Voltage1 VIH 2.0 VDD +0.3 V Input Low Voltage1 VIL VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD -5 5 μA Operating Supply Current I DD 50Ω, 2 pF load @100 MHz 105 mA IDDOE OE =Low 40 mA IDDPD No load, PD =Low 500 μA Input Capacitance CIN Input pin capacitance 7 pF Output Capacitance C OUT Output pin capacitance 6 pF Pin Inductance LPIN 5n H Output Resistance Rout CLK outputs 3.0 k Ω Pull-up Resistance R PUP OE, SEL, PD pins 110 kΩ

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 9 ICS557-05A REV O 112111 Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C 1 Test setup is RL=50 ohms with 2 pF , Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency HCSL termination 200 MHz Output High Voltage 1,2 VOH 660 700 850 mV Output Low Voltage1,2 VOL -150 0 27 mV Crossing Point Voltage1,2 Absolute 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 80 ps Modulation Frequency Spread spectrum 30 31.5 33 kHz Rise Time 1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V 175 344 700 ps Skew between outputs At crossing point Voltage 50 ps Duty Cycle 1,3 45 55 % Output Enable Time5 All outputs 10 us Output Disable Time5 All outputs 10 us Power-up Time t STABLE From power-up VDD=3.3 V 3.0 ms Spread Change Time t SPREAD Settling period after spread change 3.0 ms

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 10 ICS557-05A REV O 112111 Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C 1 Test setup is RL=50 ohms with 2 pF , Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency LVDS termination 100 MHz Differential Output Voltage V OD 247 454 mV Offset Voltage V OS 1.125 1.375 V ∆VOD |Change to VOD| 50 mV ∆VOS |Change to VOS| 50 mV Jitter, Cycle-to-Cycle1,3 80 ps Modulation Frequency Spread spectrum 30 31.5 33 kHz Slew Rate, Rise 1,3 tSLR Measured from ±150 mV from crossing point voltage

14 V / n s

Slew Rate, Fall1,3 tSLF Measured from ±150 mV from crossing point voltage Skew between outputs At crossing point Voltage 50 ps Duty Cycle1,3 45 55 % Output Enable Time5 All outputs 10 µs Output Disable Time5 All outputs 10 µs Power-up Time t STABLE From power-up VDD=3.3 V 3 ms Spread Change Time t SPREAD Settling period after spread change 3 ms Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 93 ° C/W θJA 1 m/s air flow 78 ° C/W θJA 3 m/s air flow 65 ° C/W Thermal Resistance Junction to Case θJC 20 ° C/W

QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE 11 ICS557-05A REV O 112111 Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153

Ordering Information

“LF” suffix to the part number are the Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 557G-05ALF 557G-05ALF Tubes 20-pin TSSOP 0 to +70 ° C 557G-05ALFT 557G-05ALF Tape and Reel 20-pin TSSOP 0 to +70 ° C 557GI-05ALF 557GI-05AL Tubes 20-pin TSSOP -40 to +85 ° C 557GI-05ALFT 557GI-05AL Tape and Reel 20-pin TSSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L Millimeters Inches* Symbol Min Max Min Max A1 .20 0 .047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 D 6.40 6.60 0.252 0.260 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0.45 0.75 0.018 0.030 a0 ° 8° 0° 8°

© 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG

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