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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Packaged in 16-pin TSSOP
  • RoHS 5 (green) or RoHS 6 (green and lead free) compliant packaging
  • Supports HCSL or LVDS output levels
  • Operating voltage of 3.3 V
  • Input frequency of 25 MHz
  • Jitter 60 ps (cycle-to-cycle)
  • Spread Spectrum capability
  • Industrial and commercial temperature ranges
  • For PCIe Gen2 applications, see the 5V41065
  • For PCIe Gen3 applications, see the 5V41235 Block Diagram Phase Lock Loop Clock Buffer/ Crystal Oscillator VDD GND X1/ICLK

25 MHz

SS1:SS0 S1:S0 CLK0 CLK0 Rr(IREF) CLK1 CLK1 OE Optional tuning crystal capacitors

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 2 ICS557-03 REV U 112111 Pin Assignment Output Select Table 1 (MHz) Spread Selection Table 2 Pin Descriptions CLK0 CLK0 GNDODA VDDXD OE SS0 X1/ICLK SS1 CLK1 VDDODA 16-pin (173 mil) TSSOP GNDXD IREF CLK1 S1 S0 CLK(1:0), CLK(1:0) 00 2 5 M 0 1 100M 1 0 125M 1 1 200M SS1 SS0 Spread%

00 N o S p r e a d

0 1 Down -0.5 1 0 Down -0.75

11 N o S p r e a d

1 S0 Input Select pin 0. See Table1. Internal pull-up resistor. 2 S1 Input Select pin 1. See Table 1. Internal pull-up resistor. 3 SS0 Input Spread Select pin 0. See Table 2. Internal pull-up resistor. 4 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 5 X2 Output Crystal connection. Leave unconnected for clock input. 6 OE Input Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor. 7 GNDXD Power Connect to ground. 8 SS1 Input Spread Select pin 1. See Table 2. Internal pull-up resistor.

9 IREF Output Precision resistor attached to this pin is connected to the internal current

reference. 10 CLK1 Output HCSL complimentary clock output 1. 11 CLK1 Output HCSL true clock output 1. 12 VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 13 GNDODA Power Connect to ground. 14 CLK0 Output HCSL complimentary clock output 0. 15 CLK0 Output HCSL true clock output 0. 16 VDDXD Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 3 ICS557-03 REV U 112111 Applications Information External Components A minimum number of external components are required for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01 μF should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. Crystal A 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-03 to meet PCI Express specifications. Crystal Capacitors Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. C L= Crystal’s load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF . (16-8)*2=16. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50Ω, then RR = 475Ω (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF . Output Termination The PCI-Express differential clock outputs of the ICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. Output Structures General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. RR 475 6*IREF =2.3 mA IREF See Output Termination Sections - Pages 3 ~ 5Ω

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 4 ICS557-03 REV U 112111 PCI-Express Layout Guidelines PCI-Express Device Routing Typical PCI-Express (HCSL) Waveform Common Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch RS 33 ohm RT 49.9 ohm Differential Routing on a Single PCB Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express Connector Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch RS RS RT RT PCI-Express Load or Connector L1 L2 L3’ L1’ L2’ L4’ ICS557-03 Output Clock 0.175 V 0.525 V 0.175 V 0.525 V tOR tOF500 ps 500 ps 700 mV

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 5 ICS557-03 REV U 112111 LVDS Compatible Layout Guidelines LVDS Device Routing Typical LVDS Waveform Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signals HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 1150 mV 1250 mV tOR tOF500 ps 500 ps 1325 mV 1000 mV 1150 mV 1250 mV

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 6 ICS557-03 REV U 112111 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. Item Rating Supply Voltage, VDDXD, VDDODA 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70 ° C Ambient Operating Temperature (industrial) -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C ESD Protection (Input) 2000 V min. (HBM) Parameter Symbo l Conditions Min. Typ. Max. Units Supply Voltage V 2.97 3.3 3.63 V Input High Voltage1 VIH S0, S1, OE, ICLK, SS0, SS1 2.0 VDD +0.3 V Input Low Voltage1 VIL S0, S1, OE, ICLK, SS0, SS1 VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD -5 5 μA Operating Supply Current I DD 50Ω, 2 pF 78 mA IDDOE OE =Low 44 mA Input Capacitance C IN Input pin capacitance 7 pF Output Capacitance C OUT Output pin capacitance 6 pF Pin Inductance L PIN 5n H Output Resistance R OUT CLK outputs 3.0 k Ω Pull-up Resistor R PU S0, S1, OE, SS0, SS1 100 k Ω

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 7 ICS557-03 REV U 112111 Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85° C 1 Test setup is RL=50 ohms with 2 pF , Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency HCSL termination 200 MHz Output High Voltage 1,2 VOH 660 700 850 mV Output Low Voltage1,2 VOL -150 0 27 mV Crossing Point Voltage1,2 Absolute 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 80 ps Modulation Frequency Spread spectrum 30 31.5 33 kHz Rise Time 1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V 175 344 700 ps Skew between outputs At crossing point Voltage 50 ps Duty Cycle 1,3 45 55 % Output Enable Time5 All outputs 12 us Output Disable Time5 All outputs 12 us Power-up Time t STABLE From power-up VDD=3.3 V 3.0 3.5 ms Spread Change Time t SPREAD Settling period after spread change 3.0 3.5 ms

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 8 ICS557-03 REV U 112111 Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85° C 1 Test setup is RL=50 ohms with 2 pF , Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. Electrical Characteristics - Differential Phase Jitter Note 1: Guaranteed by design and characterization, not 100% tested in production. Note 2: See http://www.pcisig.com for complete specs. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency LVDS termination 100 MHz Differential Output Voltage V OD 247 454 mV Offset Voltage V OS 1.125 1.375 V ∆VOD |Change to VOD| 50 mV ∆VOS |Change to VOS| 50 mV Jitter, Cycle-to-Cycle1,3 80 ps Modulation Frequency Spread spectrum 30 31.5 33 kHz Slew Rate, Rise 1,3 tSLR Measured from ±150 mV from crossing point voltage

14 V / n s

Slew Rate, Fall1,3 tSLF Measured from ±150 mV from crossing point voltage Skew between outputs At crossing point Voltage 50 ps Duty Cycle1,3 45 55 % Output Enable Time5 All outputs 12 µs Output Disable Time5 All outputs 12 µs Power-up Time t STABLE From power-up VDD=3.3 V 3 3.5 ms Spread Change Time t SPREAD Settling period after spread change 3 3.5 ms Parameter Symbol Conditions Min Typ Max Units Notes Jitter, Phase t jphasePLL PCIe Gen 1 - - 86 ps (p-p) 1, 2

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 9 ICS557-03 REV U 112111 Thermal Characteristics Marking Diagram (ICS557G-03LF) Marking Diagram (ICS557GI-03LF) Notes: 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” designates Pb (lead) free package. 4. “I” designates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin of not USA. Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 78 ° C/W θJA 1 m/s air flow 70 ° C/W θJA 3 m/s air flow 68 ° C/W Thermal Resistance Junction to Case θJC 37 ° C/W 16 9 557G03LF YYWW 1 8 16 9 557GI03L YYWW

IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 10 ICS557-03 REV U 112111 Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 557G-03LF See Page 8 Tubes 16-pin TSSOP 0 to +70 ° C 557G-03LFT Tape and Reel 16-pin TSSOP 0 to +70 ° C 557GI-03LF See Page 8 Tubes 16-pin TSSOP -40 to +85 ° C 557GI-03LFT Tape and Reel 16-pin TSSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L Millimeters Inches* Symbol Min Max Min Max A -- 1.20 -- 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 4.90 5.1 0.193 0.201 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0.45 0.75 0.018 0.030 a0 ° 8° 0° 8°

© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS557-03