ICS554-01A RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

  • Input frequency up to 200 MHz
  • Advanced CMOS process
  • Outputs are skew matched to within 50 ps
  • Packaged in 16-pin TSSOP , Pb-free
  • One PECL input to 4 PECL output clock drivers
  • Operating Voltages of 3.3 V or 5 V
  • Industrial temperature range
  • Functional equivalent to ICS554-01
  • Simplified passive termination network compared to ICS554-01 Block Diagram IN IN VDD VSS

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 2 ICS554-01A REV D 051310 Pin Assignment Pin Descriptions NC VDD VDD IN GND GND IN NC 16-pin 173 mil (0.65mm) TSSOP Number Name Type Pin Description 1 NC — No Connect. 2 VDD Power Connect to +3.3 V or 5 V. Must be same as pin 15. 3Q 0 Output Clock Output Q0. 4 Q0 Output Clock Output Q0. 5 Q1 Output Clock Output Q1. 6Q 1 Output Clock Output Q1. 7 GND Power Connect to Ground. 8 IN Input PECL Clock Input. 9I N Input Complementary PECL Clock Input.

10 GND Power Connect to Ground

Output Clock Output Q2. 12 Q2 Output Clock Output Q2. 13 Q3 Output Clock Output Q3. 14 Q3 Output Clock Output Q3. 15 VDD Power Connect to +3.3 V or 5 V. Must be same as pin 2. 16 NC — No Connect.

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 3 ICS554-01A REV D 051310 External Components The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and GND on pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should be placed as close to the device as possible. To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on the others) will cause at least 15ps of skew. Termination for PECL or LVPECL Outputs The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs. Therefore, termination resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 ohm transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. The figures below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist, but it is recommended that board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. PECL or LVPECL Output Termination LVPECL Output Termination Z0 = 50 ohms FOUT FINZ0 = 50 ohms 50 ohms 50 ohms C1 RTT RTT = Z 0(VOH + VOL / VCC -2) -2 C1 = 0.1µF to 0.01µF Z0 = 50 ohms FOUT FINZ0 = 50 ohms 3.3 V 5 2 3 2 5 2Z0 3 2 Z0

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 4 ICS554-01A REV D 051310 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS554-01A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 – +85 ° C Power Supply Voltage (measured in respect to GND) +3.15 +5.25 V

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 5 ICS554-01A REV D 051310 VDD=3.3 V ±5% Ambient temperature -40 to +85 ° C Note 1: VOH and VOL can be set by the external resistor values on the PECL outputs. note 2: IDD includes the current through the external resistors which can be modified. VDD = 3.3 V ±5, Ambient Temperature -40 to +85 ° C Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 5.25 V Peak to Peak Input Voltage IN 0.3 1.0 V Input Common Mode Range IN VDD=3.3 V VDD-2 VDD-0.6 Input Common Mode Range IN VDD=5 V VDD-3.7 VDD-0.6 Output High Voltage V OH Note 1 VDD-1.2 V Output Low Voltage V OL Note 1 VDD - 2.0 V Operating Supply Current IDD No Load, 135 MHz 80 mA Short Circuit Current, 3.3 V I OS ±50 mA Short Circuit Current, 5 V I OS ±60 mA Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Propagation Delay VDD = 3.3 V 2 ns VDD = 5 V 2 ns Output to Output Skew Crosspoint of pair 0 50 ps Duty Cycle Crosspoint of pair 45 50 55 %

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 6 ICS554-01A REV D 051310 Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb free packaging, RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 554G-01AILF 554G1AIL Tubes 16-pin TSSOP -40 to +85 ° C 554G-01AILFT Tape and Reel 16-pin TSSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE A AA e - C - b aaa C c L Millimeters Inches Symbol Min Max Min Max A- - 1 . 2 0 - - 0 . 0 4 7 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 4.90 5.1 0.193 0.201 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0.45 0.75 0.018 0.030 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER

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