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Document overview

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Technical content

Features

  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and small 8-pin DFN package, Pb-free
  • Input/Output clock frequency up to 200 MHz
  • Ideal for networking clocks
  • Operating Voltages: 1.8V to 3.3V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C) Block Diagram ICLK Output Enable

LOW SKEW 1 TO 4 CLOCK BUFFER 2 REVISION A 03/18/15 553S DATASHEET Pin Assignments Pin Descriptions External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33  series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 553S is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. Pin Number Pin Name Pin Type Pin Description 1 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 GND Power Connect to ground. 5 ICLK Input Clock input. 6 Q2 Output Clock Output 2. 7 Q3 Output Clock Output 3. 8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. VDD GND ICLK OE 8-pin SOIC VDD GND ICLK OE 8-pin DFN

REVISION A 03/18/15 3 LOW SKEW 1 TO 4 CLOCK BUFFER 553S DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 553S. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 3.465V Output Enable and All Outputs -0.5 V to VDD+0.5 V ICLK 3.465V Ambient Operating Temperature (extended) -40 to +105 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Parameter Min. Typ. Max. Units Ambient Operating Temperature (extended) -40 +105 C Power Supply Voltage (measured in respect to GND) +1.71 +3.465 V

LOW SKEW 1 TO 4 CLOCK BUFFER 4 REVISION A 03/18/15 553S DATASHEET (VDD = 1.8V, 2.5V, 3.3V) VDD=1.8V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise Notes: 1. Nominal switch ing threshold is VDD/2 VDD=2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise VDD=3.3 V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 1.71 1.89 V Input High Voltage, ICLK V IH Note 1 0.7xVDD VDD V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -10mA 1.3 V Output Low Voltage V OL IOL = 10mA 0.35 V Operating Supply Current IDD No load, 135MHz 15 mA Nominal Output Impedance Z O 17  Input Capacitance C IN ICLK, OE pin 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.375 2.625 V Input High Voltage, ICLK V IH Note 1 0.7xVDD VDD V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -16 mA 1.8 V Output Low Voltage V OL IOL = 16 mA 0.5 V Operating Supply Current IDD No load, 135 MHz 18 mA Nominal Output Impedance Z O 17  Input Capacitance C IN ICLK, OE pin 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.45 V Input High Voltage, ICLK V IH Note 1 0.7xVDD VDD V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -25 mA 2.2 V Output Low Voltage V OL IOL = 25 mA 0.7 V Operating Supply Current IDD No load, 135 MHz 22 mA Nominal Output Impedance Z O 17  Input Capacitance C IN ICLK, OE pin 5 pF

REVISION A 03/18/15 5 LOW SKEW 1 TO 4 CLOCK BUFFER 553S DATASHEET (VDD = 1.8V, 2.5V, 3.3V) VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise Notes: 1. With rail to rail input clock 2. Between any 2 outputs with equal loading. 3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.36 to 1.44 V, CL=5 pF 0.6 1.0 ns Output Fall Time t OF 1.44 to 0.36 V, CL=5 pF 0.6 1.0 ns Propagation Delay Note 1 2.5 3 3.5 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps Output to Output Skew Note 2 Rising edges at VDD/2 50 65 ps Device to Device Skew Rising edges at VDD/2 200 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5 pF 3 cycles Output Disable Time t DIS CL < 5 pF 3 cycles Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.5 to 2.0 V, CL=5 pF 0.6 1.0 ns Output Fall Time t OF 2.0 to 0.5 V, CL=5 pF 0.6 1.0 ns Propagation Delay Note 1 3 3.5 4 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps Output to Output Skew Note 2 Rising edges at VDD/2 40 65 ps Device to Device Skew Rising edges at VDD/2 200 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5 pF 3 cycles Output Disable Time t DIS CL < 5 pF 3 cycles Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.66 to 2.64 V, CL=5 pF 0.6 1.0 ns Output Fall Time t OF 2.64 to 0.66 V, CL=5 pF 0.6 1.0 ns Propagation Delay Note 1 2.5 3 3.5 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps Output to Output Skew Note 2 Rising edges at VDD/2 25 65 ps Device to Device Skew Rising edges at VDD/2 200 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5 pF 3 cycles Output Disable Time t DIS CL < 5 pF 3 cycles

REVISION A 03/18/15 7 LOW SKEW 1 TO 4 CLOCK BUFFER 553S DATASHEET Thermal Characteristics (8SOIC) Marking Diagrams Notes: 1. “” is the lot number. 2. “YYWW” or “YW” are the last digits of the year and week that the part was assembled. 3 “G” denotes RoHS compliant package. 4. “$” denotes mark code. 5. “I” denotes extended temperature range device. Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W 553S YW 8-pin DFN IDT 553S DCGI YYWW$ 8-pin SOIC

LOW SKEW 1 TO 4 CLOCK BUFFER 8 REVISION A 03/18/15 553S DATASHEET Package Outline and Package Dimensions (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)

REVISION A 03/18/15 9 LOW SKEW 1 TO 4 CLOCK BUFFER 553S DATASHEET Package Outline and Package Dimensions, cont. (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)

LOW SKEW 1 TO 4 CLOCK BUFFER 10 REVISION A 03/18/15 553S DATASHEET Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)

Ordering Information

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant. Part / Order Number Marking Shippi ng Packaging Package Temperature 553SDCGI see page 7 Tubes 8-pin SOIC -40 to +105 C 553SDCGI8 Tape and Reel 8-pin SOIC -40 to +105 C 553SCMGI Cut Tape 8-pin DFN -40 to +105 C 553SCMGI8 Tape and Reel 8-pin DFN -40 to +105 C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 a0  8 0 8

REVISION A 03/18/15 11 LOW SKEW 1 TO 4 CLOCK BUFFER 553S DATASHEET

Revision History

Rev. Date Originator Description of Change A 03/18/15 B. Chandhoke Initial release.

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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