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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Features
- Low additive phase jitter RMS: 50fs
- Extremely low skew outputs (50ps)
- Low cost clock buffer
- Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
- Input/Output clock frequency up to 200 MHz
- Non-inverting output clock
- Ideal for networking clocks
- Operating Voltages: 1.8V to 3.3V
- Output Enable mode tri-states outputs
- Advanced, low power CMOS process
- Extended temperature range (-40°C to +105°C) Block Diagram ICLK Output Enable
LOW SKEW 1 TO 4 CLOCK BUFFER 2 REVISION A 03/18/15 551S DATASHEET Pin Assignment Pin Descriptions External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. ICLK VDD GND OE
8 Pin (150 mil) SOIC
1 ICLK Input Clock input. Internal pull-up resistor. 2 Q1 Output Clock output 1. 3 Q2 Output Clock output 2. 4 Q3 Output Clock output 3. 5 Q4 Output Clock output 4. 6 GND Power Connect to ground. 7 VDD Power Connect +1.8V, +2.5V or +3.3V. 8 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor.
REVISION A 03/18/15 3 LOW SKEW 1 TO 4 CLOCK BUFFER 551S DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 551S. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 3.465V All Inputs and Outputs -0.5 V to 3.465V Ambient Operating Temperature, Extended -40 to +105 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Parameter Min. Typ. Max. Units Ambient Operating Temperature, extended -40 – +105 C Power Supply Voltage (measured in respect to GND) +1.71 +3.465 V
LOW SKEW 1 TO 4 CLOCK BUFFER 4 REVISION A 03/18/15 551S DATASHEET VDD=1.8 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise Notes: 1. Nominal switching threshold is VDD/2. VDD=2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise Notes: 1. Nominal switching threshold is VDD/2. VDD=3.3 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise Notes: 1. Nominal switching threshold is VDD/2. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 1.71 1.89 V Input High Voltage, ICLK V IH Note 1 0.7xVDD 1.89 V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -10 mA 1.3 V Output Low Voltage V OL IOL = 10 mA 0.35 V Operating Supply Current IDD No load, 135 MHz 13 mA Nominal Output Impedance Z O 17 Input Capacitance C IN OE pin 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.375 2.625 V Input High Voltage, ICLK V IH Note 1 0.7xVDD 2.625 V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -16 mA 1.8 V Output Low Voltage V OL IOL = 16 mA 0.5 V Operating Supply Current IDD No load, 135 MHz 18 mA Nominal Output Impedance Z O 17 Input Capacitance C IN OE pin 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.465 V Input High Voltage, ICLK V IH Note 1 0.7xVDD 3.465 V Input Low Voltage, ICLK V IL Note 1 0.3xVDD V Input High Voltage, OE V IH 0.7xVDD VDD V Input Low Voltage, OE V IL 0.3xVDD V Output High Voltage V OH IOH = -25 mA 2.2 V Output Low Voltage V OL IOL = 25 mA 0.7 V Operating Supply Current IDD No load, 135 MHz 22 mA Nominal Output Impedance Z O 17 Input Capacitance C IN OE pin 5 pF
REVISION A 03/18/15 5 LOW SKEW 1 TO 4 CLOCK BUFFER 551S DATASHEET VDD=1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise VDD=2.5V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise VDD=3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise Notes: 1. With rail to rail input clock. 2. Between any 2 outputs with equal loading. 3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. 4. With external series resistor of 33 positioned close to each output pin. Parameter Symbol Conditions Min. Typ. Max. Units Output Frequency 5pF load, Note 4 200 MHz Output Clock Rise Time t OR 0.36 to 1.44 V 0.6 1.0 ns Output Clock Fall Time t OF 1.44 to 0.36V 0.6 1.0 ns Propagation Delay 135 MHz, Note 1 1.5 2 4 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.03 0.05 ps Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5pF 3 cycles Output Disable Time t DIS CL < 5pF 3 cycles Parameter Symbol Conditions Min. Typ. Max. Units Output Frequency 5pF load, Note 4 200 MHz Output Clock Rise Time t OR 0.5 to 2.0V 0.6 1.0 ns Output Clock Fall Time t OF 2.0 to 0.5V 0.6 1.0 ns Propagation Delay 135 MHz, Note 1 1.8 2.5 4.5 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.035 0.05 ps Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5pF 3 cycles Output Disable Time t DIS CL < 5pF 3 cycles Parameter Symbol Conditions Min. Typ. Max. Units Output Frequency 5pF load, Note 4 200 MHz Output Clock Rise Time t OR 0.66 to 2.64V 0.6 1.0 ns Output Clock Fall Time t OF 2.64 to 0.66V 0.6 1.0 ns Propagation Delay 135 MHz, Note 1 1.5 2 4 ns Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.037 0.05 ps Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Output Enable Time t EN CL < 5pF 3 cycles Output Disable Time t DIS CL < 5pF 3 cycles
REVISION A 03/18/15 7 LOW SKEW 1 TO 4 CLOCK BUFFER 551S DATASHEET Thermal Characteristics (8SOIC) Marking Diagrams Notes: 1. “” is the lot number. 2. “YYWW” or “YW” are the last digits of the year and week that the part was assembled. 3 “G” denotes RoHS compliant package. 4. “$” denotes the mark code. 5. “I” denotes extended temperature range device. Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W 551S YW 8-pin DFN IDT 551S DCGI YYWW$ 8-pin SOIC
LOW SKEW 1 TO 4 CLOCK BUFFER 8 REVISION A 03/18/15 551S DATASHEET Package Outline and Package Dimensions (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)
REVISION A 03/18/15 9 LOW SKEW 1 TO 4 CLOCK BUFFER 551S DATASHEET Package Outline and Package Dimensions, cont. (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)
LOW SKEW 1 TO 4 CLOCK BUFFER 10 REVISION A 03/18/15 551S DATASHEET Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Ordering Information
“G” suffix to the part number denotes Pb-Free configuration, RoHS compliant. Part / Order Number Marking Shippi ng Packaging Package Temperature 551SDCGI see page 7 Tubes 8-pin SOIC -40 to +105 C 551SDCGI8 Tape and Reel 8-pin SOIC -40 to +105 C 551SCMGI Cut Tape 8-pin DFN -40 to +105 C 551SCMGI8 Tape and Reel 8-pin DFN -40 to +105 C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 a0 8 0 8
REVISION A 03/18/15 11 LOW SKEW 1 TO 4 CLOCK BUFFER 551S DATASHEET
Revision History
Rev. Date Originator Description of Change A 03/18/15 B. Chandhoke Initial release.
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters
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