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The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si550 supports any frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-b ased VCXO is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram Available with any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz 3rd generation DSPLL® with superior jitter performance (0.5 ps) 3x better temperature stability than SAW-based oscillators Excellent PSRR performance Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant SONET/SDH xDSL 10 GbE LAN/WAN Low-jitter clock generation Optical modules Clock and data recovery Fixed Frequency XO Any-Frequency 10 MHz–1.4 GHz DSPLL ® Clock Synthesis ADC VDD Vc OE GND CLK– CLK+ Ordering Information: See page 10. Pin Assignments: See page 9. (Top View) Si5602 VC GND OE VDD CLK+ CLK– Si550 REVISION D
- Electrical Specifications
Table 1. Recommended Operating Conditions
- Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details.
- OE pin includes a 17 k resistor to VDD.
Table 2. VC Control Voltage Input
4 LVC BSL –5 ±1 +5 %
- Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- KV variation is ±10% of typical values.
- BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
Table 3. CLK± Output Frequency Characteristics
- See Section 3. "Ordering Information" on page 10 for further details.
- Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
- Nominal output frequency set by VCNOM =V DD/2.
- Selectable parameter specified by part number.
- Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
- Rterm = 100 (differential).
Table 5. CLK± Output Phase Jitter
- Refer to AN255, AN256, and AN266 for further information.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
- Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 5. CLK± Output Phase Jitter (Continued)
- Refer to AN255, AN256, and AN266 for further information.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
- Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 6. CLK± Output Period Jitter *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
- Refer to AN255, AN256, and AN266 for further information.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
- Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 7. CLK± Output Phase Noise (Typical)
155.52 MHz
491.52 MHz
622.08 MHz
10 MHz
100 MHz
Table 8. Environmental Compliance The Si550 meets the following qualification test requirements. Table 9. Thermal Characteristics
Table 10. Absolute Maximum Ratings1
- Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
extended periods may affect device reliability.
- The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
Table 11. Si550 Pin Descriptions
1 VC Analog Input Control Voltage
2 OE* Input
3 GND Ground Electrical and Case Ground
4 CLK+ Output Oscillator Output
5 CLK–
6 VDD Power Power Supply Voltage
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option. Figure 1. Part Number Convention
550 VCXO
550 X X XXXMXXX D G R
- For best jitter and phase noise performance, always choose the smallest Kv that meets
world PLL designs. See AN255 and AN266 for more information.
- APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
- Nominal Pull range (±) = 0.5 x V
- Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
- Minimum APR values noted above include worst case values for all parameters.
- Combination not available.
is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. resolution, a six digit code will be assigned for the specific frequency.
Rev. 1.1 13 6. Top Marking 6.1. Si550 Top Marking 6.2. Top Marking Explanation Line Position Description 1 1–10 “SiLabs”+ Part Family Number, 550 (First 3 characters in part number) 2 1–10 Si550: Option1+Option2+Freq(6007)+Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant
14 Rev. 1.1 DOCUMENT CHANGE LIST Revision 0.6 to Revision 1.0 Updated Table 4 on page 3. Updated 2.5 V/3.3 V and 1.8 V CML output level specifications. Updated Table 5 on page 4. Removed the words “Differential Modes: LVPECL/LVDS/CML” in the footnote referring to AN256. Added footnotes clarifying max offset frequency test conditions. Added CMOS phase jitter specs. Updated Table 10 on page 8. Separated 1.8 V, 2.5 V/3.3 V supply voltage specifications. Updated and clarified Table 8 on page 7 Added “Moisture Sensitivity Level” and “Contact Pads” rows. Updated 6. "Top Marking" on page 13 to reflect specific marking information (previously, figure was generic). Updated 4. "Package Outline and Suggested Pad Layout" on page 11. Added cyrstal impedance pin in Figure 2 on page 11 and Table 12 on page 11. Reordered spec tables and back matter to conform to data sheet quality conventions. Revision 1.0 to Revision 1.1 Added Table 9, “Thermal Characteristics,” on page 7.
Rev. 1.1 15 CONTACT INFORMATION Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.