54S134 FAIRCHILD | Alldatasheet
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, CONNECTION DIAGRAM { PINOUT A Vsas/rasisa 0/072 © 12-INPUT NAND GATE G fis] vec (With 3-State Outputs) ie re g CE ig 2 ig Ce alle -E ORDERING CODE: See Section 9 u (a z cw] = Lf our TYPE TRUTH TABLE a | Plastic re [ ourpurs ] Flatpak Any In LOW Lo ofH INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions H = HIGH Voltage Level LZ Low Voltage Level 54/748 (UL) X= Immaterial PINS Nianoue 2= High Impedance Inputs 1.25/1.25 Outputs 50/12.5 DC AND AC CHARACTERISTICS: See Section 3° SYMBOL PARAMETER 54/748 Ea CONDITIONS |_xm | 24 [tow =-20mA | Voc = Min ven 24 V Pion==85maAT]_ n= 08 Outputs HIGH 13 Veo = lec Power Supply [Outputs LOW 16 Vin=50V,VE=0V_| Max Current 25 Vin=5.0V, VE=5.0V tPuH Propagation Delay 20 60 ’ ten Data to Output 2.0 75 Figs. 3-3, 3-4 tezH ’ 19.5 tezi. ee Figs. 98, S11. S12 te | Output Disable Time |] | Figs. 3-3, 3-11, 012 tPLZ “DC limits apply over operating temperature range: AC limits apply at Ta = +25°C and Voc = +50 V. 4-173