54LVC32A

SN54LVC32A TI | Alldatasheet

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SN74LVC32A . . . RGY PACKAGE (TOP VIEW) 1 14 7 8 3Y V GND CC GND V CC SN54LVC32A . . . J OR W PACKAGE SN74LVC32A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 NC NC NC NC NC V GND NC SN54LVC32A . . . FK PACKAGE (TOP VIEW) CC NC - No internal connection DESCRIPTION/ORDERING INFORMATION The 'LVC32A devices perform the Boolean function Y A B or Y A • B in positive logic. SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 Typical V OHV (Output V OH Undershoot) V at V CC 3.3 T A C Operate From 1.65 V to 3.6 V Latch-Up Performance Exceeds 250 mA Per Specified From C to JESD C to 125 and C to 125 C ESD Protection Exceeds JESD Inputs Accept Voltages to 5.5 V 2000-V Human-Body Model (A114-A) Max t pd of 3.8 ns at 3.3 V 200-V Machine Model (A115-A) Typical V OLP (Output Ground Bounce) <0.8 V at V CC 3.3 T A C 1000-V Charged-Device Model (C101) The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V V CC operation, and the SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V V CC operation. ORDERING INFORMATION ORDERABLE TOP-SIDE T A PACKAGE (1) PART NUMBER MARKING C to C QFN RGY Reel of 1000 SN74LVC32ARGYR LC32A Tube of SN74LVC32AD SOIC D Reel of 2500 SN74LVC32ADR LVC32A Reel of 250 SN74LVC32ADT SOP NS Reel of 2000 SN74LVC32ANSR LVC32A C to 125 C SSOP DB Reel of 2000 SN74LVC32ADBR LC32A Tube of SN74LVC32APW TSSOP PW Reel of 2000 SN74LVC32APWR LC32A Reel of 250 SN74LVC32APWT CDIP J Tube of SNJ54LVC32AJ SNJ54LVC32AJ C to 125 C CFP W Tube of 150 SNJ54LVC32AW SNJ54LVC32AW LCCC FK Tube of SNJ54LVC32AFK SNJ54LVC32AFK (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 1993 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) A B Y Absolute Maximum Ratings (1) SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. FUNCTION TABLE (EACH GATE) INPUTS OUTPUT Y A B H X H X H H L L L LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 6.5 V V I Input voltage range (2) 0.5 6.5 V V O Output voltage range (2) (3) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through V CC or GND 100 mA D package (4) DB package (4) θ JA Package thermal impedance NS package (4) C/W PW package (4) 113 RGY package (5) T stg Storage temperature range 150 C P tot Power dissipation T A C to 125 C (6) (7) 500 mW (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of V CC is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) The package thermal impedance is calculated in accordance with JESD 51-5. (6) For the D package: above the value of P tot derates linearly with mW/K. (7) For the DB, DGV, NS, and PW packages: above the value of P tot derates linearly with 5.5 mW/K.

www.ti.com Recommended Operating Conditions (1) Recommended Operating Conditions (1) SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 SN54LVC32A TO 125 C UNIT MIN MAX Operating 3.6 V CC Supply voltage V Data retention only 1.5 V IH High-level input voltage V CC 2.7 V to 3.6 V V V IL Low-level input voltage V CC 2.7 V to 3.6 V 0.8 V V I Input voltage 5.5 V V O Output voltage V CC V V CC 2.7 V I OH High-level output current mA V CC V V CC 2.7 V I OL Low-level output current mA V CC V Δ Δ v Input transition rise or fall rate ns/V (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. SN74LVC32A T A C TO C TO 125 C UNIT MIN MAX MIN MAX MIN MAX Operating 1.65 3.6 1.65 3.6 1.65 3.6 V CC Supply voltage V Data retention only 1.5 1.5 1.5 V CC 1.65 V to 1.95 V 0.65 V CC 0.65 V CC 0.65 V CC High-level input V IH V CC 2.3 V to 2.7 V 1.7 1.7 1.7 V voltage V CC 2.7 V to 3.6 V V CC 1.65 V to 1.95 V 0.35 V CC 0.35 V CC 0.35 V CC Low-level input V IL V CC 2.3 V to 2.7 V 0.7 0.7 0.7 V voltage V CC 2.7 V to 3.6 V 0.8 0.8 0.8 V I Input voltage 5.5 5.5 5.5 V V O Output voltage V CC V CC V CC V V CC 1.65 V V CC 2.3 V High-level output I OH mA current V CC 2.7 V V CC V V CC 1.65 V V CC 2.3 V Low-level output I OL mA current V CC 2.7 V V CC V Δ Δ v Input transition rise or fall rate ns/V (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com Electrical Characteristics Electrical Characteristics Switching Characteristics SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 over operating free-air temperature range (unless otherwise noted) SN54LVC32A PARAMETER TEST CONDITIONS V CC TO 125 C UNIT MIN MAX I OH 100 µ A 2.7 V to 3.6 V V CC 0.2 2.7 V 2.2 V OH I OH mA V V 2.4 I OH mA V 2.2 I OL 100 µ A 2.7 V to 3.6 V 0.2 V OL I OL mA 2.7 V 0.4 V I OL mA V 0.55 I I V I 5.5 V or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A Δ I CC One input at V CC 0.6 Other inputs at V CC or GND 2.7 V to 3.6 V 500 µ A over operating free-air temperature range (unless otherwise noted) SN74LVC32A PARAMETER TEST CONDITIONS V CC T A C TO C TO 125 C UNIT MIN TYP MAX MIN MAX MIN MAX I OH 100 µ A 1.65 V to 3.6 V V CC 0.2 V CC 0.2 V CC 0.3 I OH mA 1.65 V 1.29 1.2 1.05 I OH mA 2.3 V 1.9 1.7 1.55 V OH V 2.7 V 2.2 2.2 2.05 I OH mA V 2.4 2.4 2.25 I OH mA V 2.3 2.2 I OL 100 µ A 1.65 V to 3.6 V 0.1 0.2 0.3 I OL mA 1.65 V 0.24 0.45 0.6 V OL I OL mA 2.3 V 0.3 0.7 0.85 V I OL mA 2.7 V 0.4 0.4 0.6 I OL mA V 0.55 0.55 0.8 I I V I 5.5 V or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A One input at V CC 0.6 Δ I CC Other inputs at V CC or 2.7 V to 3.6 V 500 500 5000 µ A GND C i V I V CC or GND 3.3 V pF over operating free-air temperature range (unless otherwise noted) (see Figure SN54LVC32A FROM TO PARAMETER V CC TO 125 C UNIT (INPUT) (OUTPUT) MIN MAX 2.7 V 4.4 t pd A or B Y ns 3.3 V 0.3 V 3.8

www.ti.com Switching Characteristics Operating Characteristics SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 over operating free-air temperature range (unless otherwise noted) (see Figure SN74LVC32A FROM TO PARAMETER V CC T A C TO C TO 125 C UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX 1.8 V 0.15 V 4.2 8.2 8.7 10.2 2.5 V 0.2 V 2.6 4.9 5.4 6.9 t pd A or B Y ns 2.7 V 4.2 4.4 5.5 3.3 V 0.3 V 2.5 3.6 3.8 t sk(o) 3.3 V 0.3 V 1.5 ns T A C TEST PARAMETER V CC TYP UNIT CONDITIONS 1.8 V 7.5 C pd Power dissipation capacitance per gate f MHz 2.5 V 10.6 pF 3.3 V 12.5

www.ti.com PARAMETER MEASUREMENT INFORMATION VM thtsu From Output Under Test CL (see Note A) LOAD CIRCUIT VLOAD Open GND RL RL Data Input Timing Input VI 0 V VI 0 V 0 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL VI 0 V Input Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VLOAD/2 0 V VOL + VΔ VOH - VΔ ≈ 0 V VI VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Output Control VM VM VM VM VM VM VM VM VM VM VM VM VI VM VM 2.7 V 1 kΩ 500 Ω 500 Ω 500 Ω VCC RL 2 × VCC 2 × VCC 6 V 6 V VLOAD CL 30 pF 30 pF 50 pF 50 pF 0.15 V 0.15 V 0.3 V 0.3 V VΔ VCC VCC 2.7 V 2.7 V VI VCC/2 VCC/2 1.5 V 1.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns INPUTS SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS286P JANUARY 1993 REVISED APRIL 2005 Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9761801Q2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-9761801QCA ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC 5962-9761801QDA ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC SN74LVC32AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI SN74LVC32ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVC32ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI SN74LVC32APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SNJ54LVC32AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SNJ54LVC32AJ ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC SNJ54LVC32AW ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

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8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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