54LS165

54LS165 NSC | Alldatasheet

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Semiconducto . 54LS165/DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in Data at the parallel inputs are loaded directly into the regis- the direction of Qa toward Qy when clocked. Parallel-inac- terona high-to-low transition of the shift/load input, regard- cess is made available by eight individual direct data inputs, _less of the logic levels on the clock, clock inhibit, or serial which are enabled by a low level at the shift/load input. inputs. These registers also feature gated clock inputs and comple- mentary outputs from the eighth bit. Features Clocking is accomplished through a 2-input NOR gate, per- = Complementary outputs mitting one input to be used as a clock-inhibit function. Hold- Direct overriding (data) inputs ing either of the clock inputs high inhibits clocking, and hold- @ Gated clock inputs ing either clock input low with the load input high enables |-to-seri A the other clock input. The clock-inhibit input should be : Paral * serial ota we sion changed to the high level only while the clock input is high. ypical frequency 35 N Parallel loading is inhibited as long as the load input is high. ™ Typical power dissipation 105 mW a Connection Diagram Dual-In-Line Package CLOCK PARALLEL INPUTS ‘SERIAL OUTPUT Voc INHIBIT “D c B A” INPUT Oy 6 15 14 13 2 bbl 10 9 1 2 3 4 5 6 7 6 SHIFT/ CLOCK E F G H_ OUTPUT GND LOAD ———— ay PARALLEL INPUTS TUF /6300-1 Order Number 54LS165DMQB, 54LS165FMQB, DM74LS165WM or DM74LS165N See NS Package Number J16A, M16B, N16E or W16A Function Table Inputs Qn toad L x x x ah a b h H L L x x Qho Qg0 Quo H L t H x H Qan Qen H L T L x L Qan Q6n H H x x x Qo Qg0 Quo H = High Level (steady state), L = Low Level (steady state) X = Don't Care (any input, including transitions) T = Transition trom low-to-high level a... = The level of steady-state input al inputs A through H, respectively. a0, Qz0, Qo = The level of Qa, Qg, or Qu, respectively, before the indicated steady-state input conditions were established. an Qan = The level of Q, or Qg, respectively, before the most recent T transition of the clock. 2191

w o @| Absolute Maximum Ratings (ote) a If Military/Aerospace specified devices are required, Note: The “Absolute Maximum Ratings” are those values please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran- Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The ‘Supply Voltage v parametric values defined in the “Electrical Characteristics” Input Voltage Ww table are not guaranteed at the absolute maximum ratings. Operating Froe Air Temperature R The “Recommended Operating Conditions” table will define perating Free Ait erature Range the conditions for actual device operation. 54LS —55°C to + 125°C ope DM74LS OC to +70°C Storage Temperature Range —65°C to + 150°C Recommended Operating Conditions DM74LS165 crm | eer Se ee | Toot Suppy vonage [4s | 5 | s5 [a] 5 | sa] v Vin High Level Input Voltage [2 [ye Vi Low Level Input Voltage [or oe Tv lon High Level Output Current Po on [04 | ima lou Low Level Output Current a OO Sd GB fcuk Glock Frequency (Note 1) a fouk Clock Frequency (Note 2) Po 0 te tw Pulse Wii | clock [ we ft tas Py (Note [toad [ois [Os tsu Setup Time | Part | to [| | to PT meres) [20 | sei | wo [ [fa fT | Enabe | so [| ft ao [shit [io as tw Hold Time (Note 6) [os |p yo Ps Ta Free Air Operating Temperature [ =s5 [| as | oo TT wm Tc Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) vi Input Clamp Voltage _| Voc = Min, || = —18mA a a ee Vou High Level Output | Voc = Min, lon = Max [sus fas | Ty Votage Vu=MaxVin= Min owra | a7] ga] Vou Low Level Output | Veo = Min, lo, = Max [sus fT oa | lon = 4 mA, Voc = Min [| 2s Toa | " Input Current @ Max | Voo=Max,Vi=7V(DM74) | shitload [|| 03 | a iewtVotage | i= Tov 64.8) [owes [os] NH High Level Input Voc = Max Shit/load | | | 0 | A Curent wean [ones [a | We Low Level Input Voc = Max Snitvtoad | [OT 12 | iy Core vin sav ones [=a | los Short Circuit Voc = Max a CuaputCurent | oie owes | =20 [|= 100 | loc Supply Current Voc = Max (Note 5) [tat a6 ma Note 1:C, = 15 pF, Ry = 2kM, Ta = 25°C and Voc = 5V Note 2: C, = 50 pF, Ry = 2kM, Ta = 25°C and Voc = 5V Note 3: Alll typicals are at Voc = 5V, Ta = 25°C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5; With all outputs open, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, Icc is measured first with the parallel inputs at 4.5V, then again grounded. Note 6: T, = 25°C and Voc = 5V. 2-192

Switching Characteristics at voc = 5v and Ts = 25°C (See Section 1 for Test Waveforms and Output Load) | a [sas [owas | From (Input) RL = 2ka fuax MaximumCiock Frequency [| as P20 Mz tPLH Propagation Delay Time Load to 37 ne Low to High Level Output ‘AnyQ tPHL Propagation Delay Time Load to ns High to Low Level Output AnyQ tPLH Propagation Delay Time Clock to ns Low to High Level Output AnyQ tPHL Propagation Delay Time Clock to 47 ns High to Low Level Output AnyQ tPLH Propagation Delay Time 27 ns Low to High Level Output tpHL Propagation Delay Time H 37 ns High to Low Level Output toQu tPLH Propagation Delay Time H ns Low to High Level Output toy tPHL Propagation Delay Time 32 ns High to Low Level Output Timing Diagram Typical Shift, Load, and inhibit Sequences CLOCK INHIBIT ‘SERIAL INPUT L SHIFT /LOAD ‘ (UH e_ im] mre rm F °_FL_ . 2 | OUTPUT Oy » * LefweLefrelifn ouTPuT Gy bo H]efrete Paqe LOAD TL/F/6999-3 2-193

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