54FCT374A NSC | Alldatasheet
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a = > CA National wureo00 | Q Semiconductor 4 N“N 54FCT/74FCT374A 5 Octal D Flip-Flop with TRI-STATE® Outputs 9 o General Description Features m~ The 'FCT374A is a high-speed, low-power octal D-type flip § NSC _54/74FCT374A is pin and functionally equivalent | J flop featuring separate D-type inputs for each flip-flop and to IDT 54/74FCT374A TRI-STATE outputs for bus-oriented_applications. A buff- @ Buffered positive edge triggered clock ° ered Clock (CP) and Output Enable (OE) are common to all ™ TRI-STATE outputs for bus-oriented applications iz} flip-flops. @ TTL input and output level compatible 2 m TTL inputs accept CMOS levels 0 @ High current latch up immunity lol = 48 mA (commercial) and 32 mA (military) 7 m Electrostatic discharge protection > 2 kV ZT @ Inherently radiation tolerant 7 mo] Logic Symbols Connection Diagrams = IEEE/IEC Pin Assignment Z — for DIP, Flatpak and SOIC = Do Dy Dz Ds Dy Ds Dg Dy yen " D cP cp Dc oi 20F-Vee g a fo 5] a i a a > 0; 02 03 04 Os Og 07 % 99 do43 18}-D, an | iy A a a m TL/F/10264-1 2 Fe os 16 F-05 ° 5—J Fs o,-46 isos i= oe a ee od 7 sf > 03-48 13 Dy ~~ ae a 06 6 03-49 12F-0, LF, eno10 tibee TL/F/10264-2 TLF/ 0264-3 [_ PinNames | __ Description | Do-D7 Data Inputs Pin Assignment cp Clock Pulse Input for LCC CE TRI-STATE Output Enable Input Ds Dy 0p 04 Dy Qo-07 TRI-STATE Outputs iayeicy 5 Dy GND &) 0, cP fi] Woe % Voc 0, 0, DEH Me Ds Os Og 05 Dy TLF/10264-4 TALSTATE® a registered trademark of National Somiconductor Crporaton FACT a trademark of National Semiconductor Corporation, ©1990 National Semicondictr Corporation TLIF/10264 \\ RRO-B20M120/Pantod in. S.A
Functional Description Truth Table The 'FCT374A consists of eight edge-triggered flip-flops [inputs | utputs with individual D-type inputs and TRI-STATE outputs. The buffered clock and buffered Output Enable are commonto. |__Dn | cP | OE | Om | all flip-flops. The eight flip-flops will store the state of their H ST L H individual D inputs that meet the setup and hold time re- L Wa L L quirements on the LOW-to-HIGH Clock (CP) transition. With x x 4 z the Output Enable (OE) LOW, the contents of the eight flip- flops are available at the outputs. When the OE is HIGH, the H = HIGH Voltage Level outputs go to the high impedance state. Operation of the ‘ = tow Voltage Level F a = Immaterial OE input does not affect the state of the flip-flops. 2 = tagh impedance 7” = LOW-to-HIGH Transition Logic Diagram 09 i) 1 05 % Os 6 % cp—] >0 ot gt] df pT gy gt gr a o_o Qo Qo Qo go Qo Qo oa S O e) ° ©) ° ° * ° ° 2) re) Q fe) e fe) aptly TY WY 1Y WY WY p Q 0, 0, 05 o, 05, Og 0, TUF/10264-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate Propagation delays.
Absolute Maximum Ratings (note 1) Recommended Operating If Military/Aerospace specified devices are required, Conditions Please contact the National Semiconductor Sales " Supply Voltage (Vcc) Office/Distributors for availability and specifications. 54FCTA 4.5V to 5.5V Terming! Voltage 6 74FCTA 4.75V to 5.25V with Respect to GND (VteRm) 54ECTA -0.5V to 7.0V Input Voltage OV to Voc 74FCTA —0.5V to 7.0V Output Voltage OV to Voc. Temperature under Bias (Tgias) Operating Temperature (Ta) . 7 74FCTA 55°C to + 125°C S4FCTA — 55°C to + 125°C 54FCTA 65°C to + 135°C 74FCTA O°C to +70°C Storage Temperature (Teta) Junction Temperature (Ty) ; 74FCTA —55°C to + 125°C coIP 175°C SAFCTA —65°C to + 150°C POIP 140°C Power Dissipation (P7) 0.5W DC Output Current (Iour) 120 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without ‘exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of FACT FCT circuits outside databook specifications. DC Characteristics for "FCTA Family Devices Typical values are at Vcc = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value specified for the appropriate device type: Com: Voc = 5.0V 5%, Ta = O°C to + 70°C; Mil: Veg = 5.0V +10%, Ta = —55°C to + 125°C, Vic = Voc — 0.2V. Symbol SAFCTA/T4RCTA Conditions Min Typ Max Vie Minimum High Level v Input Voltage Vir Maximum Low Level Vv Input Voltage hy Input High Current a | Yoo = Max Vi = Voo - Vi = 2.7V (Note 2) UL Input Low Current a | Yoo = Max V, = 0.5V (Note 2) La Vv, = GND loz Maximum TRI-STATE Current 10.0 Voc = Max Vo = Veo 10.0 A Vo = 2.7V (Note 2) 100} ™ Vo = 0.5V (Note 2) -10.0 Vo = GND Vik Clamp Diode Voltage Voc = Min; Iy = —18mA los__| Shor Grcuitcurent | 0-120 | ma_| Vo = Max Note 1); Vo = GND Vou Minimum High Level 28 © 3.0 Voc = 3V: Vin = 0.2V or Vic; lon = —32 pA Output Voltage Vac Veo y_| Yoo = Min lon = —300 yA 24 43 Vin = Vi or Vit, loH = —12 mA (Mil) 24 43 lox = —15 mA (Com) VoL Maximum Low Level GND 0.2 Voc = 3V; Vin = 0.2V or Vic; lor = 300 pA Output Voltage GND 02 y_ | Yoo = Min lot = 300 pA 03 0.50 Vin = Vin or Vit lo, = 32 mA (Mil) 03 0.50 lo, = 48 mA (Com) loc Maximum Quiescent Voc = Max Supply Current 0.001 «1.5 | MA | Vin> Vic. Vin < 0.2V Alec Quiescent Supply Current; ma_| Yoo = Max TTL Inputs HIGH Vin = 3.4V (Note 3)
DC Characteristics for ’FCTA Family Devices (continues) Typical values are at Voc = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value ‘specified for the appropriate device type: Com: Voc = 5.0V +5%, Ta = 0°C to + 70°C; Mil: Voc = 5.0V +10%, Ta = —55°C to +125°C, Vuc = Voc — 0.2V. loeb Dynamic Power Voc = Max Vin = Vuc Supply Current (Note 4) Outputs Open Vin < 0.2V 0.15 0.25 mA/MHz OE - GND ‘One Input Toggling 50% Duty Cycle Io Total Power Supply Voc = Max Vin = Vic Current (Note 6) 18 40 Outputs Open Vin < 0.2V ° ° fop = 10 MHz OE = GND | = 5.0 MHz Vin = 34V 20 60 One Bit Toggling Vin = GND 50% Duty Cycle mA (Note 5) Vin = Vac Voc = Max Vin < 0.2V 3.78 78 Outputs Open fop = 10 MHz OE = GND f= 25MHz Vin = 3.4V 6.0 16.8 Eight Bits Toggling Vin = GND 50% Duty Cycle Vu Input Hysteresis. Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time. Note 2: This parameter guaranteed but not tested. Note 3: Per TTL driven input {Vij = 3.4V); all other inputs at Voc or GND. Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Note 5: Values for these conditions are examples of the icc formula. These limits are guaranteed but not tested. Note 6: lc = lauiescent + inputs + loynaMic Io = lec + Bloc DyNr + Iocp (fcp/2 + f, Ni) lec = Quiescent Current Alcc = Power Supply Current for a TTL High Input (Vin = 3.4V) Dy = Duty Cycle for TTL Inputs High Ny = Number of Inputs at Dy Igcp = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) {cp = Clock Frequency for Register Devices (Zero for Non-Register Devices) (= Input Frequency 'N, = Number of Inputs at f, All currents are in milliamps and all frequencies are in megahertz.
S4FCTA/74FCTA 74FCTA S4FCTA _ Ta, Voc = Com Ta, Voc = Mil symbol ’ i ay Ry = 5000 Ry — 5000 Units coe CL = 50 pF C, = 50 pF [tye | Minwwote Max | iniwote 1) Max | tet Propagation Delay tet Cp to On 45 20 65 ns tpzH Output Enable Time 55 15 65 ns teze : : tpHz Output Disable Time 18 55 ns teiz : : tsu Set Up Time High or Low Dp top 2.0 ns tH Hold Time High or Low Dp to Cp 16 ns tw Cp Pulse Width High or Low 40 ns Note 1: Minimum limits are guaranteed but not tested on propagation delays. Capacitance 1, = + 25°C, = 1.0MHz InputGapactance | 6 | 10 | pr | v= ov Note: This parameter is measured at characterization but not tested.
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74FCT 3744 P C QR Temperature Range Family —__]- LL Special Variations 74FCT = Commercial TTL-Compatible X = Devices shipped in 13” 54FCT = Military TTL-Compatible reels A QR = Commercial grade device Device Type with burn-in Package Code QB = Military grade device with P = Plastic DIP environmental and burn-in D = Ceramic DIP processing shipped in tubes F = Flatpak ; ; Temperature Range L = Leadless Ceramic Chip Carrier (LCC) C = Commercial (0°C to + 70°C) S = Small Outline (SOIC) M = Military (55°C to + 125°C)
Physical Dimensions inches (mitimeters) 0.200 + 0.005 (5.080=0.127) TP 5. 0.015 +0.010 vw TI 7 ™ pzar20 256) gato Ss “9.007 0.011 ie 50205 <— ness ay pooner | ian | | te mur pS | Aaa QU | UU 0.022.028 Tre oS (0589-0.711) aor7-o.093 4 =) q t YP (1-959—2-362) = a P 0.045—0.055 G = SSS Z i wa-1a5n AA one ~ ty 143—1.357) Top View Side View We Zo age 0.04040.010 11.016 20.254) 3PLCS Bottom View 0.015 0.003 ons on ~ (0.38 (.076}- wre ¥ ert mace 0.07 WAX TYP ® wt Detail A an never 20-Terminal Ceramic Leadiess Chip Carrier (L) 0.985 0.025 1g) (0.635) max heed Fd [3] {v6} [+5} v4) [rs] fr) fr 20-0310 (6.588—7.874) fu EEOC 0.005 — 0.020 (0.127—0.508) mo TYP 0.037 + 0.005 [vase en 0.005, 0.055 + 0.005 war) | BLASS SEALANT “iN 70-308=1.524) Pf im cr] amo (ORO ROR EOS Ly WAX 55° ‘86° 94° Foi ets 920 908-0012 Ga 21-02m (0.203 0.305) [0310-040 | 0.060 P| orn ENDS 0.1000.010 @smoxa2s4) 20a evn 20-Lead Ceramic Dual-In-Line Package (D)
Physical Dimensions inches (mitiimeters) (Continued) ness t itecney | TARA AAABAAD i AT tt fo ena ine we went TOU UCTECT EL { VUREEYEEE EX Preise rad w iozn omen er son-00m . , fem -1.108 (w2st—o7an ** r ones pier ee _ a SN ee t + i trae 5 ue | 016-09, am -o| ea | |. oon 010 yp mem) gta eae oan Z ‘asso 0.008 ryp ‘e700 ener 20-Lead Small Outline Integrated Circuit (S) 0.970-0.990 (2.337 0.762) i 0.032 20,005, ‘wax OP LL of dans \\ BLL \\ RAD 0.240-0.260 PINNO.T IDENT e) © (6.096-6.604) PINNO. 1IDENT —~_ 0280 ie attri OPTION) ay a j OY Ca Ted Ca eT TAT TAY Tad ay + GC] ! 0.090 OPTION 2 oes 0.060, NOM 0.040 I OPTION 2 Ar 0.130 0.005 ! ooss 1528) ira win can | | 0.145-0.200 97.5" +75" n0oe-o0rs! ~ aro ce" | 7 ° I (o.203-0.381) as ee 10020010 _ | LL 0.125-0.150 (0508) O58) om (8.890) soe Rev 20-Lead Plastic Dual-In-Line Package (P)
2 Physical Dimensions inches (mitimeters) (Continued) Lit. # 114703 3s 0.060-0.090 0.540 i TYP od 0.250-0.320 D (6.350=8.128) [oa = f 2019 1817161514 1312 11 = MAX Glass (6.604=6.858) 234567 8 910 0.008-0.012 J Ro} A F DETAIL A ue ome Mf 0.250-0.320 a HIN 91 (6.350-8.128) = (DENT Lu W20A (REV D) (=) lL gce10.08 np - Le QaLs0018 np - Gr.143) MACTIP ws 20-Lead Ceramic Flatpak (F) wv ld o Ee oO re vt aN oO ire uw LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL, SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury os yf to the user. a a U4) National Semiconductor Nalionsl Semiconductor National Semiconductor National Semiconductor National Semicondutores National Semiconductor Corporation Gmott Japan Lia. Hong Kong Lid. Do Graal isa, (Austral PTY, Lia. 2000 Semeandvetor Drive industesrasse 10 Sanseido 8g. SF Sute 513 5th Floor Av. Brig Fara Lime, 1983 Ist Flor, 441 St. Kida Ad PO. Box 58090, (0.2080 Furstenelsoruck 4:15 Nis Shins Chachem Golden Paz, 0 Ando. Cony, 62 Matbourne, 3004 Santa Cua, CA 95052-8090 West Germany ShyokeKu, 77 Mody Road, Tamshetau East, 01451 Sao Paulo, SP, Bras Victory. Austraa Ta (000) 272.0059 Ter (084-41) 10.0 Tokyo 160, Japan Kowloon, Hong Kang Tot (58/11) 212.5008 Tat (03) 267-5000 WE (910) 339-9240 Telex 527-649 Tet 3-208-7001 To 3-7291290 Fax: (55/11) 217-1181 NSBR BR Fax: 61-3:2677458 Fax (08141) 100554 FAX: 3:299-7000 “Telex. 52996 NSSEA HK Fax: 93112598 ‘tence ety nec tte ei on bn ey eg specications