54FCT273 NSC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

n Eight edge-triggered D flip-flops n Buffered common clock n Buffered, asynchronous Master Reset n See ’FCT377 for clock enable version n See ’FCT373 for transparent latch version n See ’FCT374 for TRI-STATE® version n Output sink capability of 32 mA, source capability of 12 mA n TTL input and output level compatible n CMOS power consumption n Standard Microcircuit Drawing (SMD) 5962-8765601 Ordering Code Military Package Package Description Number 54FCT273DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT273FMQB W20A 20-Lead Cerpack 54FCT273LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Description Names D 0–D 7 Data Inputs MR Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q 0–Q 7 Data Outputs TRI-STATE® is a registered trademark of National Semiconductor Corporation. Pin Assignment for DIP and Flatpack DS100956-1 Pin Assignment for LCC DS100956-2 August 1998 54FCT273 Octal D-Type Flip-Flop © 1998 National Semiconductor Corporation DS100956 www.national.com

Mode Select-Function Table Operating Mode Inputs Output MR CP D n Q n Reset (Clear) L X X L Load “1” H N h H Load “0” H N l L H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran- sition L = LOW Voltage Level steady state I= LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran- sition X = Immaterial N = LOW-to-HIGH clock transition Logic Diagram DS100956-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias Ceramic −55˚C to +175˚C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +4.75V in the HIGH State −0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current −500 mA (Across Comm Operating Range) Over Voltage Latchup V CC + 4.5V Recommended Operating Conditions Free Air Ambient Temperature Military −55˚C to +125˚C Supply Voltage Military +4.5V to +5.5V Note 1:Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2:Either voltage limit or current limit is sufficient to protect inputs. Symbol Parameter FCT240 Units V CC Conditions Min Max VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH Voltage 54FCT 4.3 V Min I OH = −300 uA 54FCT 2.4 V Min I OH = −12 mA VOL Output LOW Voltage 54FCT 0.2 V Min I OL = 300 µA 54FCT 0.5 V Min I OL = 32 mA IIH Input HIGH Current 5 µA Max V IN = 5.5V IIL Input LOW Current −5 µA Max V IN = 0.0V IOS Output Short-Circuit Current −60 mA Max V OUT = 0.0V ICCQ Power Supply Current 1.5 mA Max V IN = 0.2V or VIN = 5.3V ΔICC Power Supply Current 2.0 mA Max V IN = 3.4V ICCT Total Power Supply Current 6.0 mA Max VIN = 3.4V or VIN = GND, OE = GND, fI = 10Mhz, outputs open, one bit toggling - 50% duty cycle 4.0 mA Max VIN = 5.3V or VIN = 0.2V,OE = GND, fI = 10Mhz, outputs open, one bit toggling - 50% duty cycle ICCD Dynamic ICC 0.25 mA/MHz Max Outputs Open,OE= GND, One Bit Toggling, 50% Duty Cycle Symbol Parameter 54FCT Units Fig. No. TA = −55˚C to +125˚C VCC = 4.5V to 5.5V C L = 50 pF Min Max tPLH Propagation Delay 2.0 15.0 ns Figures 2, 5 tPHL CP to On 2.0 15.0 tPHL Propagation Delay 2.0 15.0 ns Figures 2, 5 MR to On www.national.com3

TA = −55˚C to +125˚C Symbol Parameter V CC = 4.5V to 5.5V Units Fig. No. C L = 50 pF Min Max ts(H) Setup Time, HIGH 3.5 ns Figure 6 ts(L) or LOW D n to CP 3.5 th(H) Hold Time, HIGH 2.5 ns Figure 6 th(L) or LOW D n to CP 2.5 tw (H) Pulse Width, CP, 7.0 ns Figure 2 tw (L) HIGH or LOW 7.0 tw (L) Master Reset Pulse 7.0 ns Figure 2 Width, LOW tREC Recovery Time 5.0 ns Figure 6 MR to CP Capacitance Symbol Parameter Max Units Conditions TA = 25˚C C IN Input Capacitance 10 pF V CC = 0V C OUT (Note 3) Output Capacitance 12 pF V CC = 5.0V Note 3:C OUT is measured at frequency f= 1 MHz, per MIL-STD-833B, Method 3012. www.national.com 4

Physical Dimensionsinches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) 20-Lead Ceramic Dual-In-Line (D) www.national.com7

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 20-Lead Ceramic Flatpak (F) 54FCT273 Octal D-Type Flip-Flop National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.