54F377

54F377 TI1 | Alldatasheet

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54F377 Octal D Flip-Flop with Clock Enable Literature Number: SNOS191A

54F/74F377 Octal D Flip-Flop with Clock Enable May 1995 54F/74F377 Octal D Flip-Flop with Clock Enable General Description The ’F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE ) is LOW. The register is fully edge-triggered. The state of each D in- put, one setup time before the LOW-to-HIGH clock tran- sition, is transferred to the corresponding flip-flop’s Q out- put. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable opera- tion.

Features

Y Ideal for addressable register applications Y Clock enable for address and data synchronization

applications

Y Eight edge-triggered D flip-flops Y Buffered common clock Y See ’F273 for master reset version Y See ’F373 for transparent latch version Y See ’F374 for TRI-STATE É version Y Guaranteed 4000V minimum ESD protection Commercial Military Package Package DescriptionNumber 74F377PC N20A 20-Lead (0.300 × Wide) Molded Dual-In-Line 54F377DM (QB) J20A 20-Lead Ceramic Dual-In-Line 74F377SC (Note 1) M20B 20-Lead (0.300 × Wide) Molded Small Outline, JEDEC 74F377SJ (Note 1) M20D 20-Lead (0.300 × Wide) Molded Small Outline, EIAJ 54F377FM (QB) W20A 20-Lead Cerpack 54F377LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX and SJX. Logic Symbols TL/F/9525–1 IEEE/IEC TL/F/9525–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A. Obsolete

DIP, SOIC and Flatpak TL/F/9525–2 Pin Assignment for LCC TL/F/9525–3 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL D0 –D7 Data Inputs 1.0/1.0 20 mA/b0.6 mA CE Clock Enable (Active LOW) 1.0/1.0 20 mA/b0.6 mA CP Clock Pulse Input 1.0/1.0 20 mA/b0.6 mA Q0 –Q7 Data Outputs 50/33.3 b1 mA/20 mA Mode Select-Function Table Operating Mode Inputs Output CP CE Dn Qn Load ‘‘1’’ L Ih H Load ‘‘0’’ L II L Hold L h X No Change (Do Nothing) X H X No Change H e HIGH Voltage Level h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L e LOW Voltage Level I e LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X e Immaterial L e LOW-to-HIGH Clock Transition Logic Diagram TL/F/9525–5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Obsolete

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATE Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0§Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 IOH eb 1m A Voltage 74F 10% V CC 2.5 V Min I OH eb 1m A 74F 5% V CC 2.7 IOH eb 1m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 20 mA Voltage 74F 10% V CC 0.5 IOL e 20 mA IIH Input HIGH Current 5.0 mA Max V IN e 2.7V IBVI Input HIGH Current 7.0 mA Max VIN e 7.0V Breakdown Test IIL Input LOW Current b0.6 mA Max V IN e 0.5V IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V ICEX Output HIGH Leakage Current 50 mA Max V OUT e VCC VID Input Leakage Test 4.75 V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded ICCH Power Supply Current 35 46 mA Max CP e L ICCL 44 56 Dn e MR e HIGH Obsolete

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter VCC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fMax Maximum Clock Frequency 130 85 105 MHz AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 74F 377 S C X Temperature Range Family Special Variations 74F e Commercial X e Devices shipped in 13 × reels 54F e Military QB e Military grade with environmental and burn-in processing shipped Device Type in tubes Package Code Temperature RangeP e Plastic DIP C e Commercial (0 §Ct o a70§C)D e Ceramic DIP M e Military ( b55§Ct o a125§C)S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Obsolete

Physical Dimensions inches (millimeters) 20-Lead Ceramic Dual-In-Line Package (D) 20-Lead (0.300 × Wide) Molded Small Outline Package, JEDEC (S) Obsolete

Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300 × Wide) Molded Small Outline Package, EIAJ (SJ) Obsolete

54F/74F377 Octal D Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300 × Wide) Molded Dual-In-Line Package (P) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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