54F191 NSC | Alldatasheet
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Y High-SpeedÐ125 MHz typical count frequency Y Synchronous counting Y Asynchronous parallel load Y Cascadable Commercial Military Package Package DescriptionNumber 74F191PC N16E 16-Lead (0.300 × Wide) Molded Dual-In-Line 54F191DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line 74F191SC (Note 1) M16A 16-Lead (0.150 × Wide) Molded Small Outline, JEDEC 74F191SJ (Note 1) M16D 16-Lead (0.300 × Wide) Molded Small Outline, EIAJ 54F191FM (Note 2) W16A 16-Lead Cerpack 54F191LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols TL/F/9495–1 IEEE/IEC TL/F/9495–4 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak TL/F/9495–2 Pin Assignment for LCC TL/F/9495–3 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL CE Count Enable Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA P0 –P3 Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA U/D Up/Down Count Control Input 1.0/1.0 20 mA/b0.6 mA Q0 –Q3 Flip-Flop Outputs 50/33.3 b1 mA/20 mA RC Ripple Clock Output (Active LOW) 50/33.3 b1 mA/20 mA TC Terminal Count Output (Active HIGH) 50/33.3 b1 mA/20 mA Functional Description The ’F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL ) input is LOW, information pres- ent on the Parallel Data inputs (P 0–P3) is loaded into the counter and appears on the Q outputs. This operation over- rides the counting functions, as indicated in the Mode Se- lect Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U /D input signal, as indi- cated in the Mode Select Table. CE and U /D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count- down mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U /D is changed. The TC output should not be used as a clock signal be- cause it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC ) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figures 1 and 2. In Fig- ure 1 , each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state chang- es in the first and last stages. This represents the cumula- tive delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2 . All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the neg- ative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The sim- ple inhibit scheme of Figures 1 and 2 doesn’t apply, be- cause the TC output of a given stage is not affected by its own CE Mode Select Table Inputs Mode PL CE U/D CP HL L L Count Up HL H L Count Down L X X X Preset (Asyn.) H H X X No Change (Hold) RC Truth Table Inputs Output CE TC* CP RC LH ßß HX X H XL X H *TC is generated internally H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition ß e LOW Pulse
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATEÉ Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1m A Voltage 74F 10% V CC 2.5 V Min I OH eb 1m A 74F 5% V CC 2.7 I OH eb 1m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 20 mA Voltage 74F 10% V CC 0.5 I OL e 20 mA IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA, Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max VIN e 0.5V (except CE ) b1.8 V IN e 0.5V (CE ) IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V ICC Power Supply Current 38 55 mA Max
TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fmax Maximum Count Frequency 100 125 75 90 MHz
Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 ts(L) P n to PL 4.5 6.0 5.0 ns th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 th(L) P n to PL 2.0 2.0 2.0 ts(L) Setup Time LOW 10.0 10.5 10.0CE to CP ns th(L) Hold Time LOW 000CE to CP ts(H) Setup Time, HIGH or LOW 12.0 12.0 12.0 ts(L) U /D to CP 12.0 12.0 12.0 ns th(H) Hold Time, HIGH or LOW 0 0 0 th(L) U /D to CP 0 0 0 tw(L) PL Pulse Width LOW 6.0 8.5 6.0 ns tw(L) CP Pulse Width LOW 5.0 7.0 5.0 ns trec Recovery Time 6.0 7.5 6.0 nsPL to CP
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 191 S C X Temperature Range Family Special Variations 74F e Commercial X e Devices shipped in 13 × reels 54F e Military QB e Military grade with environmental and burn-in processing shipped Device Type in tubes Package Code Temperature RangeP e Plastic DIP C e Commercial (0 §Ct o a70§C)D e Ceramic DIP M e Military ( b55§Ct o a125§C)F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ
Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) 16-Lead Ceramic Dual-In-Line Package (D)
Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150 × Wide) Molded Small Outline Package, JEDEC (S) 16-Lead (0.300 × Wide) Molded Small Outline Package, EIAJ (SJ)
Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300 × Wide) Molded Dual-In-Line Package (P)
54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.