54F181DM

54F181DM NSC | Alldatasheet

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Y Full lookahead for high-speed arithmetic operation on long words Y Guaranteed 4000V minimum ESD protection Commercial Military Package Package DescriptionNumber 74F181PC N24A 24-Lead (0.600 × Wide) Molded Dual-In-Line 74F181SPC N24C 24-Lead (0.300 × Wide) Molded Dual-In-Line 54F181DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line 54F181SDM (Note 2) J24F 24-Lead (0.300 ×) Ceramic Dual-In-Line 74F181SC (Note 1) M24B 24-Lead (0.300 ×) Molded Small Outline, JEDEC 54F181FM (Note 2) W24C 24-Lead Cerpack 54F181LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier,Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak TL/F/9491–1 Pin Assignment for LCC TL/F/9491–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/9491–3 Active-LOW Operands TL/F/9491–4 IEEE/IEC TL/F/9491–10 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL A0 –A3 A Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA B0 –B3 B Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA S0 –S3 Function Select Inputs 1.0/4.0 20 mA/b2.4 mA M Mode Control Input 1.0/1.0 20 mA/b0.6 mA Cn Carry Input 1.0/5.0 20 mA/b3.0 mA F0 –F3 Function Outputs (Active LOW) 50/33.3 b1 mA/20 mA A e B Comparator Output OC */33.3 */20 mA G Carry Generate Output (Active LOW) 50/33.3 b1 mA/20 mA P Carry Propagate Output (Active LOW) 50/33.3 b1 mA/20 mA Cn a 4 Carry Output 50/33.3 b1 mA/20 mA *OC-Open Collector Functional Description The ’F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs 0 –S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations. When the Mode Control input (M) is HIGH, all internal car- ries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the C n a 4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed require- ments are not stringent, the ’F181 can be used in a simple Ripple Carry mode by connecting the Carry output (C na4) signal to the Carry input (C n) of the next unit. For high speed operation the device is used in conjunction with a carry look- ahead circuit. One carry lookahead package is required for each group of four ’F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A eB output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equiva- lence over four bits when the unit is in the Subtract mode. The A eB output is open collector and can be wired AND with other A eB outputs to give a comparison for more than four bits. The A eB signal can also be used with the C na4 signal to indicate A lB and A kB. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Be- cause subtraction is actually performed by complementary addition (1s complement), a carry out means borrow ; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this de- vice can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the oper- ations that are performed to the operands labeled inside the logic symbol.

’F181 Operation Table Logic Arithmetic Arithmetic S0 S1 S2 S3 (MeH) (M eL, C 0eInactive) (M eL, C 0eActive) LLLL A A minus 1 A HLLL A # B A # B minus 1 A # B LHLL A a BA # B minus 1 A # B H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero LLHL A a B A plus (A a B) A plus (A a B) plus 1 HLHL B A # B plus (A a B)A # B plus (A a B) plus 1 LHHL A Z B A minus B minus 1 A minus B HHHL A a B A a B A a B plus 1 LLLH A # B A plus (A a B) A plus (A a B plus 1 HLLH A Z B A plus B A plus B plus 1 LHLH B A # B plus (A a B) A # B plus (A a B) plus 1 HHLH A a BA a BA a B plus 1 L L H H Logic ‘‘0’’ A plus A (2 c A) A plus A (2 c A) plus 1 HLHH A # B A plus A # B A plus A # B plus 1 LHHH A # B A plus A # B A plus A # B plus 1 H H H H A A A plus 1 LLLL A A A plus 1 HLLL A a B A a BA a B plus 1 LHLL A # BA a B A a B plus 1 H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero LLHL A # B A plus (A # B) A plus A # B plus 1 HLHL B A # B plus (A a B) A # B plus (A a B) plus 1 LHHL A Z B A minus B minus 1 A minus B HHHL A # B A # B minus 1 A # B LLLH A a B A plus A # B A plus A # B plus 1 HLLH A Z B A plus B A plus B plus 1 LHLH B A # B plus (A a B)A # B plus (A a B) plus 1 HHLH A # BA # B minus 1 A # B L L H H Logic ‘‘1’’ A plus A (2 c A) A plus A (2 c A) plus 1 HLHH A a B A plus (A aB) A plus (A aB) plus 1 LHHH A a B A plus (A a B) A plus (A aB) plus 1 H H H H A A minus 1 A LLLL A A minus 1 A HLLL A a BA # B minus 1 A # B LHLL A # B A # B minus 1 A # B H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero LLHL A # B A plus (A a B) A plus (A a B) plus 1 HLHL B A # B plus (A a B) A # B plus (A a B) plus 1 LHHL A Z B A plus B A plus B plus 1 HHHL A a BA a BA a B plus 1 LLLH A a B A plus (A a B) A plus (A a B) plus 1 HLLH A Z B A minus B minus 1 A minus B LHLH B A # B plus (A a B)A # B plus (A a B) plus 1 HHLH A a B A a B A a B plus 1 L L H H Logic ‘‘0’’ A plus A (2 c A) A plus A (2 c A) plus 1 HLHH A # B A plus A # B A plus A # B plus 1 LHHH A # B A plus A # B A plus A # B plus 1 H H H H A A A plus 1 LLLL A A A plus 1 HLLL A # BA a B A a B plus 1 LHLL A a B A a BA a B plus 1 H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero LLHL A a B A plus A # B A plus A # B plus 1 HLHL B A # B plus (A a B)A # B plus (A a B) plus 1 LHHL A Z B A plus B A plus B plus 1 HHHL A # BA # B minus 1 A # B LLLH A # B A plus A # B A plus A # B plus 1 HLLH A Z B A minus B minus 1 A minus B LHLH B A # B plus (A a B) A # B plus (A a B) plus 1 HHLH A # B A # B minus 1 A # B L L H H Logic ‘‘1’’ A plus A (2 c A) A plus A (2 c A) plus 1 HLHH A a B A plus (A aB) A plus (A aB) plus 1 LHHH A a B A plus (A a B) A plus (A aB) plus 1 H H H H A A minus 1 A a. All Input Data Inverted b. All Input Data True c. A Input Data Inverted; B Input Data True d. A Input Data True; B Input Date Inverted

TL/F/9491–5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATEÉ Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1m A Voltage 74F 10% V CC 2.5 V Min I OH eb 1m A 74F 5% V CC 2.7 I OH eb 1m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 20 mA Voltage 74F 10% V CC 0.5 I OL e 20 mA IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max VOUT e VCC (Fn,G ,P ,C na4) Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 V IN e 0.5V (M) b1.8 mA Max VIN e 0.5V (A 0,A 1,A 3,B 0,B 1,B 3) b2.4 V IN e 0.5V (S n,A 2,B 2) b3.0 V IN e 0.5V (C n) IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V (F n,G ,P ,C na4) IOHC Open Collector, Output 250 mA Min VO e VCC (A e B) OFF Leakage Test ICCH Power Supply Current 43 65.0 mA Max V O e HIGH ICCL Power Supply Current 43 65.0 mA Max V O e LOW

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Path Mode Min Typ Max Min Max Min Max

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 181 P C Temperature Range Family Special Variations 74F e Commercial QB e Military grade device with 54F e Military environmental and burn-in processingDevice Type Temperature RangePackage Code C e Commercial (0 §Ct o a70§C)P e Plastic DIP M e Military ( b55§Ct o a125§C)SP e Slim Plastic DIP D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC

Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) 24-Lead Ceramic Dual-In-Line Package (D)

Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300 × Wide) Ceramic Dual-In-Line Package (SD) 24-Lead (0.300 × Wide) Molded Small Outline Package, JEDEC (S)

Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.600 × Wide) Molded Dual-In-Line Package (P) 24-Lead (0.300 × Wide) Molded Dual-In-Line Package (SP)

54F/74F181 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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