54ETL16245

54ETL16245 NSC | Alldatasheet

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Features

Y Supports the VME64 ETL specification Y Functionally and pin compatible with industry standard TTL 16245 SSOP pinout Y Improved TTL-compatible input threshold range Y High drive TTL-compatible outputs (I OH eb 60 mA, IOL e 90 mA) Y Supports 25 X incident wave switching on the A port Y BiCMOS design significantly reduces power dissipation. Y Distributed V CC and GND pin configuration minimizes high-speed switching noise Y 25X series-dampening resistor on B-port Y Available in 48-pin SSOP and ceramic flatpak Y Guaranteed output skew Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Guaranteed latchup protection Logic Symbol TL/F/11654–1 Pin Description Pin Names Description DIR Transmit/Receive Input OE Output Enable Input (Active LOW) An Backplane Bus Data Bn Local Bus Data Connection Diagram Pin Assignment for SSOP and Flatpak TL/F/11654–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

The device uses byte-wide Direction (DIR) control and Out- put Enable (OE ) controls. The DIR inputs determine the di- rection of data flow through the device. The OE inputs dis- able the A and the B ports. The part contains active circuitry which keeps all outputs disabled when V CC is less than 2.2V to aid in live insertion applications. Truth Table (Each 8-bit Section) Inputs Operation OE DIR L L A Data to B Bus L H B Data to A Bus H X Isolation Logic Diagrams (Positive Logic) TL/F/11654–3 TL/F/11654–4 ETL’s Improved Noise Immunity TTL input thresholds are typically determined by tempera- ture-dependent junction voltages which result in worst case input thresholds between 0.8V and 2.0V. By contrast, ETL provides greater noise immunity because its input thresh- olds are determined by current mode input circuits similar to those used for ECL or BTL. ETL’s worst case input thresh- olds, between 1.4V and 1.6V, are compensated for temper- ature, voltage and process variations. Incident Wave Switching When TTL logic is used to drive fully loaded backplanes, the combination of low backplane bus characteristic imped- ance, wide TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a val- id signal can be received across the backplane. The VME International Trade Association (VITA) defined ETL to pro- vide incident wave switching which increases the data trans- fer rate of a VME backplane and extends the life of VME applications. TTL compatibility with existing VME back- planes and modules was maintained. Improved Input Threshold Characteristics of ETL TL/F/11654–5 ABTC Worst Case V OUT –VIN TL/F/11654–6 ETL Worst Case V OUT –VIN

Incident Wave Switching (Continued) To demonstrate the incident wave switching capability, con- sider a VME application. A VME bus must be terminated to a2.94V with 190 X at each end of its 21 card backplane. The surge impedance presented by a fully loaded VME backplane is approximately 25 X. If the output voltage/cur- rent of an ABTC driver is plotted with this load, the inter- section at 1.2V for a falling edge and at 1.6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit. This is shown in the two figures below. However, an ETL driver located at one end of the backplane is able to provide incident wave switching because it has a higher drive and a tighter input threshold. Estimated ETL/ABTC Initial Falling Edge Step TL/F/11654–7 Because ETL has a much more precise input threshold re- gion, an ETL receiver will interpret its predicted falling input of 0.85V as a logic ZERO and the initial rising edge of 1.9V as a logic ONE. This comparison is for the case of a 25 X surge impedance backplane driven from one end. Estimated ETL/ABTC Initial Rising Edge Step TL/F/11654–8 The resulting ABTC and ETL waveform predictions and their input thresholds are compared below. This shows how ETL can achieve backplane speeds not always possible with conventional TTL compatible logic families. Comparing the Incident Wave Switching of ETL with ABTC TL/F/11654–9

Incident Wave Switching (Continued) The figure V CC Power-up Critical Voltages shows the rela- tionship between OE and V CC while power is being applied and removed. TL/F/11654–10 VCC and OE Power-up Relationship

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias Ceramic b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b50 mA to a5.0 mA Voltage Applied to Any Output in the Disabled or Power-off State b0.5V to 5.5V in the HIGH State b0.5V to V CC Current Applied to Output in LOW State (Max) 128 mA DC Latchup Source Current b500 mA Over Voltage Latchup (I/O) 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial b40§Ct o a85§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Minimum Input Edge Rate ( Dt/DV) Data Input 20 ns/V Enable Input 50 ns/V Symbol Parameter ETL16245 Units V CC Conditions Min Typ Max VIH Input HIGH Voltage OE 2.0 V Recognized HIGH Signal Other Inputs 1.6 VIL Input LOW Voltage OE 0.8 V Recognized LOW Signal Other Inputs 1.4 VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA (OE n, DIR) VOH Output HIGH Voltage V CC b 1V I OH eb 100 mA B Port 2.4 V Min I OH eb 1m A

2.0 V I OH eb 12 mA

A Port 2.4 V Min I OH eb 32 mA

2.0 V I OH eb 60 mA

VOL Output LOW Voltage B Port 0.4 V Min IOL e 1m A

0.8 V I OL e 12 mA

A Port 0.55 V Min IOL e 64 mA

0.9 V I OL e 90 mA

A Port, 100 mA Min OE e HIGH, VO e 0.8V b100 OE e HIGH, VO e 2.0V IOFF Output Current, Power Down 100 mA 0.0 VCC Bias e 0V VI or V O s 4.5V II Input Current Control Pins 54ETL g10 mA 5.5 V IN e 0o rV CC 74ETL g5 mA 5.5 V IN e 0o rV CC IIH a Output Leakage Current 50 mA 5.5 V OUT e 2.7V, OE e 2.0VIOZH IIL a Output Leakage Current b50 mA 5.5 V OUT e 0.5V, OE e 2.0VIOZL

ICCH Power Supply Current 40 mA Max All Outputs HIGH, OE e LOW, DIR e HIGH or LOW ICCL Power Supply Current 80 mA Max All Outputs LOW, OE e LOW, DIR e HIGH or LOW ICCZ Power Supply Current OE e HIGH 40 mA Max All Others at V CC or GND DIR e HIGH or LOW ICCD Dynamic I CC

0.15 MHz

No Load OEn e GND, DIR e HIGH (Note 1) One Bit Toggling, 50% Duty Cycle VOLP Quiet Output Maximum 1.0 V 5.0 T A e 25§C (Note 2) Dynamic V OL CL e 50 pF; R L e 500X VOLV Quiet Output Minimum b1.4 V 5.0 TA e 25§C (Note 2) Dynamic V OL CL e 50 pF; R L e 500X VOHV Minimum High Level Dynamic 2.7 V 5.0 TA e 25§C (Note 4) Output Voltage (Note 1) C L e 50 pF; R L e 500X VIHD Minimum High Level Dynamic 2.0 1.5 V 5.0 TA e 25§C (Note 3) Input Voltage (Note 1) C L e 50 pF; R L e 500X VILD Maximum Low Level Dynamic 1.2 0.8 V 5.0 TA e 25§C (Note 3) Input Voltage (Note 1) C L e 50 pF; R L e 500X Note 1: Guaranteed, but not tested. Note 3: Max. number of data inputs (n) switching. n b 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (V IHD). Guaranteed, but not tested. Symbol Parameter 74ETL 54ETL 74ETL Units Fig. No. TA ea 25§CT A eb 55§Ct o a125§CT A eb 40§Ct o a85§C VCC ea 5V V CC e 4.5V–5.5V V CC e 4.5V–5.5V Min Typ Max Min Max Min Max tr Rise Time 1V x 2V, 1.2 3.0 1.2 3.0 ns 1, 2, 4An Outputs tf Fall Time 2V x 1V, 1.2 3.0 1.2 3.0 ns 1, 2, 4An Outputs

TA eb 40§Ct o a85§CT A eb 55§Ct o a125§C VCC e 4.5V–5.5V V CC e 4.5V–5.5V

16 Outputs Switching 16 Outputs Switching

tOHS Pin-to-Pin Skew 1.3 ns Figures 1, 2, 4(Notes 1, 2) LH/HL An to Bn tOHS Pin-to-Pin Skew 1.3 ns Figures 1, 2, 4(Notes 1, 2) LH/HL Bn to An tPS Duty Cycle Skew 2.0 ns Figures 1, 2, 4(Notes 1, 2) Bn to An tPS Duty Cycle Skew 2.0 ns Figures 1, 2, 4(Notes 1, 2) An to Bn VME Extended Skew Symbol Parameter 74ETL 54ETL Units Conditions TA eb 40§Ct o a85§CT A eb 55§Ct o a125§C VCC e 4.5V–5.5V V CC e 4.5V–5.5V tPV Device-to-Device Skew LH/HL 4.0 ns Figures 1, 2, 4(Notes 1, 2) Transitions Bn to An tCP Device-to-Device Skew LH/HL 2.5 ns Figures 1, 2, 4(Notes 1, 2) Transitions An to Bn tCP Change in Propagation Delay 4.0 ns Figures 1, 2, 4(Note 1, 3) with Load Bn to An tCPV Device-to-Device, Change (Notes 1, 2, 3) in Propagation Delay with 6.0 ns Figures 1, 2, 4 with Load Bn to An Note 1: Skew is defined as the absolute difference in delay between two outputs. The specification applies to any outputs switching HIGH to LOW, LOW to HIGH, or any combination switching HIGH-to-LOW or LOW-to-HIGH. This specification is guaranteed but not tested. Note 2: This is measured with both devices at the same value of V CC g1% and with package temperature differences of 20 §C from each other. Note 3: This is measured with Rx in Figure 1 at 13 X for one unit and at 56 X for the other unit. Capacitance Symbol Parameter Typ Max Units Conditions, T A e 25§C CIN Input Capacitance 5 8 pF V CC e 0.0V (OE n, DIR) CI/O (Note 1) Output Capacitance 9 12 pF V CC e 5.0V (A n) Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012.

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 54/74 ETL16245 SS C X Temperature Range Family Special Variations VME74 e Commercial X e Devices shipped in 13 × reels VME54 e Military QB e Military grade device with environmental and burn-in Device Type processing shipped in tubes. Package Code Temperature RangeSS e Small Outline (SSOP) C e CommercialFPFP e Fine Pitch Flatpak (b40§Ct o a85§C) M e Military ( b55§Ct o a125§C) Physical Dimensions inches (millimeters) 48-Lead SSOP (0.300 × Wide) (SS)

54/74ETL16245 16-Bit Data Transceiver with Incident Wave Switching Physical Dimensions inches (millimeters) (Continued) 48-Pin Ceramic Flatpak (FPFP) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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