54AC16240 TI | Alldatasheet

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54AC16240, 74AC16240 16-BIT BUS DRIVERS WITH 3-STATE OUTPUTS SCAS234B – JULY 1990 – REVISED OCTOBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Members of the Texas Instruments Widebus  Family /C00683-State Outputs Drive Bus Lines or Buffer Memory Address Registers /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise /C0068EPIC  (Enhanced-Performance Implanted CMOS) 1-mm Process /C0068500-mA Typical Latch-Up Immunity at 125°C /C0068Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacings

description

The ’AC16240 are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide inverting outputs and symmetrical active-low output-enable (OE ) inputs. The 74AC16240 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed circuit board area. The 54AC16240 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16240 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 4-bit buffer) INPUTS OUTPUT OE A Y L H L L LH H X Z Copyright  1996, Texas Instruments IncorporatedUNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 V CC 4Y1 4Y2 GND 4Y3 4Y4 4OE 2OE 1A1 1A2 GND 1A3 1A4 V CC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V CC 4A1 4A2 GND 4A3 4A4 3OE 54AC16240 . . . WD PACKAGE 74AC16240 . . . DL PACKAGE (TOP VIEW)

54AC16240, 74AC16240 16-BIT BUS DRIVERS WITH 3-STATE OUTPUTS SCAS234B – JULY 1990 – REVISED OCTOBER 1996

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logic symbol† 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 EN1 EN4 1OE 2OE 3OE 4OE EN2 EN3 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

54AC16240, 74AC16240 16-BIT BUS DRIVERS WITH 3-STATE OUTPUTS SCAS234B – JULY 1990 – REVISED OCTOBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

54AC16240, 74AC16240 16-BIT BUS DRIVERS WITH 3-STATE OUTPUTS SCAS234B – JULY 1990 – REVISED OCTOBER 1996

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recommended operating conditions (see Note 3) 54AC16240 74AC16240 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 3 5 5.5 3 5 5.5 V VCC = 3 V 2.1 2.1 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V –4 –4 IOH High-level output current VCC = 4.5 V –24 –24 mA VCC = 5.5 V –24 –24 VCC = 3 V 12 12 IOL Low-level output current VCC = 4.5 V 24 24 mA VCC = 5.5 V 24 24 Dt/Dv Input transition rise or fall rate 0 10 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C 54AC16240 74AC16240 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 3 V 2.9 2.9 2.9 IOH = –50 mA 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 VOH IOH = –4 mA 3 V 2.58 2.48 2.48 V I2 4 A 4.5 V 3.94 3.8 3.8 IOH = –24 mA 5.5 V 4.94 4.8 4.8 IOH = –75 mA† 5.5 V 3.85 3.85 3 V 0.1 0.1 0.1 IOL = 50 mA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 VOL IOL = 12 mA 3 V 0.36 0.44 0.44 V IOL =2 4m A 4.5 V 0.36 0.44 0.44 IOL = 24 mA 5.5 V 0.36 0.44 0.44 IOL = 75 mA† 5.5 V 1.65 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 mA IOZ VO = VCC or GND 5.5 V ±0.5 ±5 ±5 mA ICC VI = VCC or GND, IO = 0 5.5 V 8 80 80 mA C i VI = VCC or GND 5 V 4.5 pF C o VO = VCC or GND 5 V 12 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

54AC16240, 74AC16240 16-BIT BUS DRIVERS WITH 3-STATE OUTPUTS SCAS234B – JULY 1990 – REVISED OCTOBER 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC16240 74AC16240 UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT tPLH A Y ns tPHL A Y ns tPZH OE Y ns tPZL OE Y ns tPHZ OE Y ns tPLZ OE Y ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC16240 74AC16240 UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT tPLH A Y ns tPHL A Y ns tPZH OE Y ns tPZL OE Y ns tPHZ OE Y ns tPLZ OE Y ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C d Power dissipation capacitanceper latch Outputs enabled C L =5 0pF f=1M H z pFC pd Pow er dissipation capacitance per latch Outputs disabled C L = 50 pF, f = 1 MH z pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

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