54AC11534_09 TI1 | Alldatasheet
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/C0053/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052/C0044/C0032/C0055/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052 /C0079/C0067/C0084/C0065/C0076/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0032/C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS037A − JULY 1987 − REVISED APRIL 1993 /C0261 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 Copyright 1993, Texas Instruments Incorporated 2−1
- Eight D-Type Flip-Flops in a Single Package
- 3-State Bus Driving Inverting Outputs
- Full Parallel Access for Loading
- Inputs Are TTL-Voltage Compatible
- Flow-Through Architecture to Optimize PCB Layout
- Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
- EPIC/C0116 (Enhanced-Performance Implanted CMOS) 1-/C0109m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
These eight flip-flops feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′AC11534 are edge- triggered, D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the complement of the logic levels at the D inputs. The ′AC11534 is functionally equivalent to the ′AC11374 except for having inverted outputs. An output-control input (OC) is used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output control (OC does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 54AC11534 is characterized for operation over the full military temperature range of −55°C to 125°C. The 74AC11534 is characterized for operation from − 40°C to 85°C. GND GND GND GND OC V CC VCC CLK 54AC11534 . . . JT PACKAGE 74AC11534 . . . DW OR NT PACKAGE (TOP VIEW) 321 13 14 CLK NC OC NC 15 16 17 18 GND GND NC GND GND NC 54AC11534 . . . FK PACKAGE (TOP VIEW) 28 27 26 CCV CCV INPUTS OUTPUT Q L L L H FUNCTION TABLE (each filp-flop) OC CLK D L X H L X X L H Q Z NC − No internal connection /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 EPIC is a trademark of Texas Instruments Incorporated.
/C0053/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052/C0044/C0032/C0055/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052 /C0079/C0067/C0084/C0065/C0076/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0032/C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS037A − JULY 1987 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−2 logic symbol† logic diagram (positive logic) CLK OC EN CLK OC † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
/C0053/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052/C0044/C0032/C0055/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052 /C0079/C0067/C0084/C0065/C0076/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0032/C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS037A − JULY 1987 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−3 recommended operating conditions 54AC11534 74AC11534 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 3 5 5.5 3 5 5.5 V VCC = 3 V 2.1 2.1 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 5.5 V 3.85 3.85 V VCC = 3 V 0.9 0.9 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVIL Low-level input voltage VCC = 5.5 V 1.65 1.65 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V −4 −4 IOH High-level output current VCC = 4.5 V −2 4 −2 4 mAIOH High-level output current VCC = 5.5 V −24 −24 mA VCC = 3 V 12 12 IOL Low-level output current VCC = 4.5 V 24 24 mAIOL Low-level output current VCC = 5.5 V 24 24 mA /C0068t//C0068v Input transition rise or fall rate OC 0 5 0 5 ns/V/C0068t//C0068v Input transition rise or fall rate D 0 10 0 10 ns/V TA Operating free-air temperature −55 125 −4 0 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C 54AC11534 74AC11534 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 3 V 2.9 2.9 2.9 IOH = − 50 /C0109A 4.5 V 4.4 4.4 4.4IOH = − 50 /C0109A 5.5 V 5.4 5.4 5.4 VOH IOH = − 4 mA 3 V 2.58 2.4 2.48 VVOH IOH = − 24 mA 4.5 V 3.94 3.7 3.8 V IOH = − 24 mA 5.5 V 4.94 4.7 4.8 IOH = − 50 mA/C0123 5.5 V 3.85 IOH = − 75 mA/C0123 5.5 V 3.85 3 V 0.1 0.1 0.1 IOL = 50 /C0109A 4.5 V 0.1 0.1 0.1IOL = 50 /C0109A 5.5 V 0.1 0.1 0.1 VOL IOL = 12 mA 3 V 0.36 0.5 0.44 VVOL IOL = 24 mA 4.5 V 0.36 0.5 0.44 V IOL = 24 mA 5.5 V 0.36 0.5 0.44 IOL = 50 mA/C0123 5.5 V 1.65 IOL = 75 mA/C0123 5.5 V 1.65 IOZ VO = VCC or GND 5.5 V ± 0.5 ± 10 ± 5 /C0109A II VI = VCC or GND 5.5 V ± 0.1 ± 1 ± 1 /C0109A ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 /C0109A C i VI = VCC or GND 5 V 4 pF C o VO = VCC or GND 5 V 10 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
/C0053/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052/C0044/C0032/C0055/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052 /C0079/C0067/C0084/C0065/C0076/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0032/C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS037A − JULY 1987 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−4 timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C 54AC11534 74AC11534 UNITMIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 0 50 0 50 0 50 MHz tw Pulse duration, CLK low or CLK high 10 10 10 ns tsu Setup time, data before CLK ↑ 3.5 3.5 3.5 ns th Hold time, data after CLK ↑ 5.5 5.5 5.5 ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C 54AC11534 74AC11534 UNITMIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 0 75 0 75 0 75 MHz tw Pulse duration, CLK low or CLK high 6.5 6.5 6.5 ns tsu Setup time, data before CLK ↑ 3.5 3.5 3.5 ns th Hold time, data after CLK ↑ 4.5 4.5 4.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC11534 74AC11534 UNITPARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 50 75 50 50 MHz tPLH CLK Q nstPHL tPZH OC Q nstPZL tPHZ OC Q ns tPLZ ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC11534 74AC11534 UNITPARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 75 100 75 75 MHz tPLH CLK Q nstPHL tPZH OC Q nstPZL tPHZ OC Q ns tPLZ ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per flip-flop Outputs enabled C L = 50 pF, f = 1 MHz pFC pd Power dissipation capacitance per flip-flop Outputs disabled C L = 50 pF, f = 1 MHz pF
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
/C0053/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052/C0044/C0032/C0055/C0052/C0065/C0067/C0049/C0049/C0053/C0051/C0052 /C0079/C0067/C0084/C0065/C0076/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0032/C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS037A − JULY 1987 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−6
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